OvmfPkg/PlatformPei/Platform.c

   1 /**@file
   2   Platform PEI driver
   3
   4   Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
   5   Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
   6
   7   SPDX-License-Identifier: BSD-2-Clause-Patent
   8
   9 **/
  10
  11 //
  12 // The package level header files this module uses
  13 //
  14 #include <PiPei.h>
  15
  16 //
  17 // The Library classes this module consumes
  18 //
  19 #include <Library/BaseLib.h>
  20 #include <Library/DebugLib.h>
  21 #include <Library/HobLib.h>
  22 #include <Library/IoLib.h>
  23 #include <Library/MemoryAllocationLib.h>
  24 #include <Library/PcdLib.h>
  25 #include <Library/PciLib.h>
  26 #include <Library/PeimEntryPoint.h>
  27 #include <Library/PeiServicesLib.h>
  28 #include <Library/QemuFwCfgLib.h>
  29 #include <Library/QemuFwCfgS3Lib.h>
  30 #include <Library/QemuFwCfgSimpleParserLib.h>
  31 #include <Library/ResourcePublicationLib.h>
  32 #include <Ppi/MasterBootMode.h>
  33 #include <IndustryStandard/I440FxPiix4.h>
  34 #include <IndustryStandard/Microvm.h>
  35 #include <IndustryStandard/Pci22.h>
  36 #include <IndustryStandard/Q35MchIch9.h>
  37 #include <IndustryStandard/QemuCpuHotplug.h>
  38 #include <OvmfPlatforms.h>
  39
  40 #include "Platform.h"
  41 #include "Cmos.h"
  42
  43 EFI_PEI_PPI_DESCRIPTOR  mPpiBootMode[] = {
  44   {
  45     EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  46     &gEfiPeiMasterBootModePpiGuid,
  47     NULL
  48   }
  49 };
  50
  51 UINT16  mHostBridgeDevId;
  52
  53 EFI_BOOT_MODE  mBootMode = BOOT_WITH_FULL_CONFIGURATION;
  54
  55 BOOLEAN  mS3Supported = FALSE;
  56
  57 UINT32  mMaxCpuCount;
  58
  59 VOID
  60 AddIoMemoryBaseSizeHob (
  61   EFI_PHYSICAL_ADDRESS  MemoryBase,
  62   UINT64                MemorySize
  63   )
  64 {
  65   BuildResourceDescriptorHob (
  66     EFI_RESOURCE_MEMORY_MAPPED_IO,
  67     EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  68     EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  69     EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  70     EFI_RESOURCE_ATTRIBUTE_TESTED,
  71     MemoryBase,
  72     MemorySize
  73     );
  74 }
  75
  76 VOID
  77 AddReservedMemoryBaseSizeHob (
  78   EFI_PHYSICAL_ADDRESS  MemoryBase,
  79   UINT64                MemorySize,
  80   BOOLEAN               Cacheable
  81   )
  82 {
  83   BuildResourceDescriptorHob (
  84     EFI_RESOURCE_MEMORY_RESERVED,
  85     EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  86     EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  87     EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  88     (Cacheable ?
  89      EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
  90      EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
  91      EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
  92      0
  93     ) |
  94     EFI_RESOURCE_ATTRIBUTE_TESTED,
  95     MemoryBase,
  96     MemorySize
  97     );
  98 }
  99
 100 VOID
 101 AddIoMemoryRangeHob (
 102   EFI_PHYSICAL_ADDRESS  MemoryBase,
 103   EFI_PHYSICAL_ADDRESS  MemoryLimit
 104   )
 105 {
 106   AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 107 }
 108
 109 VOID
 110 AddMemoryBaseSizeHob (
 111   EFI_PHYSICAL_ADDRESS  MemoryBase,
 112   UINT64                MemorySize
 113   )
 114 {
 115   BuildResourceDescriptorHob (
 116     EFI_RESOURCE_SYSTEM_MEMORY,
 117     EFI_RESOURCE_ATTRIBUTE_PRESENT |
 118     EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 119     EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 120     EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 121     EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 122     EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
 123     EFI_RESOURCE_ATTRIBUTE_TESTED,
 124     MemoryBase,
 125     MemorySize
 126     );
 127 }
 128
 129 VOID
 130 AddMemoryRangeHob (
 131   EFI_PHYSICAL_ADDRESS  MemoryBase,
 132   EFI_PHYSICAL_ADDRESS  MemoryLimit
 133   )
 134 {
 135   AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 136 }
 137
 138 VOID
 139 MemMapInitialization (
 140   VOID
 141   )
 142 {
 143   UINT64         PciIoBase;
 144   UINT64         PciIoSize;
 145   RETURN_STATUS  PcdStatus;
 146   UINT32         TopOfLowRam;
 147   UINT64         PciExBarBase;
 148   UINT32         PciBase;
 149   UINT32         PciSize;
 150
 151   PciIoBase = 0xC000;
 152   PciIoSize = 0x4000;
 153
 154   //
 155   // Video memory + Legacy BIOS region
 156   //
 157   AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
 158
 159   if (mHostBridgeDevId == 0xffff /* microvm */) {
 160     AddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB);
 161     AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */
 162     AddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */
 163     return;
 164   }
 165
 166   TopOfLowRam  = GetSystemMemorySizeBelow4gb ();
 167   PciExBarBase = 0;
 168   if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 169     //
 170     // The MMCONFIG area is expected to fall between the top of low RAM and
 171     // the base of the 32-bit PCI host aperture.
 172     //
 173     PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);
 174     ASSERT (TopOfLowRam <= PciExBarBase);
 175     ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
 176     PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
 177   } else {
 178     ASSERT (TopOfLowRam <= mQemuUc32Base);
 179     PciBase = mQemuUc32Base;
 180   }
 181
 182   //
 183   // address       purpose   size
 184   // ------------  --------  -------------------------
 185   // max(top, 2g)  PCI MMIO  0xFC000000 - max(top, 2g)
 186   // 0xFC000000    gap                           44 MB
 187   // 0xFEC00000    IO-APIC                        4 KB
 188   // 0xFEC01000    gap                         1020 KB
 189   // 0xFED00000    HPET                           1 KB
 190   // 0xFED00400    gap                          111 KB
 191   // 0xFED1C000    gap (PIIX4) / RCRB (ICH9)     16 KB
 192   // 0xFED20000    gap                          896 KB
 193   // 0xFEE00000    LAPIC                          1 MB
 194   //
 195   PciSize = 0xFC000000 - PciBase;
 196   AddIoMemoryBaseSizeHob (PciBase, PciSize);
 197   PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);
 198   ASSERT_RETURN_ERROR (PcdStatus);
 199   PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize);
 200   ASSERT_RETURN_ERROR (PcdStatus);
 201
 202   AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
 203   AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
 204   if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 205     AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
 206     //
 207     // Note: there should be an
 208     //
 209     //   AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
 210     //
 211     // call below, just like the one above for RCBA. However, Linux insists
 212     // that the MMCONFIG area be marked in the E820 or UEFI memory map as
 213     // "reserved memory" -- Linux does not content itself with a simple gap
 214     // in the memory map wherever the MCFG ACPI table points to.
 215     //
 216     // This appears to be a safety measure. The PCI Firmware Specification
 217     // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can
 218     // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory
 219     // [...]". (Emphasis added here.)
 220     //
 221     // Normally we add memory resource descriptor HOBs in
 222     // QemuInitializeRam(), and pre-allocate from those with memory
 223     // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area
 224     // is most definitely not RAM; so, as an exception, cover it with
 225     // uncacheable reserved memory right here.
 226     //
 227     AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);
 228     BuildMemoryAllocationHob (
 229       PciExBarBase,
 230       SIZE_256MB,
 231       EfiReservedMemoryType
 232       );
 233   }
 234
 235   AddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), SIZE_1MB);
 236
 237   //
 238   // On Q35, the IO Port space is available for PCI resource allocations from
 239   // 0x6000 up.
 240   //
 241   if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 242     PciIoBase = 0x6000;
 243     PciIoSize = 0xA000;
 244     ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);
 245   }
 246
 247   //
 248   // Add PCI IO Port space available for PCI resource allocations.
 249   //
 250   BuildResourceDescriptorHob (
 251     EFI_RESOURCE_IO,
 252     EFI_RESOURCE_ATTRIBUTE_PRESENT     |
 253     EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
 254     PciIoBase,
 255     PciIoSize
 256     );
 257   PcdStatus = PcdSet64S (PcdPciIoBase, PciIoBase);
 258   ASSERT_RETURN_ERROR (PcdStatus);
 259   PcdStatus = PcdSet64S (PcdPciIoSize, PciIoSize);
 260   ASSERT_RETURN_ERROR (PcdStatus);
 261 }
 262
 263 #define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName)                   \
 264           do {                                                      \
 265             BOOLEAN       Setting;                                  \
 266             RETURN_STATUS PcdStatus;                                \
 267                                                                     \
 268             if (!RETURN_ERROR (QemuFwCfgParseBool (                 \
 269                               "opt/ovmf/" #TokenName, &Setting))) { \
 270               PcdStatus = PcdSetBoolS (TokenName, Setting);         \
 271               ASSERT_RETURN_ERROR (PcdStatus);                      \
 272             }                                                       \
 273           } while (0)
 274
 275 VOID
 276 NoexecDxeInitialization (
 277   VOID
 278   )
 279 {
 280   UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);
 281 }
 282
 283 VOID
 284 PciExBarInitialization (
 285   VOID
 286   )
 287 {
 288   union {
 289     UINT64    Uint64;
 290     UINT32    Uint32[2];
 291   } PciExBarBase;
 292
 293   //
 294   // We only support the 256MB size for the MMCONFIG area:
 295   // 256 buses * 32 devices * 8 functions * 4096 bytes config space.
 296   //
 297   // The masks used below enforce the Q35 requirements that the MMCONFIG area
 298   // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.
 299   //
 300   // Note that (b) also ensures that the minimum address width we have
 301   // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice
 302   // for DXE's page tables to cover the MMCONFIG area.
 303   //
 304   PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);
 305   ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);
 306   ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);
 307
 308   //
 309   // Clear the PCIEXBAREN bit first, before programming the high register.
 310   //
 311   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);
 312
 313   //
 314   // Program the high register. Then program the low register, setting the
 315   // MMCONFIG area size and enabling decoding at once.
 316   //
 317   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);
 318   PciWrite32 (
 319     DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),
 320     PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN
 321     );
 322 }
 323
 324 VOID
 325 MicrovmInitialization (
 326   VOID
 327   )
 328 {
 329   FIRMWARE_CONFIG_ITEM  FdtItem;
 330   UINTN                 FdtSize;
 331   UINTN                 FdtPages;
 332   EFI_STATUS            Status;
 333   UINT64                *FdtHobData;
 334   VOID                  *NewBase;
 335
 336   Status = QemuFwCfgFindFile ("etc/fdt", &FdtItem, &FdtSize);
 337   if (EFI_ERROR (Status)) {
 338     DEBUG ((DEBUG_INFO, "%a: no etc/fdt found in fw_cfg\n", __FUNCTION__));
 339     return;
 340   }
 341
 342   FdtPages = EFI_SIZE_TO_PAGES (FdtSize);
 343   NewBase  = AllocatePages (FdtPages);
 344   if (NewBase == NULL) {
 345     DEBUG ((DEBUG_INFO, "%a: AllocatePages failed\n", __FUNCTION__));
 346     return;
 347   }
 348
 349   QemuFwCfgSelectItem (FdtItem);
 350   QemuFwCfgReadBytes (FdtSize, NewBase);
 351
 352   FdtHobData = BuildGuidHob (&gFdtHobGuid, sizeof (*FdtHobData));
 353   if (FdtHobData == NULL) {
 354     DEBUG ((DEBUG_INFO, "%a: BuildGuidHob failed\n", __FUNCTION__));
 355     return;
 356   }
 357
 358   DEBUG ((
 359     DEBUG_INFO,
 360     "%a: fdt at 0x%x (size %d)\n",
 361     __FUNCTION__,
 362     NewBase,
 363     FdtSize
 364     ));
 365   *FdtHobData = (UINTN)NewBase;
 366 }
 367
 368 VOID
 369 MiscInitialization (
 370   VOID
 371   )
 372 {
 373   UINTN          PmCmd;
 374   UINTN          Pmba;
 375   UINT32         PmbaAndVal;
 376   UINT32         PmbaOrVal;
 377   UINTN          AcpiCtlReg;
 378   UINT8          AcpiEnBit;
 379   RETURN_STATUS  PcdStatus;
 380
 381   //
 382   // Disable A20 Mask
 383   //
 384   IoOr8 (0x92, BIT1);
 385
 386   //
 387   // Build the CPU HOB with guest RAM size dependent address width and 16-bits
 388   // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
 389   // S3 resume as well, so we build it unconditionally.)
 390   //
 391   BuildCpuHob (mPhysMemAddressWidth, 16);
 392
 393   //
 394   // Determine platform type and save Host Bridge DID to PCD
 395   //
 396   switch (mHostBridgeDevId) {
 397     case INTEL_82441_DEVICE_ID:
 398       PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
 399       Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
 400       PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;
 401       PmbaOrVal  = PIIX4_PMBA_VALUE;
 402       AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
 403       AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;
 404       break;
 405     case INTEL_Q35_MCH_DEVICE_ID:
 406       PmCmd      = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
 407       Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
 408       PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;
 409       PmbaOrVal  = ICH9_PMBASE_VALUE;
 410       AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
 411       AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;
 412       break;
 413     case 0xffff: /* microvm */
 414       DEBUG ((DEBUG_INFO, "%a: microvm\n", __FUNCTION__));
 415       MicrovmInitialization ();
 416       PcdStatus = PcdSet16S (
 417                     PcdOvmfHostBridgePciDevId,
 418                     MICROVM_PSEUDO_DEVICE_ID
 419                     );
 420       ASSERT_RETURN_ERROR (PcdStatus);
 421       return;
 422     case CLOUDHV_DEVICE_ID:
 423       DEBUG ((DEBUG_INFO, "%a: Cloud Hypervisor host bridge\n", __FUNCTION__));
 424       PcdStatus = PcdSet16S (
 425                     PcdOvmfHostBridgePciDevId,
 426                     CLOUDHV_DEVICE_ID
 427                     );
 428       ASSERT_RETURN_ERROR (PcdStatus);
 429       return;
 430     default:
 431       DEBUG ((
 432         DEBUG_ERROR,
 433         "%a: Unknown Host Bridge Device ID: 0x%04x\n",
 434         __FUNCTION__,
 435         mHostBridgeDevId
 436         ));
 437       ASSERT (FALSE);
 438       return;
 439   }
 440
 441   PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
 442   ASSERT_RETURN_ERROR (PcdStatus);
 443
 444   //
 445   // If the appropriate IOspace enable bit is set, assume the ACPI PMBA has
 446   // been configured and skip the setup here. This matches the logic in
 447   // AcpiTimerLibConstructor ().
 448   //
 449   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
 450     //
 451     // The PEI phase should be exited with fully accessibe ACPI PM IO space:
 452     // 1. set PMBA
 453     //
 454     PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);
 455
 456     //
 457     // 2. set PCICMD/IOSE
 458     //
 459     PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
 460
 461     //
 462     // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
 463     //
 464     PciOr8 (AcpiCtlReg, AcpiEnBit);
 465   }
 466
 467   if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 468     //
 469     // Set Root Complex Register Block BAR
 470     //
 471     PciWrite32 (
 472       POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),
 473       ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN
 474       );
 475
 476     //
 477     // Set PCI Express Register Range Base Address
 478     //
 479     PciExBarInitialization ();
 480   }
 481 }
 482
 483 VOID
 484 BootModeInitialization (
 485   VOID
 486   )
 487 {
 488   EFI_STATUS  Status;
 489
 490   if (CmosRead8 (0xF) == 0xFE) {
 491     mBootMode = BOOT_ON_S3_RESUME;
 492   }
 493
 494   CmosWrite8 (0xF, 0x00);
 495
 496   Status = PeiServicesSetBootMode (mBootMode);
 497   ASSERT_EFI_ERROR (Status);
 498
 499   Status = PeiServicesInstallPpi (mPpiBootMode);
 500   ASSERT_EFI_ERROR (Status);
 501 }
 502
 503 VOID
 504 ReserveEmuVariableNvStore (
 505   )
 506 {
 507   EFI_PHYSICAL_ADDRESS  VariableStore;
 508   RETURN_STATUS         PcdStatus;
 509
 510   //
 511   // Allocate storage for NV variables early on so it will be
 512   // at a consistent address.  Since VM memory is preserved
 513   // across reboots, this allows the NV variable storage to survive
 514   // a VM reboot.
 515   //
 516   VariableStore =
 517     (EFI_PHYSICAL_ADDRESS)(UINTN)
 518     AllocateRuntimePages (
 519       EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))
 520       );
 521   DEBUG ((
 522     DEBUG_INFO,
 523     "Reserved variable store memory: 0x%lX; size: %dkb\n",
 524     VariableStore,
 525     (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
 526     ));
 527   PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);
 528   ASSERT_RETURN_ERROR (PcdStatus);
 529 }
 530
 531 VOID
 532 DebugDumpCmos (
 533   VOID
 534   )
 535 {
 536   UINT32  Loop;
 537
 538   DEBUG ((DEBUG_INFO, "CMOS:\n"));
 539
 540   for (Loop = 0; Loop < 0x80; Loop++) {
 541     if ((Loop % 0x10) == 0) {
 542       DEBUG ((DEBUG_INFO, "%02x:", Loop));
 543     }
 544
 545     DEBUG ((DEBUG_INFO, " %02x", CmosRead8 (Loop)));
 546     if ((Loop % 0x10) == 0xf) {
 547       DEBUG ((DEBUG_INFO, "\n"));
 548     }
 549   }
 550 }
 551
 552 VOID
 553 S3Verification (
 554   VOID
 555   )
 556 {
 557  #if defined (MDE_CPU_X64)
 558   if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {
 559     DEBUG ((
 560       DEBUG_ERROR,
 561       "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n",
 562       __FUNCTION__
 563       ));
 564     DEBUG ((
 565       DEBUG_ERROR,
 566       "%a: Please disable S3 on the QEMU command line (see the README),\n",
 567       __FUNCTION__
 568       ));
 569     DEBUG ((
 570       DEBUG_ERROR,
 571       "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n",
 572       __FUNCTION__
 573       ));
 574     ASSERT (FALSE);
 575     CpuDeadLoop ();
 576   }
 577
 578  #endif
 579 }
 580
 581 VOID
 582 Q35BoardVerification (
 583   VOID
 584   )
 585 {
 586   if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 587     return;
 588   }
 589
 590   DEBUG ((
 591     DEBUG_ERROR,
 592     "%a: no TSEG (SMRAM) on host bridge DID=0x%04x; "
 593     "only DID=0x%04x (Q35) is supported\n",
 594     __FUNCTION__,
 595     mHostBridgeDevId,
 596     INTEL_Q35_MCH_DEVICE_ID
 597     ));
 598   ASSERT (FALSE);
 599   CpuDeadLoop ();
 600 }
 601
 602 /**
 603   Fetch the boot CPU count and the possible CPU count from QEMU, and expose
 604   them to UefiCpuPkg modules. Set the mMaxCpuCount variable.
 605 **/
 606 VOID
 607 MaxCpuCountInitialization (
 608   VOID
 609   )
 610 {
 611   UINT16         BootCpuCount;
 612   RETURN_STATUS  PcdStatus;
 613
 614   //
 615   // Try to fetch the boot CPU count.
 616   //
 617   QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount);
 618   BootCpuCount = QemuFwCfgRead16 ();
 619   if (BootCpuCount == 0) {
 620     //
 621     // QEMU doesn't report the boot CPU count. (BootCpuCount == 0) will let
 622     // MpInitLib count APs up to (PcdCpuMaxLogicalProcessorNumber - 1), or
 623     // until PcdCpuApInitTimeOutInMicroSeconds elapses (whichever is reached
 624     // first).
 625     //
 626     DEBUG ((DEBUG_WARN, "%a: boot CPU count unavailable\n", __FUNCTION__));
 627     mMaxCpuCount = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
 628   } else {
 629     //
 630     // We will expose BootCpuCount to MpInitLib. MpInitLib will count APs up to
 631     // (BootCpuCount - 1) precisely, regardless of timeout.
 632     //
 633     // Now try to fetch the possible CPU count.
 634     //
 635     UINTN   CpuHpBase;
 636     UINT32  CmdData2;
 637
 638     CpuHpBase = ((mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) ?
 639                  ICH9_CPU_HOTPLUG_BASE : PIIX4_CPU_HOTPLUG_BASE);
 640
 641     //
 642     // If only legacy mode is available in the CPU hotplug register block, or
 643     // the register block is completely missing, then the writes below are
 644     // no-ops.
 645     //
 646     // 1. Switch the hotplug register block to modern mode.
 647     //
 648     IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0);
 649     //
 650     // 2. Select a valid CPU for deterministic reading of
 651     //    QEMU_CPUHP_R_CMD_DATA2.
 652     //
 653     //    CPU#0 is always valid; it is the always present and non-removable
 654     //    BSP.
 655     //
 656     IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0);
 657     //
 658     // 3. Send a command after which QEMU_CPUHP_R_CMD_DATA2 is specified to
 659     //    read as zero, and which does not invalidate the selector. (The
 660     //    selector may change, but it must not become invalid.)
 661     //
 662     //    Send QEMU_CPUHP_CMD_GET_PENDING, as it will prove useful later.
 663     //
 664     IoWrite8 (CpuHpBase + QEMU_CPUHP_W_CMD, QEMU_CPUHP_CMD_GET_PENDING);
 665     //
 666     // 4. Read QEMU_CPUHP_R_CMD_DATA2.
 667     //
 668     //    If the register block is entirely missing, then this is an unassigned
 669     //    IO read, returning all-bits-one.
 670     //
 671     //    If only legacy mode is available, then bit#0 stands for CPU#0 in the
 672     //    "CPU present bitmap". CPU#0 is always present.
 673     //
 674     //    Otherwise, QEMU_CPUHP_R_CMD_DATA2 is either still reserved (returning
 675     //    all-bits-zero), or it is specified to read as zero after the above
 676     //    steps. Both cases confirm modern mode.
 677     //
 678     CmdData2 = IoRead32 (CpuHpBase + QEMU_CPUHP_R_CMD_DATA2);
 679     DEBUG ((DEBUG_VERBOSE, "%a: CmdData2=0x%x\n", __FUNCTION__, CmdData2));
 680     if (CmdData2 != 0) {
 681       //
 682       // QEMU doesn't support the modern CPU hotplug interface. Assume that the
 683       // possible CPU count equals the boot CPU count (precluding hotplug).
 684       //
 685       DEBUG ((
 686         DEBUG_WARN,
 687         "%a: modern CPU hotplug interface unavailable\n",
 688         __FUNCTION__
 689         ));
 690       mMaxCpuCount = BootCpuCount;
 691     } else {
 692       //
 693       // Grab the possible CPU count from the modern CPU hotplug interface.
 694       //
 695       UINT32  Present, Possible, Selected;
 696
 697       Present  = 0;
 698       Possible = 0;
 699
 700       //
 701       // We've sent QEMU_CPUHP_CMD_GET_PENDING last; this ensures
 702       // QEMU_CPUHP_RW_CMD_DATA can now be read usefully. However,
 703       // QEMU_CPUHP_CMD_GET_PENDING may have selected a CPU with actual pending
 704       // hotplug events; therefore, select CPU#0 forcibly.
 705       //
 706       IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible);
 707
 708       do {
 709         UINT8  CpuStatus;
 710
 711         //
 712         // Read the status of the currently selected CPU. This will help with a
 713         // sanity check against "BootCpuCount".
 714         //
 715         CpuStatus = IoRead8 (CpuHpBase + QEMU_CPUHP_R_CPU_STAT);
 716         if ((CpuStatus & QEMU_CPUHP_STAT_ENABLED) != 0) {
 717           ++Present;
 718         }
 719
 720         //
 721         // Attempt to select the next CPU.
 722         //
 723         ++Possible;
 724         IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible);
 725         //
 726         // If the selection is successful, then the following read will return
 727         // the selector (which we know is positive at this point). Otherwise,
 728         // the read will return 0.
 729         //
 730         Selected = IoRead32 (CpuHpBase + QEMU_CPUHP_RW_CMD_DATA);
 731         ASSERT (Selected == Possible || Selected == 0);
 732       } while (Selected > 0);
 733
 734       //
 735       // Sanity check: fw_cfg and the modern CPU hotplug interface should
 736       // return the same boot CPU count.
 737       //
 738       if (BootCpuCount != Present) {
 739         DEBUG ((
 740           DEBUG_WARN,
 741           "%a: QEMU v2.7 reset bug: BootCpuCount=%d "
 742           "Present=%u\n",
 743           __FUNCTION__,
 744           BootCpuCount,
 745           Present
 746           ));
 747         //
 748         // The handling of QemuFwCfgItemSmpCpuCount, across CPU hotplug plus
 749         // platform reset (including S3), was corrected in QEMU commit
 750         // e3cadac073a9 ("pc: fix FW_CFG_NB_CPUS to account for -device added
 751         // CPUs", 2016-11-16), part of release v2.8.0.
 752         //
 753         BootCpuCount = (UINT16)Present;
 754       }
 755
 756       mMaxCpuCount = Possible;
 757     }
 758   }
 759
 760   DEBUG ((
 761     DEBUG_INFO,
 762     "%a: BootCpuCount=%d mMaxCpuCount=%u\n",
 763     __FUNCTION__,
 764     BootCpuCount,
 765     mMaxCpuCount
 766     ));
 767   ASSERT (BootCpuCount <= mMaxCpuCount);
 768
 769   PcdStatus = PcdSet32S (PcdCpuBootLogicalProcessorNumber, BootCpuCount);
 770   ASSERT_RETURN_ERROR (PcdStatus);
 771   PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, mMaxCpuCount);
 772   ASSERT_RETURN_ERROR (PcdStatus);
 773 }
 774
 775 /**
 776   Perform Platform PEI initialization.
 777
 778   @param  FileHandle      Handle of the file being invoked.
 779   @param  PeiServices     Describes the list of possible PEI Services.
 780
 781   @return EFI_SUCCESS     The PEIM initialized successfully.
 782
 783 **/
 784 EFI_STATUS
 785 EFIAPI
 786 InitializePlatform (
 787   IN       EFI_PEI_FILE_HANDLE  FileHandle,
 788   IN CONST EFI_PEI_SERVICES     **PeiServices
 789   )
 790 {
 791   EFI_STATUS  Status;
 792
 793   DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));
 794
 795   DebugDumpCmos ();
 796
 797   if (QemuFwCfgS3Enabled ()) {
 798     DEBUG ((DEBUG_INFO, "S3 support was detected on QEMU\n"));
 799     mS3Supported = TRUE;
 800     Status       = PcdSetBoolS (PcdAcpiS3Enable, TRUE);
 801     ASSERT_EFI_ERROR (Status);
 802   }
 803
 804   S3Verification ();
 805   BootModeInitialization ();
 806   AddressWidthInitialization ();
 807
 808   //
 809   // Query Host Bridge DID
 810   //
 811   mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
 812
 813   MaxCpuCountInitialization ();
 814
 815   if (FeaturePcdGet (PcdSmmSmramRequire)) {
 816     Q35BoardVerification ();
 817     Q35TsegMbytesInitialization ();
 818     Q35SmramAtDefaultSmbaseInitialization ();
 819   }
 820
 821   PublishPeiMemory ();
 822
 823   QemuUc32BaseInitialization ();
 824
 825   InitializeRamRegions ();
 826
 827   if (mBootMode != BOOT_ON_S3_RESUME) {
 828     if (!FeaturePcdGet (PcdSmmSmramRequire)) {
 829       ReserveEmuVariableNvStore ();
 830     }
 831
 832     PeiFvInitialization ();
 833     MemTypeInfoInitialization ();
 834     MemMapInitialization ();
 835     NoexecDxeInitialization ();
 836   }
 837
 838   InstallClearCacheCallback ();
 839   AmdSevInitialize ();
 840   MiscInitialization ();
 841   InstallFeatureControlCallback ();
 842
 843   return EFI_SUCCESS;
 844 }