OvmfPkg/PlatformPei/Platform.c

   1 /**@file
   2   Platform PEI driver
   3
   4   Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
   5   Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
   6
   7   This program and the accompanying materials
   8   are licensed and made available under the terms and conditions of the BSD License
   9   which accompanies this distribution.  The full text of the license may be found at
  10   http://opensource.org/licenses/bsd-license.php
  11
  12   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15 **/
  16
  17 //
  18 // The package level header files this module uses
  19 //
  20 #include <PiPei.h>
  21
  22 //
  23 // The Library classes this module consumes
  24 //
  25 #include <Library/BaseLib.h>
  26 #include <Library/DebugLib.h>
  27 #include <Library/HobLib.h>
  28 #include <Library/IoLib.h>
  29 #include <Library/MemoryAllocationLib.h>
  30 #include <Library/PcdLib.h>
  31 #include <Library/PciLib.h>
  32 #include <Library/PeimEntryPoint.h>
  33 #include <Library/PeiServicesLib.h>
  34 #include <Library/QemuFwCfgLib.h>
  35 #include <Library/ResourcePublicationLib.h>
  36 #include <Guid/MemoryTypeInformation.h>
  37 #include <Ppi/MasterBootMode.h>
  38 #include <IndustryStandard/Pci22.h>
  39 #include <OvmfPlatforms.h>
  40
  41 #include "Platform.h"
  42 #include "Cmos.h"
  43
  44 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
  45   { EfiACPIMemoryNVS,       0x004 },
  46   { EfiACPIReclaimMemory,   0x008 },
  47   { EfiReservedMemoryType,  0x004 },
  48   { EfiRuntimeServicesData, 0x024 },
  49   { EfiRuntimeServicesCode, 0x030 },
  50   { EfiBootServicesCode,    0x180 },
  51   { EfiBootServicesData,    0xF00 },
  52   { EfiMaxMemoryType,       0x000 }
  53 };
  54
  55
  56 EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {
  57   {
  58     EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  59     &gEfiPeiMasterBootModePpiGuid,
  60     NULL
  61   }
  62 };
  63
  64
  65 UINT16 mHostBridgeDevId;
  66
  67 EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
  68
  69 BOOLEAN mS3Supported = FALSE;
  70
  71
  72 VOID
  73 AddIoMemoryBaseSizeHob (
  74   EFI_PHYSICAL_ADDRESS        MemoryBase,
  75   UINT64                      MemorySize
  76   )
  77 {
  78   BuildResourceDescriptorHob (
  79     EFI_RESOURCE_MEMORY_MAPPED_IO,
  80       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  81       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  82       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  83       EFI_RESOURCE_ATTRIBUTE_TESTED,
  84     MemoryBase,
  85     MemorySize
  86     );
  87 }
  88
  89 VOID
  90 AddReservedMemoryBaseSizeHob (
  91   EFI_PHYSICAL_ADDRESS        MemoryBase,
  92   UINT64                      MemorySize,
  93   BOOLEAN                     Cacheable
  94   )
  95 {
  96   BuildResourceDescriptorHob (
  97     EFI_RESOURCE_MEMORY_RESERVED,
  98       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  99       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 100       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 101       (Cacheable ?
 102        EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 103        EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 104        EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
 105        0
 106        ) |
 107       EFI_RESOURCE_ATTRIBUTE_TESTED,
 108     MemoryBase,
 109     MemorySize
 110     );
 111 }
 112
 113 VOID
 114 AddIoMemoryRangeHob (
 115   EFI_PHYSICAL_ADDRESS        MemoryBase,
 116   EFI_PHYSICAL_ADDRESS        MemoryLimit
 117   )
 118 {
 119   AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 120 }
 121
 122
 123 VOID
 124 AddMemoryBaseSizeHob (
 125   EFI_PHYSICAL_ADDRESS        MemoryBase,
 126   UINT64                      MemorySize
 127   )
 128 {
 129   BuildResourceDescriptorHob (
 130     EFI_RESOURCE_SYSTEM_MEMORY,
 131       EFI_RESOURCE_ATTRIBUTE_PRESENT |
 132       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 133       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 134       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 135       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 136       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
 137       EFI_RESOURCE_ATTRIBUTE_TESTED,
 138     MemoryBase,
 139     MemorySize
 140     );
 141 }
 142
 143
 144 VOID
 145 AddMemoryRangeHob (
 146   EFI_PHYSICAL_ADDRESS        MemoryBase,
 147   EFI_PHYSICAL_ADDRESS        MemoryLimit
 148   )
 149 {
 150   AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 151 }
 152
 153
 154 VOID
 155 MemMapInitialization (
 156   VOID
 157   )
 158 {
 159   UINT64 PciIoBase;
 160   UINT64 PciIoSize;
 161
 162   PciIoBase = 0xC000;
 163   PciIoSize = 0x4000;
 164
 165   //
 166   // Create Memory Type Information HOB
 167   //
 168   BuildGuidDataHob (
 169     &gEfiMemoryTypeInformationGuid,
 170     mDefaultMemoryTypeInformation,
 171     sizeof(mDefaultMemoryTypeInformation)
 172     );
 173
 174   //
 175   // Video memory + Legacy BIOS region
 176   //
 177   AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
 178
 179   if (!mXen) {
 180     UINT32  TopOfLowRam;
 181     UINT64  PciExBarBase;
 182     UINT32  PciBase;
 183     UINT32  PciSize;
 184
 185     TopOfLowRam = GetSystemMemorySizeBelow4gb ();
 186     PciExBarBase = 0;
 187     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 188       //
 189       // The MMCONFIG area is expected to fall between the top of low RAM and
 190       // the base of the 32-bit PCI host aperture.
 191       //
 192       PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);
 193       ASSERT (TopOfLowRam <= PciExBarBase);
 194       ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
 195       PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
 196     } else {
 197       PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;
 198     }
 199
 200     //
 201     // address       purpose   size
 202     // ------------  --------  -------------------------
 203     // max(top, 2g)  PCI MMIO  0xFC000000 - max(top, 2g)
 204     // 0xFC000000    gap                           44 MB
 205     // 0xFEC00000    IO-APIC                        4 KB
 206     // 0xFEC01000    gap                         1020 KB
 207     // 0xFED00000    HPET                           1 KB
 208     // 0xFED00400    gap                          111 KB
 209     // 0xFED1C000    gap (PIIX4) / RCRB (ICH9)     16 KB
 210     // 0xFED20000    gap                          896 KB
 211     // 0xFEE00000    LAPIC                          1 MB
 212     //
 213     PciSize = 0xFC000000 - PciBase;
 214     AddIoMemoryBaseSizeHob (PciBase, PciSize);
 215     PcdSet64 (PcdPciMmio32Base, PciBase);
 216     PcdSet64 (PcdPciMmio32Size, PciSize);
 217     AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
 218     AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
 219     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 220       AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
 221       //
 222       // Note: there should be an
 223       //
 224       //   AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
 225       //
 226       // call below, just like the one above for RCBA. However, Linux insists
 227       // that the MMCONFIG area be marked in the E820 or UEFI memory map as
 228       // "reserved memory" -- Linux does not content itself with a simple gap
 229       // in the memory map wherever the MCFG ACPI table points to.
 230       //
 231       // This appears to be a safety measure. The PCI Firmware Specification
 232       // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can
 233       // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory
 234       // [...]". (Emphasis added here.)
 235       //
 236       // Normally we add memory resource descriptor HOBs in
 237       // QemuInitializeRam(), and pre-allocate from those with memory
 238       // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area
 239       // is most definitely not RAM; so, as an exception, cover it with
 240       // uncacheable reserved memory right here.
 241       //
 242       AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);
 243       BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,
 244         EfiReservedMemoryType);
 245     }
 246     AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
 247
 248     //
 249     // On Q35, the IO Port space is available for PCI resource allocations from
 250     // 0x6000 up.
 251     //
 252     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 253       PciIoBase = 0x6000;
 254       PciIoSize = 0xA000;
 255       ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);
 256     }
 257   }
 258
 259   //
 260   // Add PCI IO Port space available for PCI resource allocations.
 261   //
 262   BuildResourceDescriptorHob (
 263     EFI_RESOURCE_IO,
 264     EFI_RESOURCE_ATTRIBUTE_PRESENT     |
 265     EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
 266     PciIoBase,
 267     PciIoSize
 268     );
 269   PcdSet64 (PcdPciIoBase, PciIoBase);
 270   PcdSet64 (PcdPciIoSize, PciIoSize);
 271 }
 272
 273 EFI_STATUS
 274 GetNamedFwCfgBoolean (
 275   IN  CHAR8   *FwCfgFileName,
 276   OUT BOOLEAN *Setting
 277   )
 278 {
 279   EFI_STATUS           Status;
 280   FIRMWARE_CONFIG_ITEM FwCfgItem;
 281   UINTN                FwCfgSize;
 282   UINT8                Value[3];
 283
 284   Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);
 285   if (EFI_ERROR (Status)) {
 286     return Status;
 287   }
 288   if (FwCfgSize > sizeof Value) {
 289     return EFI_BAD_BUFFER_SIZE;
 290   }
 291   QemuFwCfgSelectItem (FwCfgItem);
 292   QemuFwCfgReadBytes (FwCfgSize, Value);
 293
 294   if ((FwCfgSize == 1) ||
 295       (FwCfgSize == 2 && Value[1] == '\n') ||
 296       (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {
 297     switch (Value[0]) {
 298       case '0':
 299       case 'n':
 300       case 'N':
 301         *Setting = FALSE;
 302         return EFI_SUCCESS;
 303
 304       case '1':
 305       case 'y':
 306       case 'Y':
 307         *Setting = TRUE;
 308         return EFI_SUCCESS;
 309
 310       default:
 311         break;
 312     }
 313   }
 314   return EFI_PROTOCOL_ERROR;
 315 }
 316
 317 #define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName)                   \
 318           do {                                                      \
 319             BOOLEAN Setting;                                        \
 320                                                                     \
 321             if (!EFI_ERROR (GetNamedFwCfgBoolean (                  \
 322                               "opt/ovmf/" #TokenName, &Setting))) { \
 323               PcdSetBool (TokenName, Setting);                      \
 324             }                                                       \
 325           } while (0)
 326
 327 VOID
 328 NoexecDxeInitialization (
 329   VOID
 330   )
 331 {
 332   UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);
 333   UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);
 334 }
 335
 336 VOID
 337 PciExBarInitialization (
 338   VOID
 339   )
 340 {
 341   union {
 342     UINT64 Uint64;
 343     UINT32 Uint32[2];
 344   } PciExBarBase;
 345
 346   //
 347   // We only support the 256MB size for the MMCONFIG area:
 348   // 256 buses * 32 devices * 8 functions * 4096 bytes config space.
 349   //
 350   // The masks used below enforce the Q35 requirements that the MMCONFIG area
 351   // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.
 352   //
 353   // Note that (b) also ensures that the minimum address width we have
 354   // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice
 355   // for DXE's page tables to cover the MMCONFIG area.
 356   //
 357   PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);
 358   ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);
 359   ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);
 360
 361   //
 362   // Clear the PCIEXBAREN bit first, before programming the high register.
 363   //
 364   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);
 365
 366   //
 367   // Program the high register. Then program the low register, setting the
 368   // MMCONFIG area size and enabling decoding at once.
 369   //
 370   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);
 371   PciWrite32 (
 372     DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),
 373     PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN
 374     );
 375 }
 376
 377 VOID
 378 MiscInitialization (
 379   VOID
 380   )
 381 {
 382   UINTN  PmCmd;
 383   UINTN  Pmba;
 384   UINT32 PmbaAndVal;
 385   UINT32 PmbaOrVal;
 386   UINTN  AcpiCtlReg;
 387   UINT8  AcpiEnBit;
 388
 389   //
 390   // Disable A20 Mask
 391   //
 392   IoOr8 (0x92, BIT1);
 393
 394   //
 395   // Build the CPU HOB with guest RAM size dependent address width and 16-bits
 396   // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
 397   // S3 resume as well, so we build it unconditionally.)
 398   //
 399   BuildCpuHob (mPhysMemAddressWidth, 16);
 400
 401   //
 402   // Determine platform type and save Host Bridge DID to PCD
 403   //
 404   switch (mHostBridgeDevId) {
 405     case INTEL_82441_DEVICE_ID:
 406       PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
 407       Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
 408       PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;
 409       PmbaOrVal  = PIIX4_PMBA_VALUE;
 410       AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
 411       AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;
 412       break;
 413     case INTEL_Q35_MCH_DEVICE_ID:
 414       PmCmd      = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
 415       Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
 416       PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;
 417       PmbaOrVal  = ICH9_PMBASE_VALUE;
 418       AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
 419       AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;
 420       break;
 421     default:
 422       DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
 423         __FUNCTION__, mHostBridgeDevId));
 424       ASSERT (FALSE);
 425       return;
 426   }
 427   PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
 428
 429   //
 430   // If the appropriate IOspace enable bit is set, assume the ACPI PMBA
 431   // has been configured (e.g., by Xen) and skip the setup here.
 432   // This matches the logic in AcpiTimerLibConstructor ().
 433   //
 434   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
 435     //
 436     // The PEI phase should be exited with fully accessibe ACPI PM IO space:
 437     // 1. set PMBA
 438     //
 439     PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);
 440
 441     //
 442     // 2. set PCICMD/IOSE
 443     //
 444     PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
 445
 446     //
 447     // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
 448     //
 449     PciOr8 (AcpiCtlReg, AcpiEnBit);
 450   }
 451
 452   if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 453     //
 454     // Set Root Complex Register Block BAR
 455     //
 456     PciWrite32 (
 457       POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),
 458       ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN
 459       );
 460
 461     //
 462     // Set PCI Express Register Range Base Address
 463     //
 464     PciExBarInitialization ();
 465   }
 466 }
 467
 468
 469 VOID
 470 BootModeInitialization (
 471   VOID
 472   )
 473 {
 474   EFI_STATUS    Status;
 475
 476   if (CmosRead8 (0xF) == 0xFE) {
 477     mBootMode = BOOT_ON_S3_RESUME;
 478   }
 479   CmosWrite8 (0xF, 0x00);
 480
 481   Status = PeiServicesSetBootMode (mBootMode);
 482   ASSERT_EFI_ERROR (Status);
 483
 484   Status = PeiServicesInstallPpi (mPpiBootMode);
 485   ASSERT_EFI_ERROR (Status);
 486 }
 487
 488
 489 VOID
 490 ReserveEmuVariableNvStore (
 491   )
 492 {
 493   EFI_PHYSICAL_ADDRESS VariableStore;
 494
 495   //
 496   // Allocate storage for NV variables early on so it will be
 497   // at a consistent address.  Since VM memory is preserved
 498   // across reboots, this allows the NV variable storage to survive
 499   // a VM reboot.
 500   //
 501   VariableStore =
 502     (EFI_PHYSICAL_ADDRESS)(UINTN)
 503       AllocateAlignedRuntimePages (
 504         EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),
 505         PcdGet32 (PcdFlashNvStorageFtwSpareSize)
 506         );
 507   DEBUG ((EFI_D_INFO,
 508           "Reserved variable store memory: 0x%lX; size: %dkb\n",
 509           VariableStore,
 510           (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
 511         ));
 512   PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);
 513 }
 514
 515
 516 VOID
 517 DebugDumpCmos (
 518   VOID
 519   )
 520 {
 521   UINT32 Loop;
 522
 523   DEBUG ((EFI_D_INFO, "CMOS:\n"));
 524
 525   for (Loop = 0; Loop < 0x80; Loop++) {
 526     if ((Loop % 0x10) == 0) {
 527       DEBUG ((EFI_D_INFO, "%02x:", Loop));
 528     }
 529     DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));
 530     if ((Loop % 0x10) == 0xf) {
 531       DEBUG ((EFI_D_INFO, "\n"));
 532     }
 533   }
 534 }
 535
 536
 537 VOID
 538 S3Verification (
 539   VOID
 540   )
 541 {
 542 #if defined (MDE_CPU_X64)
 543   if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {
 544     DEBUG ((EFI_D_ERROR,
 545       "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));
 546     DEBUG ((EFI_D_ERROR,
 547       "%a: Please disable S3 on the QEMU command line (see the README),\n",
 548       __FUNCTION__));
 549     DEBUG ((EFI_D_ERROR,
 550       "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));
 551     ASSERT (FALSE);
 552     CpuDeadLoop ();
 553   }
 554 #endif
 555 }
 556
 557
 558 /**
 559   Perform Platform PEI initialization.
 560
 561   @param  FileHandle      Handle of the file being invoked.
 562   @param  PeiServices     Describes the list of possible PEI Services.
 563
 564   @return EFI_SUCCESS     The PEIM initialized successfully.
 565
 566 **/
 567 EFI_STATUS
 568 EFIAPI
 569 InitializePlatform (
 570   IN       EFI_PEI_FILE_HANDLE  FileHandle,
 571   IN CONST EFI_PEI_SERVICES     **PeiServices
 572   )
 573 {
 574   EFI_STATUS    Status;
 575
 576   DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));
 577
 578   DebugDumpCmos ();
 579
 580   XenDetect ();
 581
 582   if (QemuFwCfgS3Enabled ()) {
 583     DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));
 584     mS3Supported = TRUE;
 585     Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);
 586     ASSERT_EFI_ERROR (Status);
 587   }
 588
 589   S3Verification ();
 590   BootModeInitialization ();
 591   AddressWidthInitialization ();
 592
 593   PublishPeiMemory ();
 594
 595   InitializeRamRegions ();
 596
 597   if (mXen) {
 598     DEBUG ((EFI_D_INFO, "Xen was detected\n"));
 599     InitializeXen ();
 600   }
 601
 602   //
 603   // Query Host Bridge DID
 604   //
 605   mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
 606
 607   if (mBootMode != BOOT_ON_S3_RESUME) {
 608     ReserveEmuVariableNvStore ();
 609     PeiFvInitialization ();
 610     MemMapInitialization ();
 611     NoexecDxeInitialization ();
 612   }
 613
 614   MiscInitialization ();
 615   InstallFeatureControlCallback ();
 616
 617   return EFI_SUCCESS;
 618 }