OvmfPkg/PlatformPei/Platform.c

   1 /**@file
   2   Platform PEI driver
   3
   4   Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
   5   Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
   6
   7   SPDX-License-Identifier: BSD-2-Clause-Patent
   8
   9 **/
  10
  11 //
  12 // The package level header files this module uses
  13 //
  14 #include <PiPei.h>
  15
  16 //
  17 // The Library classes this module consumes
  18 //
  19 #include <Library/BaseLib.h>
  20 #include <Library/DebugLib.h>
  21 #include <Library/HobLib.h>
  22 #include <Library/IoLib.h>
  23 #include <Library/MemoryAllocationLib.h>
  24 #include <Library/PcdLib.h>
  25 #include <Library/PciLib.h>
  26 #include <Library/PeimEntryPoint.h>
  27 #include <Library/PeiServicesLib.h>
  28 #include <Library/QemuFwCfgLib.h>
  29 #include <Library/QemuFwCfgS3Lib.h>
  30 #include <Library/ResourcePublicationLib.h>
  31 #include <Guid/MemoryTypeInformation.h>
  32 #include <Ppi/MasterBootMode.h>
  33 #include <IndustryStandard/I440FxPiix4.h>
  34 #include <IndustryStandard/Pci22.h>
  35 #include <IndustryStandard/Q35MchIch9.h>
  36 #include <IndustryStandard/QemuCpuHotplug.h>
  37 #include <OvmfPlatforms.h>
  38
  39 #include "Platform.h"
  40 #include "Cmos.h"
  41
  42 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
  43   { EfiACPIMemoryNVS,       0x004 },
  44   { EfiACPIReclaimMemory,   0x008 },
  45   { EfiReservedMemoryType,  0x004 },
  46   { EfiRuntimeServicesData, 0x024 },
  47   { EfiRuntimeServicesCode, 0x030 },
  48   { EfiBootServicesCode,    0x180 },
  49   { EfiBootServicesData,    0xF00 },
  50   { EfiMaxMemoryType,       0x000 }
  51 };
  52
  53
  54 EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {
  55   {
  56     EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  57     &gEfiPeiMasterBootModePpiGuid,
  58     NULL
  59   }
  60 };
  61
  62
  63 UINT16 mHostBridgeDevId;
  64
  65 EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
  66
  67 BOOLEAN mS3Supported = FALSE;
  68
  69 UINT32 mMaxCpuCount;
  70
  71 VOID
  72 AddIoMemoryBaseSizeHob (
  73   EFI_PHYSICAL_ADDRESS        MemoryBase,
  74   UINT64                      MemorySize
  75   )
  76 {
  77   BuildResourceDescriptorHob (
  78     EFI_RESOURCE_MEMORY_MAPPED_IO,
  79       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  80       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  81       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  82       EFI_RESOURCE_ATTRIBUTE_TESTED,
  83     MemoryBase,
  84     MemorySize
  85     );
  86 }
  87
  88 VOID
  89 AddReservedMemoryBaseSizeHob (
  90   EFI_PHYSICAL_ADDRESS        MemoryBase,
  91   UINT64                      MemorySize,
  92   BOOLEAN                     Cacheable
  93   )
  94 {
  95   BuildResourceDescriptorHob (
  96     EFI_RESOURCE_MEMORY_RESERVED,
  97       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  98       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  99       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 100       (Cacheable ?
 101        EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 102        EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 103        EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
 104        0
 105        ) |
 106       EFI_RESOURCE_ATTRIBUTE_TESTED,
 107     MemoryBase,
 108     MemorySize
 109     );
 110 }
 111
 112 VOID
 113 AddIoMemoryRangeHob (
 114   EFI_PHYSICAL_ADDRESS        MemoryBase,
 115   EFI_PHYSICAL_ADDRESS        MemoryLimit
 116   )
 117 {
 118   AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 119 }
 120
 121
 122 VOID
 123 AddMemoryBaseSizeHob (
 124   EFI_PHYSICAL_ADDRESS        MemoryBase,
 125   UINT64                      MemorySize
 126   )
 127 {
 128   BuildResourceDescriptorHob (
 129     EFI_RESOURCE_SYSTEM_MEMORY,
 130       EFI_RESOURCE_ATTRIBUTE_PRESENT |
 131       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 132       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 133       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 134       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 135       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
 136       EFI_RESOURCE_ATTRIBUTE_TESTED,
 137     MemoryBase,
 138     MemorySize
 139     );
 140 }
 141
 142
 143 VOID
 144 AddMemoryRangeHob (
 145   EFI_PHYSICAL_ADDRESS        MemoryBase,
 146   EFI_PHYSICAL_ADDRESS        MemoryLimit
 147   )
 148 {
 149   AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 150 }
 151
 152
 153 VOID
 154 MemMapInitialization (
 155   VOID
 156   )
 157 {
 158   UINT64        PciIoBase;
 159   UINT64        PciIoSize;
 160   RETURN_STATUS PcdStatus;
 161
 162   PciIoBase = 0xC000;
 163   PciIoSize = 0x4000;
 164
 165   //
 166   // Create Memory Type Information HOB
 167   //
 168   BuildGuidDataHob (
 169     &gEfiMemoryTypeInformationGuid,
 170     mDefaultMemoryTypeInformation,
 171     sizeof(mDefaultMemoryTypeInformation)
 172     );
 173
 174   //
 175   // Video memory + Legacy BIOS region
 176   //
 177   AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
 178
 179   if (!mXen) {
 180     UINT32  TopOfLowRam;
 181     UINT64  PciExBarBase;
 182     UINT32  PciBase;
 183     UINT32  PciSize;
 184
 185     TopOfLowRam = GetSystemMemorySizeBelow4gb ();
 186     PciExBarBase = 0;
 187     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 188       //
 189       // The MMCONFIG area is expected to fall between the top of low RAM and
 190       // the base of the 32-bit PCI host aperture.
 191       //
 192       PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);
 193       ASSERT (TopOfLowRam <= PciExBarBase);
 194       ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
 195       PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
 196     } else {
 197       ASSERT (TopOfLowRam <= mQemuUc32Base);
 198       PciBase = mQemuUc32Base;
 199     }
 200
 201     //
 202     // address       purpose   size
 203     // ------------  --------  -------------------------
 204     // max(top, 2g)  PCI MMIO  0xFC000000 - max(top, 2g)
 205     // 0xFC000000    gap                           44 MB
 206     // 0xFEC00000    IO-APIC                        4 KB
 207     // 0xFEC01000    gap                         1020 KB
 208     // 0xFED00000    HPET                           1 KB
 209     // 0xFED00400    gap                          111 KB
 210     // 0xFED1C000    gap (PIIX4) / RCRB (ICH9)     16 KB
 211     // 0xFED20000    gap                          896 KB
 212     // 0xFEE00000    LAPIC                          1 MB
 213     //
 214     PciSize = 0xFC000000 - PciBase;
 215     AddIoMemoryBaseSizeHob (PciBase, PciSize);
 216     PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);
 217     ASSERT_RETURN_ERROR (PcdStatus);
 218     PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize);
 219     ASSERT_RETURN_ERROR (PcdStatus);
 220
 221     AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
 222     AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
 223     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 224       AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
 225       //
 226       // Note: there should be an
 227       //
 228       //   AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
 229       //
 230       // call below, just like the one above for RCBA. However, Linux insists
 231       // that the MMCONFIG area be marked in the E820 or UEFI memory map as
 232       // "reserved memory" -- Linux does not content itself with a simple gap
 233       // in the memory map wherever the MCFG ACPI table points to.
 234       //
 235       // This appears to be a safety measure. The PCI Firmware Specification
 236       // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can
 237       // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory
 238       // [...]". (Emphasis added here.)
 239       //
 240       // Normally we add memory resource descriptor HOBs in
 241       // QemuInitializeRam(), and pre-allocate from those with memory
 242       // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area
 243       // is most definitely not RAM; so, as an exception, cover it with
 244       // uncacheable reserved memory right here.
 245       //
 246       AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);
 247       BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,
 248         EfiReservedMemoryType);
 249     }
 250     AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
 251
 252     //
 253     // On Q35, the IO Port space is available for PCI resource allocations from
 254     // 0x6000 up.
 255     //
 256     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 257       PciIoBase = 0x6000;
 258       PciIoSize = 0xA000;
 259       ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);
 260     }
 261   }
 262
 263   //
 264   // Add PCI IO Port space available for PCI resource allocations.
 265   //
 266   BuildResourceDescriptorHob (
 267     EFI_RESOURCE_IO,
 268     EFI_RESOURCE_ATTRIBUTE_PRESENT     |
 269     EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
 270     PciIoBase,
 271     PciIoSize
 272     );
 273   PcdStatus = PcdSet64S (PcdPciIoBase, PciIoBase);
 274   ASSERT_RETURN_ERROR (PcdStatus);
 275   PcdStatus = PcdSet64S (PcdPciIoSize, PciIoSize);
 276   ASSERT_RETURN_ERROR (PcdStatus);
 277 }
 278
 279 EFI_STATUS
 280 GetNamedFwCfgBoolean (
 281   IN  CHAR8   *FwCfgFileName,
 282   OUT BOOLEAN *Setting
 283   )
 284 {
 285   EFI_STATUS           Status;
 286   FIRMWARE_CONFIG_ITEM FwCfgItem;
 287   UINTN                FwCfgSize;
 288   UINT8                Value[3];
 289
 290   Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);
 291   if (EFI_ERROR (Status)) {
 292     return Status;
 293   }
 294   if (FwCfgSize > sizeof Value) {
 295     return EFI_BAD_BUFFER_SIZE;
 296   }
 297   QemuFwCfgSelectItem (FwCfgItem);
 298   QemuFwCfgReadBytes (FwCfgSize, Value);
 299
 300   if ((FwCfgSize == 1) ||
 301       (FwCfgSize == 2 && Value[1] == '\n') ||
 302       (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {
 303     switch (Value[0]) {
 304       case '0':
 305       case 'n':
 306       case 'N':
 307         *Setting = FALSE;
 308         return EFI_SUCCESS;
 309
 310       case '1':
 311       case 'y':
 312       case 'Y':
 313         *Setting = TRUE;
 314         return EFI_SUCCESS;
 315
 316       default:
 317         break;
 318     }
 319   }
 320   return EFI_PROTOCOL_ERROR;
 321 }
 322
 323 #define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName)                   \
 324           do {                                                      \
 325             BOOLEAN       Setting;                                  \
 326             RETURN_STATUS PcdStatus;                                \
 327                                                                     \
 328             if (!EFI_ERROR (GetNamedFwCfgBoolean (                  \
 329                               "opt/ovmf/" #TokenName, &Setting))) { \
 330               PcdStatus = PcdSetBoolS (TokenName, Setting);         \
 331               ASSERT_RETURN_ERROR (PcdStatus);                      \
 332             }                                                       \
 333           } while (0)
 334
 335 VOID
 336 NoexecDxeInitialization (
 337   VOID
 338   )
 339 {
 340   UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);
 341   UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);
 342 }
 343
 344 VOID
 345 PciExBarInitialization (
 346   VOID
 347   )
 348 {
 349   union {
 350     UINT64 Uint64;
 351     UINT32 Uint32[2];
 352   } PciExBarBase;
 353
 354   //
 355   // We only support the 256MB size for the MMCONFIG area:
 356   // 256 buses * 32 devices * 8 functions * 4096 bytes config space.
 357   //
 358   // The masks used below enforce the Q35 requirements that the MMCONFIG area
 359   // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.
 360   //
 361   // Note that (b) also ensures that the minimum address width we have
 362   // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice
 363   // for DXE's page tables to cover the MMCONFIG area.
 364   //
 365   PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);
 366   ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);
 367   ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);
 368
 369   //
 370   // Clear the PCIEXBAREN bit first, before programming the high register.
 371   //
 372   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);
 373
 374   //
 375   // Program the high register. Then program the low register, setting the
 376   // MMCONFIG area size and enabling decoding at once.
 377   //
 378   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);
 379   PciWrite32 (
 380     DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),
 381     PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN
 382     );
 383 }
 384
 385 VOID
 386 MiscInitialization (
 387   VOID
 388   )
 389 {
 390   UINTN         PmCmd;
 391   UINTN         Pmba;
 392   UINT32        PmbaAndVal;
 393   UINT32        PmbaOrVal;
 394   UINTN         AcpiCtlReg;
 395   UINT8         AcpiEnBit;
 396   RETURN_STATUS PcdStatus;
 397
 398   //
 399   // Disable A20 Mask
 400   //
 401   IoOr8 (0x92, BIT1);
 402
 403   //
 404   // Build the CPU HOB with guest RAM size dependent address width and 16-bits
 405   // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
 406   // S3 resume as well, so we build it unconditionally.)
 407   //
 408   BuildCpuHob (mPhysMemAddressWidth, 16);
 409
 410   //
 411   // Determine platform type and save Host Bridge DID to PCD
 412   //
 413   switch (mHostBridgeDevId) {
 414     case INTEL_82441_DEVICE_ID:
 415       PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
 416       Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
 417       PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;
 418       PmbaOrVal  = PIIX4_PMBA_VALUE;
 419       AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
 420       AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;
 421       break;
 422     case INTEL_Q35_MCH_DEVICE_ID:
 423       PmCmd      = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
 424       Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
 425       PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;
 426       PmbaOrVal  = ICH9_PMBASE_VALUE;
 427       AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
 428       AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;
 429       break;
 430     default:
 431       DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
 432         __FUNCTION__, mHostBridgeDevId));
 433       ASSERT (FALSE);
 434       return;
 435   }
 436   PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
 437   ASSERT_RETURN_ERROR (PcdStatus);
 438
 439   //
 440   // If the appropriate IOspace enable bit is set, assume the ACPI PMBA
 441   // has been configured (e.g., by Xen) and skip the setup here.
 442   // This matches the logic in AcpiTimerLibConstructor ().
 443   //
 444   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
 445     //
 446     // The PEI phase should be exited with fully accessibe ACPI PM IO space:
 447     // 1. set PMBA
 448     //
 449     PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);
 450
 451     //
 452     // 2. set PCICMD/IOSE
 453     //
 454     PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
 455
 456     //
 457     // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
 458     //
 459     PciOr8 (AcpiCtlReg, AcpiEnBit);
 460   }
 461
 462   if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 463     //
 464     // Set Root Complex Register Block BAR
 465     //
 466     PciWrite32 (
 467       POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),
 468       ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN
 469       );
 470
 471     //
 472     // Set PCI Express Register Range Base Address
 473     //
 474     PciExBarInitialization ();
 475   }
 476 }
 477
 478
 479 VOID
 480 BootModeInitialization (
 481   VOID
 482   )
 483 {
 484   EFI_STATUS    Status;
 485
 486   if (CmosRead8 (0xF) == 0xFE) {
 487     mBootMode = BOOT_ON_S3_RESUME;
 488   }
 489   CmosWrite8 (0xF, 0x00);
 490
 491   Status = PeiServicesSetBootMode (mBootMode);
 492   ASSERT_EFI_ERROR (Status);
 493
 494   Status = PeiServicesInstallPpi (mPpiBootMode);
 495   ASSERT_EFI_ERROR (Status);
 496 }
 497
 498
 499 VOID
 500 ReserveEmuVariableNvStore (
 501   )
 502 {
 503   EFI_PHYSICAL_ADDRESS VariableStore;
 504   RETURN_STATUS        PcdStatus;
 505
 506   //
 507   // Allocate storage for NV variables early on so it will be
 508   // at a consistent address.  Since VM memory is preserved
 509   // across reboots, this allows the NV variable storage to survive
 510   // a VM reboot.
 511   //
 512   VariableStore =
 513     (EFI_PHYSICAL_ADDRESS)(UINTN)
 514       AllocateRuntimePages (
 515         EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))
 516         );
 517   DEBUG ((EFI_D_INFO,
 518           "Reserved variable store memory: 0x%lX; size: %dkb\n",
 519           VariableStore,
 520           (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
 521         ));
 522   PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);
 523   ASSERT_RETURN_ERROR (PcdStatus);
 524 }
 525
 526
 527 VOID
 528 DebugDumpCmos (
 529   VOID
 530   )
 531 {
 532   UINT32 Loop;
 533
 534   DEBUG ((EFI_D_INFO, "CMOS:\n"));
 535
 536   for (Loop = 0; Loop < 0x80; Loop++) {
 537     if ((Loop % 0x10) == 0) {
 538       DEBUG ((EFI_D_INFO, "%02x:", Loop));
 539     }
 540     DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));
 541     if ((Loop % 0x10) == 0xf) {
 542       DEBUG ((EFI_D_INFO, "\n"));
 543     }
 544   }
 545 }
 546
 547
 548 VOID
 549 S3Verification (
 550   VOID
 551   )
 552 {
 553 #if defined (MDE_CPU_X64)
 554   if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {
 555     DEBUG ((EFI_D_ERROR,
 556       "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));
 557     DEBUG ((EFI_D_ERROR,
 558       "%a: Please disable S3 on the QEMU command line (see the README),\n",
 559       __FUNCTION__));
 560     DEBUG ((EFI_D_ERROR,
 561       "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));
 562     ASSERT (FALSE);
 563     CpuDeadLoop ();
 564   }
 565 #endif
 566 }
 567
 568
 569 /**
 570   Fetch the boot CPU count and the possible CPU count from QEMU, and expose
 571   them to UefiCpuPkg modules. Set the mMaxCpuCount variable.
 572 **/
 573 VOID
 574 MaxCpuCountInitialization (
 575   VOID
 576   )
 577 {
 578   UINT16        BootCpuCount;
 579   RETURN_STATUS PcdStatus;
 580
 581   //
 582   // Try to fetch the boot CPU count.
 583   //
 584   QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount);
 585   BootCpuCount = QemuFwCfgRead16 ();
 586   if (BootCpuCount == 0) {
 587     //
 588     // QEMU doesn't report the boot CPU count. (BootCpuCount == 0) will let
 589     // MpInitLib count APs up to (PcdCpuMaxLogicalProcessorNumber - 1), or
 590     // until PcdCpuApInitTimeOutInMicroSeconds elapses (whichever is reached
 591     // first).
 592     //
 593     DEBUG ((DEBUG_WARN, "%a: boot CPU count unavailable\n", __FUNCTION__));
 594     mMaxCpuCount = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
 595   } else {
 596     //
 597     // We will expose BootCpuCount to MpInitLib. MpInitLib will count APs up to
 598     // (BootCpuCount - 1) precisely, regardless of timeout.
 599     //
 600     // Now try to fetch the possible CPU count.
 601     //
 602     UINTN CpuHpBase;
 603     UINT32 CmdData2;
 604
 605     CpuHpBase = ((mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) ?
 606                  ICH9_CPU_HOTPLUG_BASE : PIIX4_CPU_HOTPLUG_BASE);
 607
 608     //
 609     // If only legacy mode is available in the CPU hotplug register block, or
 610     // the register block is completely missing, then the writes below are
 611     // no-ops.
 612     //
 613     // 1. Switch the hotplug register block to modern mode.
 614     //
 615     IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0);
 616     //
 617     // 2. Select a valid CPU for deterministic reading of
 618     //    QEMU_CPUHP_R_CMD_DATA2.
 619     //
 620     //    CPU#0 is always valid; it is the always present and non-removable
 621     //    BSP.
 622     //
 623     IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0);
 624     //
 625     // 3. Send a command after which QEMU_CPUHP_R_CMD_DATA2 is specified to
 626     //    read as zero, and which does not invalidate the selector. (The
 627     //    selector may change, but it must not become invalid.)
 628     //
 629     //    Send QEMU_CPUHP_CMD_GET_PENDING, as it will prove useful later.
 630     //
 631     IoWrite8 (CpuHpBase + QEMU_CPUHP_W_CMD, QEMU_CPUHP_CMD_GET_PENDING);
 632     //
 633     // 4. Read QEMU_CPUHP_R_CMD_DATA2.
 634     //
 635     //    If the register block is entirely missing, then this is an unassigned
 636     //    IO read, returning all-bits-one.
 637     //
 638     //    If only legacy mode is available, then bit#0 stands for CPU#0 in the
 639     //    "CPU present bitmap". CPU#0 is always present.
 640     //
 641     //    Otherwise, QEMU_CPUHP_R_CMD_DATA2 is either still reserved (returning
 642     //    all-bits-zero), or it is specified to read as zero after the above
 643     //    steps. Both cases confirm modern mode.
 644     //
 645     CmdData2 = IoRead32 (CpuHpBase + QEMU_CPUHP_R_CMD_DATA2);
 646     DEBUG ((DEBUG_VERBOSE, "%a: CmdData2=0x%x\n", __FUNCTION__, CmdData2));
 647     if (CmdData2 != 0) {
 648       //
 649       // QEMU doesn't support the modern CPU hotplug interface. Assume that the
 650       // possible CPU count equals the boot CPU count (precluding hotplug).
 651       //
 652       DEBUG ((DEBUG_WARN, "%a: modern CPU hotplug interface unavailable\n",
 653         __FUNCTION__));
 654       mMaxCpuCount = BootCpuCount;
 655     } else {
 656       //
 657       // Grab the possible CPU count from the modern CPU hotplug interface.
 658       //
 659       UINT32 Present, Possible, Selected;
 660
 661       Present = 0;
 662       Possible = 0;
 663
 664       //
 665       // We've sent QEMU_CPUHP_CMD_GET_PENDING last; this ensures
 666       // QEMU_CPUHP_RW_CMD_DATA can now be read usefully. However,
 667       // QEMU_CPUHP_CMD_GET_PENDING may have selected a CPU with actual pending
 668       // hotplug events; therefore, select CPU#0 forcibly.
 669       //
 670       IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible);
 671
 672       do {
 673         UINT8 CpuStatus;
 674
 675         //
 676         // Read the status of the currently selected CPU. This will help with a
 677         // sanity check against "BootCpuCount".
 678         //
 679         CpuStatus = IoRead8 (CpuHpBase + QEMU_CPUHP_R_CPU_STAT);
 680         if ((CpuStatus & QEMU_CPUHP_STAT_ENABLED) != 0) {
 681           ++Present;
 682         }
 683         //
 684         // Attempt to select the next CPU.
 685         //
 686         ++Possible;
 687         IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible);
 688         //
 689         // If the selection is successful, then the following read will return
 690         // the selector (which we know is positive at this point). Otherwise,
 691         // the read will return 0.
 692         //
 693         Selected = IoRead32 (CpuHpBase + QEMU_CPUHP_RW_CMD_DATA);
 694         ASSERT (Selected == Possible || Selected == 0);
 695       } while (Selected > 0);
 696
 697       //
 698       // Sanity check: fw_cfg and the modern CPU hotplug interface should
 699       // return the same boot CPU count.
 700       //
 701       if (BootCpuCount != Present) {
 702         DEBUG ((DEBUG_WARN, "%a: QEMU v2.7 reset bug: BootCpuCount=%d "
 703           "Present=%u\n", __FUNCTION__, BootCpuCount, Present));
 704         //
 705         // The handling of QemuFwCfgItemSmpCpuCount, across CPU hotplug plus
 706         // platform reset (including S3), was corrected in QEMU commit
 707         // e3cadac073a9 ("pc: fix FW_CFG_NB_CPUS to account for -device added
 708         // CPUs", 2016-11-16), part of release v2.8.0.
 709         //
 710         BootCpuCount = (UINT16)Present;
 711       }
 712
 713       mMaxCpuCount = Possible;
 714     }
 715   }
 716
 717   DEBUG ((DEBUG_INFO, "%a: BootCpuCount=%d mMaxCpuCount=%u\n", __FUNCTION__,
 718     BootCpuCount, mMaxCpuCount));
 719   ASSERT (BootCpuCount <= mMaxCpuCount);
 720
 721   PcdStatus = PcdSet32S (PcdCpuBootLogicalProcessorNumber, BootCpuCount);
 722   ASSERT_RETURN_ERROR (PcdStatus);
 723   PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, mMaxCpuCount);
 724   ASSERT_RETURN_ERROR (PcdStatus);
 725 }
 726
 727
 728 /**
 729   Perform Platform PEI initialization.
 730
 731   @param  FileHandle      Handle of the file being invoked.
 732   @param  PeiServices     Describes the list of possible PEI Services.
 733
 734   @return EFI_SUCCESS     The PEIM initialized successfully.
 735
 736 **/
 737 EFI_STATUS
 738 EFIAPI
 739 InitializePlatform (
 740   IN       EFI_PEI_FILE_HANDLE  FileHandle,
 741   IN CONST EFI_PEI_SERVICES     **PeiServices
 742   )
 743 {
 744   EFI_STATUS    Status;
 745
 746   DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));
 747
 748   DebugDumpCmos ();
 749
 750   XenDetect ();
 751
 752   if (QemuFwCfgS3Enabled ()) {
 753     DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));
 754     mS3Supported = TRUE;
 755     Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);
 756     ASSERT_EFI_ERROR (Status);
 757   }
 758
 759   S3Verification ();
 760   BootModeInitialization ();
 761   AddressWidthInitialization ();
 762
 763   //
 764   // Query Host Bridge DID
 765   //
 766   mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
 767
 768   MaxCpuCountInitialization ();
 769
 770   if (FeaturePcdGet (PcdSmmSmramRequire)) {
 771     Q35TsegMbytesInitialization ();
 772   }
 773
 774   PublishPeiMemory ();
 775
 776   QemuUc32BaseInitialization ();
 777
 778   InitializeRamRegions ();
 779
 780   if (mXen) {
 781     DEBUG ((EFI_D_INFO, "Xen was detected\n"));
 782     InitializeXen ();
 783   }
 784
 785   if (mBootMode != BOOT_ON_S3_RESUME) {
 786     if (!FeaturePcdGet (PcdSmmSmramRequire)) {
 787       ReserveEmuVariableNvStore ();
 788     }
 789     PeiFvInitialization ();
 790     MemMapInitialization ();
 791     NoexecDxeInitialization ();
 792   }
 793
 794   InstallClearCacheCallback ();
 795   AmdSevInitialize ();
 796   MiscInitialization ();
 797   InstallFeatureControlCallback ();
 798
 799   return EFI_SUCCESS;
 800 }