OvmfPkg/PlatformPei/Platform.c

   1 /**@file
   2   Platform PEI driver
   3
   4   Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
   5   Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
   6
   7   This program and the accompanying materials
   8   are licensed and made available under the terms and conditions of the BSD License
   9   which accompanies this distribution.  The full text of the license may be found at
  10   http://opensource.org/licenses/bsd-license.php
  11
  12   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15 **/
  16
  17 //
  18 // The package level header files this module uses
  19 //
  20 #include <PiPei.h>
  21
  22 //
  23 // The Library classes this module consumes
  24 //
  25 #include <Library/BaseLib.h>
  26 #include <Library/DebugLib.h>
  27 #include <Library/HobLib.h>
  28 #include <Library/IoLib.h>
  29 #include <Library/MemoryAllocationLib.h>
  30 #include <Library/PcdLib.h>
  31 #include <Library/PciLib.h>
  32 #include <Library/PeimEntryPoint.h>
  33 #include <Library/PeiServicesLib.h>
  34 #include <Library/QemuFwCfgLib.h>
  35 #include <Library/ResourcePublicationLib.h>
  36 #include <Guid/MemoryTypeInformation.h>
  37 #include <Ppi/MasterBootMode.h>
  38 #include <IndustryStandard/Pci22.h>
  39 #include <OvmfPlatforms.h>
  40
  41 #include "Platform.h"
  42 #include "Cmos.h"
  43
  44 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
  45   { EfiACPIMemoryNVS,       0x004 },
  46   { EfiACPIReclaimMemory,   0x008 },
  47   { EfiReservedMemoryType,  0x004 },
  48   { EfiRuntimeServicesData, 0x024 },
  49   { EfiRuntimeServicesCode, 0x030 },
  50   { EfiBootServicesCode,    0x180 },
  51   { EfiBootServicesData,    0xF00 },
  52   { EfiMaxMemoryType,       0x000 }
  53 };
  54
  55
  56 EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {
  57   {
  58     EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  59     &gEfiPeiMasterBootModePpiGuid,
  60     NULL
  61   }
  62 };
  63
  64
  65 UINT16 mHostBridgeDevId;
  66
  67 EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
  68
  69 BOOLEAN mS3Supported = FALSE;
  70
  71
  72 VOID
  73 AddIoMemoryBaseSizeHob (
  74   EFI_PHYSICAL_ADDRESS        MemoryBase,
  75   UINT64                      MemorySize
  76   )
  77 {
  78   BuildResourceDescriptorHob (
  79     EFI_RESOURCE_MEMORY_MAPPED_IO,
  80       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  81       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  82       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  83       EFI_RESOURCE_ATTRIBUTE_TESTED,
  84     MemoryBase,
  85     MemorySize
  86     );
  87 }
  88
  89 VOID
  90 AddReservedMemoryBaseSizeHob (
  91   EFI_PHYSICAL_ADDRESS        MemoryBase,
  92   UINT64                      MemorySize,
  93   BOOLEAN                     Cacheable
  94   )
  95 {
  96   BuildResourceDescriptorHob (
  97     EFI_RESOURCE_MEMORY_RESERVED,
  98       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  99       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 100       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 101       (Cacheable ?
 102        EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 103        EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 104        EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
 105        0
 106        ) |
 107       EFI_RESOURCE_ATTRIBUTE_TESTED,
 108     MemoryBase,
 109     MemorySize
 110     );
 111 }
 112
 113 VOID
 114 AddIoMemoryRangeHob (
 115   EFI_PHYSICAL_ADDRESS        MemoryBase,
 116   EFI_PHYSICAL_ADDRESS        MemoryLimit
 117   )
 118 {
 119   AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 120 }
 121
 122
 123 VOID
 124 AddMemoryBaseSizeHob (
 125   EFI_PHYSICAL_ADDRESS        MemoryBase,
 126   UINT64                      MemorySize
 127   )
 128 {
 129   BuildResourceDescriptorHob (
 130     EFI_RESOURCE_SYSTEM_MEMORY,
 131       EFI_RESOURCE_ATTRIBUTE_PRESENT |
 132       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 133       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 134       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 135       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 136       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
 137       EFI_RESOURCE_ATTRIBUTE_TESTED,
 138     MemoryBase,
 139     MemorySize
 140     );
 141 }
 142
 143
 144 VOID
 145 AddMemoryRangeHob (
 146   EFI_PHYSICAL_ADDRESS        MemoryBase,
 147   EFI_PHYSICAL_ADDRESS        MemoryLimit
 148   )
 149 {
 150   AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 151 }
 152
 153
 154 VOID
 155 AddUntestedMemoryBaseSizeHob (
 156   EFI_PHYSICAL_ADDRESS        MemoryBase,
 157   UINT64                      MemorySize
 158   )
 159 {
 160   BuildResourceDescriptorHob (
 161     EFI_RESOURCE_SYSTEM_MEMORY,
 162       EFI_RESOURCE_ATTRIBUTE_PRESENT |
 163       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 164       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 165       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 166       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 167       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,
 168     MemoryBase,
 169     MemorySize
 170     );
 171 }
 172
 173
 174 VOID
 175 AddUntestedMemoryRangeHob (
 176   EFI_PHYSICAL_ADDRESS        MemoryBase,
 177   EFI_PHYSICAL_ADDRESS        MemoryLimit
 178   )
 179 {
 180   AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 181 }
 182
 183 VOID
 184 MemMapInitialization (
 185   VOID
 186   )
 187 {
 188   //
 189   // Create Memory Type Information HOB
 190   //
 191   BuildGuidDataHob (
 192     &gEfiMemoryTypeInformationGuid,
 193     mDefaultMemoryTypeInformation,
 194     sizeof(mDefaultMemoryTypeInformation)
 195     );
 196
 197   //
 198   // Add PCI IO Port space available for PCI resource allocations.
 199   //
 200   BuildResourceDescriptorHob (
 201     EFI_RESOURCE_IO,
 202     EFI_RESOURCE_ATTRIBUTE_PRESENT     |
 203     EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
 204     PcdGet64 (PcdPciIoBase),
 205     PcdGet64 (PcdPciIoSize)
 206     );
 207
 208   //
 209   // Video memory + Legacy BIOS region
 210   //
 211   AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
 212
 213   if (!mXen) {
 214     UINT32  TopOfLowRam;
 215     UINT64  PciExBarBase;
 216     UINT32  PciBase;
 217     UINT32  PciSize;
 218
 219     TopOfLowRam = GetSystemMemorySizeBelow4gb ();
 220     PciExBarBase = 0;
 221     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 222       //
 223       // The MMCONFIG area is expected to fall between the top of low RAM and
 224       // the base of the 32-bit PCI host aperture.
 225       //
 226       PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);
 227       ASSERT (TopOfLowRam <= PciExBarBase);
 228       ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
 229       PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
 230     } else {
 231       PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;
 232     }
 233
 234     //
 235     // address       purpose   size
 236     // ------------  --------  -------------------------
 237     // max(top, 2g)  PCI MMIO  0xFC000000 - max(top, 2g)
 238     // 0xFC000000    gap                           44 MB
 239     // 0xFEC00000    IO-APIC                        4 KB
 240     // 0xFEC01000    gap                         1020 KB
 241     // 0xFED00000    HPET                           1 KB
 242     // 0xFED00400    gap                          111 KB
 243     // 0xFED1C000    gap (PIIX4) / RCRB (ICH9)     16 KB
 244     // 0xFED20000    gap                          896 KB
 245     // 0xFEE00000    LAPIC                          1 MB
 246     //
 247     PciSize = 0xFC000000 - PciBase;
 248     AddIoMemoryBaseSizeHob (PciBase, PciSize);
 249     PcdSet64 (PcdPciMmio32Base, PciBase);
 250     PcdSet64 (PcdPciMmio32Size, PciSize);
 251     AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
 252     AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
 253     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 254       AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
 255       //
 256       // Note: there should be an
 257       //
 258       //   AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
 259       //
 260       // call below, just like the one above for RCBA. However, Linux insists
 261       // that the MMCONFIG area be marked in the E820 or UEFI memory map as
 262       // "reserved memory" -- Linux does not content itself with a simple gap
 263       // in the memory map wherever the MCFG ACPI table points to.
 264       //
 265       // This appears to be a safety measure. The PCI Firmware Specification
 266       // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can
 267       // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory
 268       // [...]". (Emphasis added here.)
 269       //
 270       // Normally we add memory resource descriptor HOBs in
 271       // QemuInitializeRam(), and pre-allocate from those with memory
 272       // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area
 273       // is most definitely not RAM; so, as an exception, cover it with
 274       // uncacheable reserved memory right here.
 275       //
 276       AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);
 277       BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,
 278         EfiReservedMemoryType);
 279     }
 280     AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
 281   }
 282 }
 283
 284 EFI_STATUS
 285 GetNamedFwCfgBoolean (
 286   IN  CHAR8   *FwCfgFileName,
 287   OUT BOOLEAN *Setting
 288   )
 289 {
 290   EFI_STATUS           Status;
 291   FIRMWARE_CONFIG_ITEM FwCfgItem;
 292   UINTN                FwCfgSize;
 293   UINT8                Value[3];
 294
 295   Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);
 296   if (EFI_ERROR (Status)) {
 297     return Status;
 298   }
 299   if (FwCfgSize > sizeof Value) {
 300     return EFI_BAD_BUFFER_SIZE;
 301   }
 302   QemuFwCfgSelectItem (FwCfgItem);
 303   QemuFwCfgReadBytes (FwCfgSize, Value);
 304
 305   if ((FwCfgSize == 1) ||
 306       (FwCfgSize == 2 && Value[1] == '\n') ||
 307       (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {
 308     switch (Value[0]) {
 309       case '0':
 310       case 'n':
 311       case 'N':
 312         *Setting = FALSE;
 313         return EFI_SUCCESS;
 314
 315       case '1':
 316       case 'y':
 317       case 'Y':
 318         *Setting = TRUE;
 319         return EFI_SUCCESS;
 320
 321       default:
 322         break;
 323     }
 324   }
 325   return EFI_PROTOCOL_ERROR;
 326 }
 327
 328 #define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName)                   \
 329           do {                                                      \
 330             BOOLEAN Setting;                                        \
 331                                                                     \
 332             if (!EFI_ERROR (GetNamedFwCfgBoolean (                  \
 333                               "opt/ovmf/" #TokenName, &Setting))) { \
 334               PcdSetBool (TokenName, Setting);                      \
 335             }                                                       \
 336           } while (0)
 337
 338 VOID
 339 NoexecDxeInitialization (
 340   VOID
 341   )
 342 {
 343   UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);
 344   UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);
 345 }
 346
 347 VOID
 348 PciExBarInitialization (
 349   VOID
 350   )
 351 {
 352   union {
 353     UINT64 Uint64;
 354     UINT32 Uint32[2];
 355   } PciExBarBase;
 356
 357   //
 358   // We only support the 256MB size for the MMCONFIG area:
 359   // 256 buses * 32 devices * 8 functions * 4096 bytes config space.
 360   //
 361   // The masks used below enforce the Q35 requirements that the MMCONFIG area
 362   // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.
 363   //
 364   // Note that (b) also ensures that the minimum address width we have
 365   // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice
 366   // for DXE's page tables to cover the MMCONFIG area.
 367   //
 368   PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);
 369   ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);
 370   ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);
 371
 372   //
 373   // Clear the PCIEXBAREN bit first, before programming the high register.
 374   //
 375   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);
 376
 377   //
 378   // Program the high register. Then program the low register, setting the
 379   // MMCONFIG area size and enabling decoding at once.
 380   //
 381   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);
 382   PciWrite32 (
 383     DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),
 384     PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN
 385     );
 386 }
 387
 388 VOID
 389 MiscInitialization (
 390   VOID
 391   )
 392 {
 393   UINTN  PmCmd;
 394   UINTN  Pmba;
 395   UINTN  AcpiCtlReg;
 396   UINT8  AcpiEnBit;
 397
 398   //
 399   // Disable A20 Mask
 400   //
 401   IoOr8 (0x92, BIT1);
 402
 403   //
 404   // Build the CPU HOB with guest RAM size dependent address width and 16-bits
 405   // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
 406   // S3 resume as well, so we build it unconditionally.)
 407   //
 408   BuildCpuHob (mPhysMemAddressWidth, 16);
 409
 410   //
 411   // Determine platform type and save Host Bridge DID to PCD
 412   //
 413   switch (mHostBridgeDevId) {
 414     case INTEL_82441_DEVICE_ID:
 415       PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
 416       Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
 417       AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
 418       AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;
 419       break;
 420     case INTEL_Q35_MCH_DEVICE_ID:
 421       PmCmd      = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
 422       Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
 423       AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
 424       AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;
 425       break;
 426     default:
 427       DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
 428         __FUNCTION__, mHostBridgeDevId));
 429       ASSERT (FALSE);
 430       return;
 431   }
 432   PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
 433
 434   //
 435   // If the appropriate IOspace enable bit is set, assume the ACPI PMBA
 436   // has been configured (e.g., by Xen) and skip the setup here.
 437   // This matches the logic in AcpiTimerLibConstructor ().
 438   //
 439   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
 440     //
 441     // The PEI phase should be exited with fully accessibe ACPI PM IO space:
 442     // 1. set PMBA
 443     //
 444     PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));
 445
 446     //
 447     // 2. set PCICMD/IOSE
 448     //
 449     PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
 450
 451     //
 452     // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
 453     //
 454     PciOr8 (AcpiCtlReg, AcpiEnBit);
 455   }
 456
 457   if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 458     //
 459     // Set Root Complex Register Block BAR
 460     //
 461     PciWrite32 (
 462       POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),
 463       ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN
 464       );
 465
 466     //
 467     // Set PCI Express Register Range Base Address
 468     //
 469     PciExBarInitialization ();
 470   }
 471 }
 472
 473
 474 VOID
 475 BootModeInitialization (
 476   VOID
 477   )
 478 {
 479   EFI_STATUS    Status;
 480
 481   if (CmosRead8 (0xF) == 0xFE) {
 482     mBootMode = BOOT_ON_S3_RESUME;
 483   }
 484   CmosWrite8 (0xF, 0x00);
 485
 486   Status = PeiServicesSetBootMode (mBootMode);
 487   ASSERT_EFI_ERROR (Status);
 488
 489   Status = PeiServicesInstallPpi (mPpiBootMode);
 490   ASSERT_EFI_ERROR (Status);
 491 }
 492
 493
 494 VOID
 495 ReserveEmuVariableNvStore (
 496   )
 497 {
 498   EFI_PHYSICAL_ADDRESS VariableStore;
 499
 500   //
 501   // Allocate storage for NV variables early on so it will be
 502   // at a consistent address.  Since VM memory is preserved
 503   // across reboots, this allows the NV variable storage to survive
 504   // a VM reboot.
 505   //
 506   VariableStore =
 507     (EFI_PHYSICAL_ADDRESS)(UINTN)
 508       AllocateAlignedRuntimePages (
 509         EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),
 510         PcdGet32 (PcdFlashNvStorageFtwSpareSize)
 511         );
 512   DEBUG ((EFI_D_INFO,
 513           "Reserved variable store memory: 0x%lX; size: %dkb\n",
 514           VariableStore,
 515           (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
 516         ));
 517   PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);
 518 }
 519
 520
 521 VOID
 522 DebugDumpCmos (
 523   VOID
 524   )
 525 {
 526   UINT32 Loop;
 527
 528   DEBUG ((EFI_D_INFO, "CMOS:\n"));
 529
 530   for (Loop = 0; Loop < 0x80; Loop++) {
 531     if ((Loop % 0x10) == 0) {
 532       DEBUG ((EFI_D_INFO, "%02x:", Loop));
 533     }
 534     DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));
 535     if ((Loop % 0x10) == 0xf) {
 536       DEBUG ((EFI_D_INFO, "\n"));
 537     }
 538   }
 539 }
 540
 541
 542 VOID
 543 S3Verification (
 544   VOID
 545   )
 546 {
 547 #if defined (MDE_CPU_X64)
 548   if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {
 549     DEBUG ((EFI_D_ERROR,
 550       "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));
 551     DEBUG ((EFI_D_ERROR,
 552       "%a: Please disable S3 on the QEMU command line (see the README),\n",
 553       __FUNCTION__));
 554     DEBUG ((EFI_D_ERROR,
 555       "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));
 556     ASSERT (FALSE);
 557     CpuDeadLoop ();
 558   }
 559 #endif
 560 }
 561
 562
 563 /**
 564   Perform Platform PEI initialization.
 565
 566   @param  FileHandle      Handle of the file being invoked.
 567   @param  PeiServices     Describes the list of possible PEI Services.
 568
 569   @return EFI_SUCCESS     The PEIM initialized successfully.
 570
 571 **/
 572 EFI_STATUS
 573 EFIAPI
 574 InitializePlatform (
 575   IN       EFI_PEI_FILE_HANDLE  FileHandle,
 576   IN CONST EFI_PEI_SERVICES     **PeiServices
 577   )
 578 {
 579   DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));
 580
 581   DebugDumpCmos ();
 582
 583   XenDetect ();
 584
 585   if (QemuFwCfgS3Enabled ()) {
 586     DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));
 587     mS3Supported = TRUE;
 588   }
 589
 590   S3Verification ();
 591   BootModeInitialization ();
 592   AddressWidthInitialization ();
 593
 594   PublishPeiMemory ();
 595
 596   InitializeRamRegions ();
 597
 598   if (mXen) {
 599     DEBUG ((EFI_D_INFO, "Xen was detected\n"));
 600     InitializeXen ();
 601   }
 602
 603   //
 604   // Query Host Bridge DID
 605   //
 606   mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
 607
 608   if (mBootMode != BOOT_ON_S3_RESUME) {
 609     ReserveEmuVariableNvStore ();
 610     PeiFvInitialization ();
 611     MemMapInitialization ();
 612     NoexecDxeInitialization ();
 613   }
 614
 615   MiscInitialization ();
 616
 617   return EFI_SUCCESS;
 618 }