OvmfPkg/PlatformPei/Platform.c

   1 /**@file
   2   Platform PEI driver
   3
   4   Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
   5   Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
   6
   7   This program and the accompanying materials
   8   are licensed and made available under the terms and conditions of the BSD License
   9   which accompanies this distribution.  The full text of the license may be found at
  10   http://opensource.org/licenses/bsd-license.php
  11
  12   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15 **/
  16
  17 //
  18 // The package level header files this module uses
  19 //
  20 #include <PiPei.h>
  21
  22 //
  23 // The Library classes this module consumes
  24 //
  25 #include <Library/DebugLib.h>
  26 #include <Library/HobLib.h>
  27 #include <Library/IoLib.h>
  28 #include <Library/MemoryAllocationLib.h>
  29 #include <Library/PcdLib.h>
  30 #include <Library/PciLib.h>
  31 #include <Library/PeimEntryPoint.h>
  32 #include <Library/PeiServicesLib.h>
  33 #include <Library/QemuFwCfgLib.h>
  34 #include <Library/ResourcePublicationLib.h>
  35 #include <Guid/MemoryTypeInformation.h>
  36 #include <Ppi/MasterBootMode.h>
  37 #include <IndustryStandard/Pci22.h>
  38 #include <OvmfPlatforms.h>
  39
  40 #include "Platform.h"
  41 #include "Cmos.h"
  42
  43 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
  44   { EfiACPIMemoryNVS,       0x004 },
  45   { EfiACPIReclaimMemory,   0x008 },
  46   { EfiReservedMemoryType,  0x004 },
  47   { EfiRuntimeServicesData, 0x024 },
  48   { EfiRuntimeServicesCode, 0x030 },
  49   { EfiBootServicesCode,    0x180 },
  50   { EfiBootServicesData,    0xF00 },
  51   { EfiMaxMemoryType,       0x000 }
  52 };
  53
  54
  55 EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {
  56   {
  57     EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  58     &gEfiPeiMasterBootModePpiGuid,
  59     NULL
  60   }
  61 };
  62
  63
  64 UINT16 mHostBridgeDevId;
  65
  66 EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
  67
  68 BOOLEAN mS3Supported = FALSE;
  69
  70
  71 VOID
  72 AddIoMemoryBaseSizeHob (
  73   EFI_PHYSICAL_ADDRESS        MemoryBase,
  74   UINT64                      MemorySize
  75   )
  76 {
  77   BuildResourceDescriptorHob (
  78     EFI_RESOURCE_MEMORY_MAPPED_IO,
  79       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  80       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  81       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  82       EFI_RESOURCE_ATTRIBUTE_TESTED,
  83     MemoryBase,
  84     MemorySize
  85     );
  86 }
  87
  88 VOID
  89 AddReservedMemoryBaseSizeHob (
  90   EFI_PHYSICAL_ADDRESS        MemoryBase,
  91   UINT64                      MemorySize
  92   )
  93 {
  94   BuildResourceDescriptorHob (
  95     EFI_RESOURCE_MEMORY_RESERVED,
  96       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  97       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  98       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  99       EFI_RESOURCE_ATTRIBUTE_TESTED,
 100     MemoryBase,
 101     MemorySize
 102     );
 103 }
 104
 105 VOID
 106 AddIoMemoryRangeHob (
 107   EFI_PHYSICAL_ADDRESS        MemoryBase,
 108   EFI_PHYSICAL_ADDRESS        MemoryLimit
 109   )
 110 {
 111   AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 112 }
 113
 114
 115 VOID
 116 AddMemoryBaseSizeHob (
 117   EFI_PHYSICAL_ADDRESS        MemoryBase,
 118   UINT64                      MemorySize
 119   )
 120 {
 121   BuildResourceDescriptorHob (
 122     EFI_RESOURCE_SYSTEM_MEMORY,
 123       EFI_RESOURCE_ATTRIBUTE_PRESENT |
 124       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 125       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 126       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 127       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 128       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
 129       EFI_RESOURCE_ATTRIBUTE_TESTED,
 130     MemoryBase,
 131     MemorySize
 132     );
 133 }
 134
 135
 136 VOID
 137 AddMemoryRangeHob (
 138   EFI_PHYSICAL_ADDRESS        MemoryBase,
 139   EFI_PHYSICAL_ADDRESS        MemoryLimit
 140   )
 141 {
 142   AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 143 }
 144
 145
 146 VOID
 147 AddUntestedMemoryBaseSizeHob (
 148   EFI_PHYSICAL_ADDRESS        MemoryBase,
 149   UINT64                      MemorySize
 150   )
 151 {
 152   BuildResourceDescriptorHob (
 153     EFI_RESOURCE_SYSTEM_MEMORY,
 154       EFI_RESOURCE_ATTRIBUTE_PRESENT |
 155       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 156       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 157       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 158       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 159       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,
 160     MemoryBase,
 161     MemorySize
 162     );
 163 }
 164
 165
 166 VOID
 167 AddUntestedMemoryRangeHob (
 168   EFI_PHYSICAL_ADDRESS        MemoryBase,
 169   EFI_PHYSICAL_ADDRESS        MemoryLimit
 170   )
 171 {
 172   AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 173 }
 174
 175 VOID
 176 MemMapInitialization (
 177   VOID
 178   )
 179 {
 180   //
 181   // Create Memory Type Information HOB
 182   //
 183   BuildGuidDataHob (
 184     &gEfiMemoryTypeInformationGuid,
 185     mDefaultMemoryTypeInformation,
 186     sizeof(mDefaultMemoryTypeInformation)
 187     );
 188
 189   //
 190   // Add PCI IO Port space available for PCI resource allocations.
 191   //
 192   BuildResourceDescriptorHob (
 193     EFI_RESOURCE_IO,
 194     EFI_RESOURCE_ATTRIBUTE_PRESENT     |
 195     EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
 196     0xC000,
 197     0x4000
 198     );
 199
 200   //
 201   // Video memory + Legacy BIOS region
 202   //
 203   AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
 204
 205   if (!mXen) {
 206     UINT32  TopOfLowRam;
 207     TopOfLowRam = GetSystemMemorySizeBelow4gb ();
 208
 209     //
 210     // address       purpose   size
 211     // ------------  --------  -------------------------
 212     // max(top, 2g)  PCI MMIO  0xFC000000 - max(top, 2g)
 213     // 0xFC000000    gap                           44 MB
 214     // 0xFEC00000    IO-APIC                        4 KB
 215     // 0xFEC01000    gap                         1020 KB
 216     // 0xFED00000    HPET                           1 KB
 217     // 0xFED00400    gap                          111 KB
 218     // 0xFED1C000    gap (PIIX4) / RCRB (ICH9)     16 KB
 219     // 0xFED20000    gap                          896 KB
 220     // 0xFEE00000    LAPIC                          1 MB
 221     //
 222     AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ?
 223                          BASE_2GB : TopOfLowRam, 0xFC000000);
 224     AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
 225     AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
 226     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 227       AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
 228     }
 229     AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
 230   }
 231 }
 232
 233
 234 VOID
 235 MiscInitialization (
 236   VOID
 237   )
 238 {
 239   UINTN  PmCmd;
 240   UINTN  Pmba;
 241   UINTN  AcpiCtlReg;
 242   UINT8  AcpiEnBit;
 243
 244   //
 245   // Disable A20 Mask
 246   //
 247   IoOr8 (0x92, BIT1);
 248
 249   //
 250   // Build the CPU HOB with guest RAM size dependent address width and 16-bits
 251   // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
 252   // S3 resume as well, so we build it unconditionally.)
 253   //
 254   BuildCpuHob (mPhysMemAddressWidth, 16);
 255
 256   //
 257   // Determine platform type and save Host Bridge DID to PCD
 258   //
 259   switch (mHostBridgeDevId) {
 260     case INTEL_82441_DEVICE_ID:
 261       PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
 262       Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
 263       AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
 264       AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;
 265       break;
 266     case INTEL_Q35_MCH_DEVICE_ID:
 267       PmCmd      = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
 268       Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
 269       AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
 270       AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;
 271       break;
 272     default:
 273       DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
 274         __FUNCTION__, mHostBridgeDevId));
 275       ASSERT (FALSE);
 276       return;
 277   }
 278   PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
 279
 280   //
 281   // If the appropriate IOspace enable bit is set, assume the ACPI PMBA
 282   // has been configured (e.g., by Xen) and skip the setup here.
 283   // This matches the logic in AcpiTimerLibConstructor ().
 284   //
 285   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
 286     //
 287     // The PEI phase should be exited with fully accessibe ACPI PM IO space:
 288     // 1. set PMBA
 289     //
 290     PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));
 291
 292     //
 293     // 2. set PCICMD/IOSE
 294     //
 295     PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
 296
 297     //
 298     // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
 299     //
 300     PciOr8 (AcpiCtlReg, AcpiEnBit);
 301   }
 302
 303   if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 304     //
 305     // Set Root Complex Register Block BAR
 306     //
 307     PciWrite32 (
 308       POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),
 309       ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN
 310       );
 311   }
 312 }
 313
 314
 315 VOID
 316 BootModeInitialization (
 317   VOID
 318   )
 319 {
 320   EFI_STATUS    Status;
 321
 322   if (CmosRead8 (0xF) == 0xFE) {
 323     mBootMode = BOOT_ON_S3_RESUME;
 324   }
 325   CmosWrite8 (0xF, 0x00);
 326
 327   Status = PeiServicesSetBootMode (mBootMode);
 328   ASSERT_EFI_ERROR (Status);
 329
 330   Status = PeiServicesInstallPpi (mPpiBootMode);
 331   ASSERT_EFI_ERROR (Status);
 332 }
 333
 334
 335 VOID
 336 ReserveEmuVariableNvStore (
 337   )
 338 {
 339   EFI_PHYSICAL_ADDRESS VariableStore;
 340
 341   //
 342   // Allocate storage for NV variables early on so it will be
 343   // at a consistent address.  Since VM memory is preserved
 344   // across reboots, this allows the NV variable storage to survive
 345   // a VM reboot.
 346   //
 347   VariableStore =
 348     (EFI_PHYSICAL_ADDRESS)(UINTN)
 349       AllocateAlignedRuntimePages (
 350         EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),
 351         PcdGet32 (PcdFlashNvStorageFtwSpareSize)
 352         );
 353   DEBUG ((EFI_D_INFO,
 354           "Reserved variable store memory: 0x%lX; size: %dkb\n",
 355           VariableStore,
 356           (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
 357         ));
 358   PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);
 359 }
 360
 361
 362 VOID
 363 DebugDumpCmos (
 364   VOID
 365   )
 366 {
 367   UINT32 Loop;
 368
 369   DEBUG ((EFI_D_INFO, "CMOS:\n"));
 370
 371   for (Loop = 0; Loop < 0x80; Loop++) {
 372     if ((Loop % 0x10) == 0) {
 373       DEBUG ((EFI_D_INFO, "%02x:", Loop));
 374     }
 375     DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));
 376     if ((Loop % 0x10) == 0xf) {
 377       DEBUG ((EFI_D_INFO, "\n"));
 378     }
 379   }
 380 }
 381
 382
 383 /**
 384   Perform Platform PEI initialization.
 385
 386   @param  FileHandle      Handle of the file being invoked.
 387   @param  PeiServices     Describes the list of possible PEI Services.
 388
 389   @return EFI_SUCCESS     The PEIM initialized successfully.
 390
 391 **/
 392 EFI_STATUS
 393 EFIAPI
 394 InitializePlatform (
 395   IN       EFI_PEI_FILE_HANDLE  FileHandle,
 396   IN CONST EFI_PEI_SERVICES     **PeiServices
 397   )
 398 {
 399   DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));
 400
 401   DebugDumpCmos ();
 402
 403   XenDetect ();
 404
 405   if (QemuFwCfgS3Enabled ()) {
 406     DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));
 407     mS3Supported = TRUE;
 408   }
 409
 410   BootModeInitialization ();
 411   AddressWidthInitialization ();
 412
 413   PublishPeiMemory ();
 414
 415   InitializeRamRegions ();
 416
 417   if (mXen) {
 418     DEBUG ((EFI_D_INFO, "Xen was detected\n"));
 419     InitializeXen ();
 420   }
 421
 422   //
 423   // Query Host Bridge DID
 424   //
 425   mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
 426
 427   if (mBootMode != BOOT_ON_S3_RESUME) {
 428     ReserveEmuVariableNvStore ();
 429
 430     PeiFvInitialization ();
 431
 432     MemMapInitialization ();
 433   }
 434
 435   MiscInitialization ();
 436
 437   return EFI_SUCCESS;
 438 }