OvmfPkg/PlatformPei/Platform.c

   1 /**@file
   2   Platform PEI driver
   3
   4   Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
   5   Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
   6
   7   This program and the accompanying materials
   8   are licensed and made available under the terms and conditions of the BSD License
   9   which accompanies this distribution.  The full text of the license may be found at
  10   http://opensource.org/licenses/bsd-license.php
  11
  12   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15 **/
  16
  17 //
  18 // The package level header files this module uses
  19 //
  20 #include <PiPei.h>
  21
  22 //
  23 // The Library classes this module consumes
  24 //
  25 #include <Library/DebugLib.h>
  26 #include <Library/HobLib.h>
  27 #include <Library/IoLib.h>
  28 #include <Library/MemoryAllocationLib.h>
  29 #include <Library/PcdLib.h>
  30 #include <Library/PciLib.h>
  31 #include <Library/PeimEntryPoint.h>
  32 #include <Library/PeiServicesLib.h>
  33 #include <Library/QemuFwCfgLib.h>
  34 #include <Library/ResourcePublicationLib.h>
  35 #include <Guid/MemoryTypeInformation.h>
  36 #include <Ppi/MasterBootMode.h>
  37 #include <IndustryStandard/Pci22.h>
  38 #include <OvmfPlatforms.h>
  39
  40 #include "Platform.h"
  41 #include "Cmos.h"
  42
  43 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
  44   { EfiACPIMemoryNVS,       0x004 },
  45   { EfiACPIReclaimMemory,   0x008 },
  46   { EfiReservedMemoryType,  0x004 },
  47   { EfiRuntimeServicesData, 0x024 },
  48   { EfiRuntimeServicesCode, 0x030 },
  49   { EfiBootServicesCode,    0x180 },
  50   { EfiBootServicesData,    0xF00 },
  51   { EfiMaxMemoryType,       0x000 }
  52 };
  53
  54
  55 EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {
  56   {
  57     EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  58     &gEfiPeiMasterBootModePpiGuid,
  59     NULL
  60   }
  61 };
  62
  63
  64 UINT16 mHostBridgeDevId;
  65
  66 EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
  67
  68 BOOLEAN mS3Supported = FALSE;
  69
  70
  71 VOID
  72 AddIoMemoryBaseSizeHob (
  73   EFI_PHYSICAL_ADDRESS        MemoryBase,
  74   UINT64                      MemorySize
  75   )
  76 {
  77   BuildResourceDescriptorHob (
  78     EFI_RESOURCE_MEMORY_MAPPED_IO,
  79       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  80       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  81       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  82       EFI_RESOURCE_ATTRIBUTE_TESTED,
  83     MemoryBase,
  84     MemorySize
  85     );
  86 }
  87
  88 VOID
  89 AddReservedMemoryBaseSizeHob (
  90   EFI_PHYSICAL_ADDRESS        MemoryBase,
  91   UINT64                      MemorySize
  92   )
  93 {
  94   BuildResourceDescriptorHob (
  95     EFI_RESOURCE_MEMORY_RESERVED,
  96       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  97       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  98       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  99       EFI_RESOURCE_ATTRIBUTE_TESTED,
 100     MemoryBase,
 101     MemorySize
 102     );
 103 }
 104
 105 VOID
 106 AddIoMemoryRangeHob (
 107   EFI_PHYSICAL_ADDRESS        MemoryBase,
 108   EFI_PHYSICAL_ADDRESS        MemoryLimit
 109   )
 110 {
 111   AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 112 }
 113
 114
 115 VOID
 116 AddMemoryBaseSizeHob (
 117   EFI_PHYSICAL_ADDRESS        MemoryBase,
 118   UINT64                      MemorySize
 119   )
 120 {
 121   BuildResourceDescriptorHob (
 122     EFI_RESOURCE_SYSTEM_MEMORY,
 123       EFI_RESOURCE_ATTRIBUTE_PRESENT |
 124       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 125       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 126       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 127       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 128       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
 129       EFI_RESOURCE_ATTRIBUTE_TESTED,
 130     MemoryBase,
 131     MemorySize
 132     );
 133 }
 134
 135
 136 VOID
 137 AddMemoryRangeHob (
 138   EFI_PHYSICAL_ADDRESS        MemoryBase,
 139   EFI_PHYSICAL_ADDRESS        MemoryLimit
 140   )
 141 {
 142   AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 143 }
 144
 145
 146 VOID
 147 AddUntestedMemoryBaseSizeHob (
 148   EFI_PHYSICAL_ADDRESS        MemoryBase,
 149   UINT64                      MemorySize
 150   )
 151 {
 152   BuildResourceDescriptorHob (
 153     EFI_RESOURCE_SYSTEM_MEMORY,
 154       EFI_RESOURCE_ATTRIBUTE_PRESENT |
 155       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 156       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 157       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 158       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 159       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,
 160     MemoryBase,
 161     MemorySize
 162     );
 163 }
 164
 165
 166 VOID
 167 AddUntestedMemoryRangeHob (
 168   EFI_PHYSICAL_ADDRESS        MemoryBase,
 169   EFI_PHYSICAL_ADDRESS        MemoryLimit
 170   )
 171 {
 172   AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 173 }
 174
 175 VOID
 176 MemMapInitialization (
 177   VOID
 178   )
 179 {
 180   //
 181   // Create Memory Type Information HOB
 182   //
 183   BuildGuidDataHob (
 184     &gEfiMemoryTypeInformationGuid,
 185     mDefaultMemoryTypeInformation,
 186     sizeof(mDefaultMemoryTypeInformation)
 187     );
 188
 189   //
 190   // Add PCI IO Port space available for PCI resource allocations.
 191   //
 192   BuildResourceDescriptorHob (
 193     EFI_RESOURCE_IO,
 194     EFI_RESOURCE_ATTRIBUTE_PRESENT     |
 195     EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
 196     0xC000,
 197     0x4000
 198     );
 199
 200   //
 201   // Video memory + Legacy BIOS region
 202   //
 203   AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
 204
 205   if (!mXen) {
 206     UINT32  TopOfLowRam;
 207     UINT32  PciBase;
 208
 209     TopOfLowRam = GetSystemMemorySizeBelow4gb ();
 210     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 211       //
 212       // A 3GB base will always fall into Q35's 32-bit PCI host aperture,
 213       // regardless of the Q35 MMCONFIG BAR. Correspondingly, QEMU never lets
 214       // the RAM below 4 GB exceed it.
 215       //
 216       PciBase = BASE_2GB + BASE_1GB;
 217       ASSERT (TopOfLowRam <= PciBase);
 218     } else {
 219       PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;
 220     }
 221
 222     //
 223     // address       purpose   size
 224     // ------------  --------  -------------------------
 225     // max(top, 2g)  PCI MMIO  0xFC000000 - max(top, 2g)
 226     // 0xFC000000    gap                           44 MB
 227     // 0xFEC00000    IO-APIC                        4 KB
 228     // 0xFEC01000    gap                         1020 KB
 229     // 0xFED00000    HPET                           1 KB
 230     // 0xFED00400    gap                          111 KB
 231     // 0xFED1C000    gap (PIIX4) / RCRB (ICH9)     16 KB
 232     // 0xFED20000    gap                          896 KB
 233     // 0xFEE00000    LAPIC                          1 MB
 234     //
 235     AddIoMemoryRangeHob (PciBase, 0xFC000000);
 236     AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
 237     AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
 238     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 239       AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
 240     }
 241     AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
 242   }
 243 }
 244
 245
 246 VOID
 247 MiscInitialization (
 248   VOID
 249   )
 250 {
 251   UINTN  PmCmd;
 252   UINTN  Pmba;
 253   UINTN  AcpiCtlReg;
 254   UINT8  AcpiEnBit;
 255
 256   //
 257   // Disable A20 Mask
 258   //
 259   IoOr8 (0x92, BIT1);
 260
 261   //
 262   // Build the CPU HOB with guest RAM size dependent address width and 16-bits
 263   // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
 264   // S3 resume as well, so we build it unconditionally.)
 265   //
 266   BuildCpuHob (mPhysMemAddressWidth, 16);
 267
 268   //
 269   // Determine platform type and save Host Bridge DID to PCD
 270   //
 271   switch (mHostBridgeDevId) {
 272     case INTEL_82441_DEVICE_ID:
 273       PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
 274       Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
 275       AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
 276       AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;
 277       break;
 278     case INTEL_Q35_MCH_DEVICE_ID:
 279       PmCmd      = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
 280       Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
 281       AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
 282       AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;
 283       break;
 284     default:
 285       DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
 286         __FUNCTION__, mHostBridgeDevId));
 287       ASSERT (FALSE);
 288       return;
 289   }
 290   PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
 291
 292   //
 293   // If the appropriate IOspace enable bit is set, assume the ACPI PMBA
 294   // has been configured (e.g., by Xen) and skip the setup here.
 295   // This matches the logic in AcpiTimerLibConstructor ().
 296   //
 297   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
 298     //
 299     // The PEI phase should be exited with fully accessibe ACPI PM IO space:
 300     // 1. set PMBA
 301     //
 302     PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));
 303
 304     //
 305     // 2. set PCICMD/IOSE
 306     //
 307     PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
 308
 309     //
 310     // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
 311     //
 312     PciOr8 (AcpiCtlReg, AcpiEnBit);
 313   }
 314
 315   if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 316     //
 317     // Set Root Complex Register Block BAR
 318     //
 319     PciWrite32 (
 320       POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),
 321       ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN
 322       );
 323   }
 324 }
 325
 326
 327 VOID
 328 BootModeInitialization (
 329   VOID
 330   )
 331 {
 332   EFI_STATUS    Status;
 333
 334   if (CmosRead8 (0xF) == 0xFE) {
 335     mBootMode = BOOT_ON_S3_RESUME;
 336   }
 337   CmosWrite8 (0xF, 0x00);
 338
 339   Status = PeiServicesSetBootMode (mBootMode);
 340   ASSERT_EFI_ERROR (Status);
 341
 342   Status = PeiServicesInstallPpi (mPpiBootMode);
 343   ASSERT_EFI_ERROR (Status);
 344 }
 345
 346
 347 VOID
 348 ReserveEmuVariableNvStore (
 349   )
 350 {
 351   EFI_PHYSICAL_ADDRESS VariableStore;
 352
 353   //
 354   // Allocate storage for NV variables early on so it will be
 355   // at a consistent address.  Since VM memory is preserved
 356   // across reboots, this allows the NV variable storage to survive
 357   // a VM reboot.
 358   //
 359   VariableStore =
 360     (EFI_PHYSICAL_ADDRESS)(UINTN)
 361       AllocateAlignedRuntimePages (
 362         EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),
 363         PcdGet32 (PcdFlashNvStorageFtwSpareSize)
 364         );
 365   DEBUG ((EFI_D_INFO,
 366           "Reserved variable store memory: 0x%lX; size: %dkb\n",
 367           VariableStore,
 368           (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
 369         ));
 370   PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);
 371 }
 372
 373
 374 VOID
 375 DebugDumpCmos (
 376   VOID
 377   )
 378 {
 379   UINT32 Loop;
 380
 381   DEBUG ((EFI_D_INFO, "CMOS:\n"));
 382
 383   for (Loop = 0; Loop < 0x80; Loop++) {
 384     if ((Loop % 0x10) == 0) {
 385       DEBUG ((EFI_D_INFO, "%02x:", Loop));
 386     }
 387     DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));
 388     if ((Loop % 0x10) == 0xf) {
 389       DEBUG ((EFI_D_INFO, "\n"));
 390     }
 391   }
 392 }
 393
 394
 395 /**
 396   Perform Platform PEI initialization.
 397
 398   @param  FileHandle      Handle of the file being invoked.
 399   @param  PeiServices     Describes the list of possible PEI Services.
 400
 401   @return EFI_SUCCESS     The PEIM initialized successfully.
 402
 403 **/
 404 EFI_STATUS
 405 EFIAPI
 406 InitializePlatform (
 407   IN       EFI_PEI_FILE_HANDLE  FileHandle,
 408   IN CONST EFI_PEI_SERVICES     **PeiServices
 409   )
 410 {
 411   DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));
 412
 413   DebugDumpCmos ();
 414
 415   XenDetect ();
 416
 417   if (QemuFwCfgS3Enabled ()) {
 418     DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));
 419     mS3Supported = TRUE;
 420   }
 421
 422   BootModeInitialization ();
 423   AddressWidthInitialization ();
 424
 425   PublishPeiMemory ();
 426
 427   InitializeRamRegions ();
 428
 429   if (mXen) {
 430     DEBUG ((EFI_D_INFO, "Xen was detected\n"));
 431     InitializeXen ();
 432   }
 433
 434   //
 435   // Query Host Bridge DID
 436   //
 437   mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
 438
 439   if (mBootMode != BOOT_ON_S3_RESUME) {
 440     ReserveEmuVariableNvStore ();
 441
 442     PeiFvInitialization ();
 443
 444     MemMapInitialization ();
 445   }
 446
 447   MiscInitialization ();
 448
 449   return EFI_SUCCESS;
 450 }