OvmfPkg/ResetVector/Ia32/AmdSev.asm

   1 ;------------------------------------------------------------------------------
   2 ; @file
   3 ; Provide the functions to check whether SEV and SEV-ES is enabled.
   4 ;
   5 ; Copyright (c) 2017 - 2021, Advanced Micro Devices, Inc. All rights reserved.<BR>
   6 ; SPDX-License-Identifier: BSD-2-Clause-Patent
   7 ;
   8 ;------------------------------------------------------------------------------
   9
  10 BITS    32
  11
  12 ;
  13 ; SEV-ES #VC exception handler support
  14 ;
  15 ; #VC handler local variable locations
  16 ;
  17 %define VC_CPUID_RESULT_EAX         0
  18 %define VC_CPUID_RESULT_EBX         4
  19 %define VC_CPUID_RESULT_ECX         8
  20 %define VC_CPUID_RESULT_EDX        12
  21 %define VC_GHCB_MSR_EDX            16
  22 %define VC_GHCB_MSR_EAX            20
  23 %define VC_CPUID_REQUEST_REGISTER  24
  24 %define VC_CPUID_FUNCTION          28
  25
  26 ; #VC handler total local variable size
  27 ;
  28 %define VC_VARIABLE_SIZE           32
  29
  30 ; #VC handler GHCB CPUID request/response protocol values
  31 ;
  32 %define GHCB_CPUID_REQUEST          4
  33 %define GHCB_CPUID_RESPONSE         5
  34 %define GHCB_CPUID_REGISTER_SHIFT  30
  35 %define CPUID_INSN_LEN              2
  36
  37
  38 %define SEV_GHCB_MSR                0xc0010130
  39 %define SEV_STATUS_MSR              0xc0010131
  40
  41 ; The #VC was not for CPUID
  42 %define TERM_VC_NOT_CPUID           1
  43
  44 ; The unexpected response code
  45 %define TERM_UNEXPECTED_RESP_CODE   2
  46
  47
  48 ; Macro is used to issue the MSR protocol based VMGEXIT. The caller is
  49 ; responsible to populate values in the EDX:EAX registers. After the vmmcall
  50 ; returns, it verifies that the response code matches with the expected
  51 ; code. If it does not match then terminate the guest. The result of request
  52 ; is returned in the EDX:EAX.
  53 ;
  54 ; args 1:Request code, 2: Response code
  55 %macro VmgExit 2
  56     ;
  57     ; Add request code:
  58     ;   GHCB_MSR[11:0]  = Request code
  59     or      eax, %1
  60
  61     mov     ecx, SEV_GHCB_MSR
  62     wrmsr
  63
  64     ; Issue VMGEXIT - NASM doesn't support the vmmcall instruction in 32-bit
  65     ; mode, so work around this by temporarily switching to 64-bit mode.
  66     ;
  67 BITS    64
  68     rep     vmmcall
  69 BITS    32
  70
  71     mov     ecx, SEV_GHCB_MSR
  72     rdmsr
  73
  74     ;
  75     ; Verify the reponse code, if it does not match then request to terminate
  76     ;   GHCB_MSR[11:0]  = Response code
  77     mov     ecx, eax
  78     and     ecx, 0xfff
  79     cmp     ecx, %2
  80     jne     SevEsUnexpectedRespTerminate
  81 %endmacro
  82
  83 ; Macro to terminate the guest using the VMGEXIT.
  84 ; arg 1: reason code
  85 %macro TerminateVmgExit 1
  86     mov     eax, %1
  87     ;
  88     ; Use VMGEXIT to request termination. At this point the reason code is
  89     ; located in EAX, so shift it left 16 bits to the proper location.
  90     ;
  91     ; EAX[11:0]  => 0x100 - request termination
  92     ; EAX[15:12] => 0x1   - OVMF
  93     ; EAX[23:16] => 0xXX  - REASON CODE
  94     ;
  95     shl     eax, 16
  96     or      eax, 0x1100
  97     xor     edx, edx
  98     mov     ecx, SEV_GHCB_MSR
  99     wrmsr
 100     ;
 101     ; Issue VMGEXIT - NASM doesn't support the vmmcall instruction in 32-bit
 102     ; mode, so work around this by temporarily switching to 64-bit mode.
 103     ;
 104 BITS    64
 105     rep     vmmcall
 106 BITS    32
 107
 108     ;
 109     ; We shouldn't come back from the VMGEXIT, but if we do, just loop.
 110     ;
 111 %%TerminateHlt:
 112     hlt
 113     jmp     %%TerminateHlt
 114 %endmacro
 115
 116 ; Terminate the guest due to unexpected response code.
 117 SevEsUnexpectedRespTerminate:
 118     TerminateVmgExit    TERM_UNEXPECTED_RESP_CODE
 119
 120 ; Check if Secure Encrypted Virtualization (SEV) features are enabled.
 121 ;
 122 ; Register usage is tight in this routine, so multiple calls for the
 123 ; same CPUID and MSR data are performed to keep things simple.
 124 ;
 125 ; Modified:  EAX, EBX, ECX, EDX, ESP
 126 ;
 127 ; If SEV is enabled then EAX will be at least 32.
 128 ; If SEV is disabled then EAX will be zero.
 129 ;
 130 CheckSevFeatures:
 131     ; Set the first byte of the workarea to zero to communicate to the SEC
 132     ; phase that SEV-ES is not enabled. If SEV-ES is enabled, the CPUID
 133     ; instruction will trigger a #VC exception where the first byte of the
 134     ; workarea will be set to one or, if CPUID is not being intercepted,
 135     ; the MSR check below will set the first byte of the workarea to one.
 136     mov     byte[SEV_ES_WORK_AREA], 0
 137
 138     ;
 139     ; Set up exception handlers to check for SEV-ES
 140     ;   Load temporary RAM stack based on PCDs (see SevEsIdtVmmComm for
 141     ;   stack usage)
 142     ;   Establish exception handlers
 143     ;
 144     mov       esp, SEV_ES_VC_TOP_OF_STACK
 145     mov       eax, ADDR_OF(Idtr)
 146     lidt      [cs:eax]
 147
 148     ; Check if we have a valid (0x8000_001F) CPUID leaf
 149     ;   CPUID raises a #VC exception if running as an SEV-ES guest
 150     mov       eax, 0x80000000
 151     cpuid
 152
 153     ; This check should fail on Intel or Non SEV AMD CPUs. In future if
 154     ; Intel CPUs supports this CPUID leaf then we are guranteed to have exact
 155     ; same bit definition.
 156     cmp       eax, 0x8000001f
 157     jl        NoSev
 158
 159     ; Check for SEV memory encryption feature:
 160     ; CPUID  Fn8000_001F[EAX] - Bit 1
 161     ;   CPUID raises a #VC exception if running as an SEV-ES guest
 162     mov       eax, 0x8000001f
 163     cpuid
 164     bt        eax, 1
 165     jnc       NoSev
 166
 167     ; Check if SEV memory encryption is enabled
 168     ;  MSR_0xC0010131 - Bit 0 (SEV enabled)
 169     mov       ecx, SEV_STATUS_MSR
 170     rdmsr
 171     bt        eax, 0
 172     jnc       NoSev
 173
 174     ; Check for SEV-ES memory encryption feature:
 175     ; CPUID  Fn8000_001F[EAX] - Bit 3
 176     ;   CPUID raises a #VC exception if running as an SEV-ES guest
 177     mov       eax, 0x8000001f
 178     cpuid
 179     bt        eax, 3
 180     jnc       GetSevEncBit
 181
 182     ; Check if SEV-ES is enabled
 183     ;  MSR_0xC0010131 - Bit 1 (SEV-ES enabled)
 184     mov       ecx, SEV_STATUS_MSR
 185     rdmsr
 186     bt        eax, 1
 187     jnc       GetSevEncBit
 188
 189     ; Set the first byte of the workarea to one to communicate to the SEC
 190     ; phase that SEV-ES is enabled.
 191     mov       byte[SEV_ES_WORK_AREA], 1
 192
 193 GetSevEncBit:
 194     ; Get pte bit position to enable memory encryption
 195     ; CPUID Fn8000_001F[EBX] - Bits 5:0
 196     ;
 197     and       ebx, 0x3f
 198     mov       eax, ebx
 199
 200     ; The encryption bit position is always above 31
 201     sub       ebx, 32
 202     jns       SevSaveMask
 203
 204     ; Encryption bit was reported as 31 or below, enter a HLT loop
 205 SevEncBitLowHlt:
 206     cli
 207     hlt
 208     jmp       SevEncBitLowHlt
 209
 210 SevSaveMask:
 211     xor       edx, edx
 212     bts       edx, ebx
 213
 214     mov       dword[SEV_ES_WORK_AREA_ENC_MASK], 0
 215     mov       dword[SEV_ES_WORK_AREA_ENC_MASK + 4], edx
 216     jmp       SevExit
 217
 218 NoSev:
 219     ;
 220     ; Perform an SEV-ES sanity check by seeing if a #VC exception occurred.
 221     ;
 222     cmp       byte[SEV_ES_WORK_AREA], 0
 223     jz        NoSevPass
 224
 225     ;
 226     ; A #VC was received, yet CPUID indicates no SEV-ES support, something
 227     ; isn't right.
 228     ;
 229 NoSevEsVcHlt:
 230     cli
 231     hlt
 232     jmp       NoSevEsVcHlt
 233
 234 NoSevPass:
 235     xor       eax, eax
 236
 237 SevExit:
 238     ;
 239     ; Clear exception handlers and stack
 240     ;
 241     push      eax
 242     mov       eax, ADDR_OF(IdtrClear)
 243     lidt      [cs:eax]
 244     pop       eax
 245     mov       esp, 0
 246
 247     OneTimeCallRet CheckSevFeatures
 248
 249 ; Check if Secure Encrypted Virtualization - Encrypted State (SEV-ES) feature
 250 ; is enabled.
 251 ;
 252 ; Modified:  EAX
 253 ;
 254 ; If SEV-ES is enabled then EAX will be non-zero.
 255 ; If SEV-ES is disabled then EAX will be zero.
 256 ;
 257 IsSevEsEnabled:
 258     xor       eax, eax
 259
 260     ; During CheckSevFeatures, the SEV_ES_WORK_AREA was set to 1 if
 261     ; SEV-ES is enabled.
 262     cmp       byte[SEV_ES_WORK_AREA], 1
 263     jne       SevEsDisabled
 264
 265     mov       eax, 1
 266
 267 SevEsDisabled:
 268     OneTimeCallRet IsSevEsEnabled
 269
 270 ; Start of #VC exception handling routines
 271 ;
 272
 273 SevEsIdtNotCpuid:
 274     TerminateVmgExit TERM_VC_NOT_CPUID
 275     iret
 276
 277     ;
 278     ; Total stack usage for the #VC handler is 44 bytes:
 279     ;   - 12 bytes for the exception IRET (after popping error code)
 280     ;   - 32 bytes for the local variables.
 281     ;
 282 SevEsIdtVmmComm:
 283     ;
 284     ; If we're here, then we are an SEV-ES guest and this
 285     ; was triggered by a CPUID instruction
 286     ;
 287     ; Set the first byte of the workarea to one to communicate that
 288     ; a #VC was taken.
 289     mov     byte[SEV_ES_WORK_AREA], 1
 290
 291     pop     ecx                     ; Error code
 292     cmp     ecx, 0x72               ; Be sure it was CPUID
 293     jne     SevEsIdtNotCpuid
 294
 295     ; Set up local variable room on the stack
 296     ;   CPUID function         : + 28
 297     ;   CPUID request register : + 24
 298     ;   GHCB MSR (EAX)         : + 20
 299     ;   GHCB MSR (EDX)         : + 16
 300     ;   CPUID result (EDX)     : + 12
 301     ;   CPUID result (ECX)     : + 8
 302     ;   CPUID result (EBX)     : + 4
 303     ;   CPUID result (EAX)     : + 0
 304     sub     esp, VC_VARIABLE_SIZE
 305
 306     ; Save the CPUID function being requested
 307     mov     [esp + VC_CPUID_FUNCTION], eax
 308
 309     ; The GHCB CPUID protocol uses the following mapping to request
 310     ; a specific register:
 311     ;   0 => EAX, 1 => EBX, 2 => ECX, 3 => EDX
 312     ;
 313     ; Set EAX as the first register to request. This will also be used as a
 314     ; loop variable to request all register values (EAX to EDX).
 315     xor     eax, eax
 316     mov     [esp + VC_CPUID_REQUEST_REGISTER], eax
 317
 318     ; Save current GHCB MSR value
 319     mov     ecx, SEV_GHCB_MSR
 320     rdmsr
 321     mov     [esp + VC_GHCB_MSR_EAX], eax
 322     mov     [esp + VC_GHCB_MSR_EDX], edx
 323
 324 NextReg:
 325     ;
 326     ; Setup GHCB MSR
 327     ;   GHCB_MSR[63:32] = CPUID function
 328     ;   GHCB_MSR[31:30] = CPUID register
 329     ;   GHCB_MSR[11:0]  = CPUID request protocol
 330     ;
 331     mov     eax, [esp + VC_CPUID_REQUEST_REGISTER]
 332     cmp     eax, 4
 333     jge     VmmDone
 334
 335     shl     eax, GHCB_CPUID_REGISTER_SHIFT
 336     mov     edx, [esp + VC_CPUID_FUNCTION]
 337
 338     VmgExit GHCB_CPUID_REQUEST, GHCB_CPUID_RESPONSE
 339
 340     ;
 341     ; Response GHCB MSR
 342     ;   GHCB_MSR[63:32] = CPUID register value
 343     ;   GHCB_MSR[31:30] = CPUID register
 344     ;   GHCB_MSR[11:0]  = CPUID response protocol
 345     ;
 346
 347     ; Save returned value
 348     shr     eax, GHCB_CPUID_REGISTER_SHIFT
 349     mov     [esp + eax * 4], edx
 350
 351     ; Next register
 352     inc     word [esp + VC_CPUID_REQUEST_REGISTER]
 353
 354     jmp     NextReg
 355
 356 VmmDone:
 357     ;
 358     ; At this point we have all CPUID register values. Restore the GHCB MSR,
 359     ; set the return register values and return.
 360     ;
 361     mov     eax, [esp + VC_GHCB_MSR_EAX]
 362     mov     edx, [esp + VC_GHCB_MSR_EDX]
 363     mov     ecx, SEV_GHCB_MSR
 364     wrmsr
 365
 366     mov     eax, [esp + VC_CPUID_RESULT_EAX]
 367     mov     ebx, [esp + VC_CPUID_RESULT_EBX]
 368     mov     ecx, [esp + VC_CPUID_RESULT_ECX]
 369     mov     edx, [esp + VC_CPUID_RESULT_EDX]
 370
 371     add     esp, VC_VARIABLE_SIZE
 372
 373     ; Update the EIP value to skip over the now handled CPUID instruction
 374     ; (the CPUID instruction has a length of 2)
 375     add     word [esp], CPUID_INSN_LEN
 376     iret
 377
 378 ALIGN   2
 379
 380 Idtr:
 381     dw      IDT_END - IDT_BASE - 1  ; Limit
 382     dd      ADDR_OF(IDT_BASE)       ; Base
 383
 384 IdtrClear:
 385     dw      0                       ; Limit
 386     dd      0                       ; Base
 387
 388 ALIGN   16
 389
 390 ;
 391 ; The Interrupt Descriptor Table (IDT)
 392 ;   This will be used to determine if SEV-ES is enabled.  Upon execution
 393 ;   of the CPUID instruction, a VMM Communication Exception will occur.
 394 ;   This will tell us if SEV-ES is enabled.  We can use the current value
 395 ;   of the GHCB MSR to determine the SEV attributes.
 396 ;
 397 IDT_BASE:
 398 ;
 399 ; Vectors 0 - 28 (No handlers)
 400 ;
 401 %rep 29
 402     dw      0                                    ; Offset low bits 15..0
 403     dw      0x10                                 ; Selector
 404     db      0                                    ; Reserved
 405     db      0x8E                                 ; Gate Type (IA32_IDT_GATE_TYPE_INTERRUPT_32)
 406     dw      0                                    ; Offset high bits 31..16
 407 %endrep
 408 ;
 409 ; Vector 29 (VMM Communication Exception)
 410 ;
 411     dw      (ADDR_OF(SevEsIdtVmmComm) & 0xffff)  ; Offset low bits 15..0
 412     dw      0x10                                 ; Selector
 413     db      0                                    ; Reserved
 414     db      0x8E                                 ; Gate Type (IA32_IDT_GATE_TYPE_INTERRUPT_32)
 415     dw      (ADDR_OF(SevEsIdtVmmComm) >> 16)     ; Offset high bits 31..16
 416 ;
 417 ; Vectors 30 - 31 (No handlers)
 418 ;
 419 %rep 2
 420     dw      0                                    ; Offset low bits 15..0
 421     dw      0x10                                 ; Selector
 422     db      0                                    ; Reserved
 423     db      0x8E                                 ; Gate Type (IA32_IDT_GATE_TYPE_INTERRUPT_32)
 424     dw      0                                    ; Offset high bits 31..16
 425 %endrep
 426 IDT_END: