1 ;------------------------------------------------------------------------------
3 ; Sets the CR3 register for 64-bit paging
5 ; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
6 ; Copyright (c) 2017 - 2020, Advanced Micro Devices, Inc. All rights reserved.<BR>
7 ; SPDX-License-Identifier: BSD-2-Clause-Patent
9 ;------------------------------------------------------------------------------
13 %define PAGE_PRESENT 0x01
14 %define PAGE_READ_WRITE 0x02
15 %define PAGE_USER_SUPERVISOR 0x04
16 %define PAGE_WRITE_THROUGH 0x08
17 %define PAGE_CACHE_DISABLE 0x010
18 %define PAGE_ACCESSED 0x020
19 %define PAGE_DIRTY 0x040
20 %define PAGE_PAT 0x080
21 %define PAGE_GLOBAL 0x0100
22 %define PAGE_2M_MBO 0x080
23 %define PAGE_2M_PAT 0x01000
25 %define PAGE_4K_PDE_ATTR (PAGE_ACCESSED + \
30 %define PAGE_2M_PDE_ATTR (PAGE_2M_MBO + \
36 %define PAGE_PDP_ATTR (PAGE_ACCESSED + \
41 ; Modified: EAX, EBX, ECX, EDX
43 SetCr3ForPageTables64:
45 ; Clear the WorkArea header. The SEV probe routines will populate the
46 ; work area when detected.
47 mov byte[WORK_AREA_GUEST_TYPE], 0
49 ; Check whether the SEV is active and populate the SevEsWorkArea
50 OneTimeCall CheckSevFeatures
52 ; If SEV is enabled, the C-bit position is always above 31.
53 ; The mask will be saved in the EDX and applied during the
54 ; the page table build below.
55 OneTimeCall GetSevCBitMaskAbove31
58 ; For OVMF, build some initial page tables at
59 ; PcdOvmfSecPageTablesBase - (PcdOvmfSecPageTablesBase + 0x6000).
61 ; This range should match with PcdOvmfSecPageTablesSize which is
62 ; declared in the FDF files.
64 ; At the end of PEI, the pages tables will be rebuilt into a
65 ; more permanent location by DxeIpl.
68 mov ecx, 6 * 0x1000 / 4
70 clearPageTablesMemoryLoop:
71 mov dword[ecx * 4 + PT_ADDR (0) - 4], eax
72 loop clearPageTablesMemoryLoop
75 ; Top level Page Directory Pointers (1 * 512GB entry)
77 mov dword[PT_ADDR (0)], PT_ADDR (0x1000) + PAGE_PDP_ATTR
78 mov dword[PT_ADDR (4)], edx
81 ; Next level Page Directory Pointers (4 * 1GB entries => 4GB)
83 mov dword[PT_ADDR (0x1000)], PT_ADDR (0x2000) + PAGE_PDP_ATTR
84 mov dword[PT_ADDR (0x1004)], edx
85 mov dword[PT_ADDR (0x1008)], PT_ADDR (0x3000) + PAGE_PDP_ATTR
86 mov dword[PT_ADDR (0x100C)], edx
87 mov dword[PT_ADDR (0x1010)], PT_ADDR (0x4000) + PAGE_PDP_ATTR
88 mov dword[PT_ADDR (0x1014)], edx
89 mov dword[PT_ADDR (0x1018)], PT_ADDR (0x5000) + PAGE_PDP_ATTR
90 mov dword[PT_ADDR (0x101C)], edx
93 ; Page Table Entries (2048 * 2MB entries => 4GB)
100 add eax, PAGE_2M_PDE_ATTR
101 mov [ecx * 8 + PT_ADDR (0x2000 - 8)], eax
102 mov [(ecx * 8 + PT_ADDR (0x2000 - 8)) + 4], edx
103 loop pageTableEntriesLoop
105 ; Clear the C-bit from the GHCB page if the SEV-ES is enabled.
106 OneTimeCall SevClearPageEncMaskForGhcbPage
110 ; Set CR3 now that the paging structures are available
115 OneTimeCallRet SetCr3ForPageTables64