OvmfPkg/XenPlatformPei/MemDetect.c

   1 /**@file
   2   Memory Detection for Virtual Machines.
   3
   4   Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
   5   Copyright (c) 2019, Citrix Systems, Inc.
   6
   7   SPDX-License-Identifier: BSD-2-Clause-Patent
   8
   9 Module Name:
  10
  11   MemDetect.c
  12
  13 **/
  14
  15 //
  16 // The package level header files this module uses
  17 //
  18 #include <IndustryStandard/Q35MchIch9.h>
  19 #include <PiPei.h>
  20
  21 //
  22 // The Library classes this module consumes
  23 //
  24 #include <Library/BaseLib.h>
  25 #include <Library/BaseMemoryLib.h>
  26 #include <Library/DebugLib.h>
  27 #include <Library/HobLib.h>
  28 #include <Library/IoLib.h>
  29 #include <Library/PcdLib.h>
  30 #include <Library/PciLib.h>
  31 #include <Library/PeimEntryPoint.h>
  32 #include <Library/ResourcePublicationLib.h>
  33
  34 #include "Platform.h"
  35 #include "Cmos.h"
  36
  37 UINT8  mPhysMemAddressWidth;
  38
  39 STATIC UINT32  mS3AcpiReservedMemoryBase;
  40 STATIC UINT32  mS3AcpiReservedMemorySize;
  41
  42 STATIC UINT16  mQ35TsegMbytes;
  43
  44 VOID
  45 Q35TsegMbytesInitialization (
  46   VOID
  47   )
  48 {
  49   UINT16         ExtendedTsegMbytes;
  50   RETURN_STATUS  PcdStatus;
  51
  52   if (mHostBridgeDevId != INTEL_Q35_MCH_DEVICE_ID) {
  53     DEBUG ((
  54       DEBUG_ERROR,
  55       "%a: no TSEG (SMRAM) on host bridge DID=0x%04x; "
  56       "only DID=0x%04x (Q35) is supported\n",
  57       __FUNCTION__,
  58       mHostBridgeDevId,
  59       INTEL_Q35_MCH_DEVICE_ID
  60       ));
  61     ASSERT (FALSE);
  62     CpuDeadLoop ();
  63   }
  64
  65   //
  66   // Check if QEMU offers an extended TSEG.
  67   //
  68   // This can be seen from writing MCH_EXT_TSEG_MB_QUERY to the MCH_EXT_TSEG_MB
  69   // register, and reading back the register.
  70   //
  71   // On a QEMU machine type that does not offer an extended TSEG, the initial
  72   // write overwrites whatever value a malicious guest OS may have placed in
  73   // the (unimplemented) register, before entering S3 or rebooting.
  74   // Subsequently, the read returns MCH_EXT_TSEG_MB_QUERY unchanged.
  75   //
  76   // On a QEMU machine type that offers an extended TSEG, the initial write
  77   // triggers an update to the register. Subsequently, the value read back
  78   // (which is guaranteed to differ from MCH_EXT_TSEG_MB_QUERY) tells us the
  79   // number of megabytes.
  80   //
  81   PciWrite16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB), MCH_EXT_TSEG_MB_QUERY);
  82   ExtendedTsegMbytes = PciRead16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB));
  83   if (ExtendedTsegMbytes == MCH_EXT_TSEG_MB_QUERY) {
  84     mQ35TsegMbytes = PcdGet16 (PcdQ35TsegMbytes);
  85     return;
  86   }
  87
  88   DEBUG ((
  89     DEBUG_INFO,
  90     "%a: QEMU offers an extended TSEG (%d MB)\n",
  91     __FUNCTION__,
  92     ExtendedTsegMbytes
  93     ));
  94   PcdStatus = PcdSet16S (PcdQ35TsegMbytes, ExtendedTsegMbytes);
  95   ASSERT_RETURN_ERROR (PcdStatus);
  96   mQ35TsegMbytes = ExtendedTsegMbytes;
  97 }
  98
  99 STATIC
 100 UINT64
 101 GetHighestSystemMemoryAddress (
 102   BOOLEAN  Below4gb
 103   )
 104 {
 105   EFI_E820_ENTRY64  *E820Map;
 106   UINT32            E820EntriesCount;
 107   EFI_E820_ENTRY64  *Entry;
 108   EFI_STATUS        Status;
 109   UINT32            Loop;
 110   UINT64            HighestAddress;
 111   UINT64            EntryEnd;
 112
 113   HighestAddress = 0;
 114
 115   Status = XenGetE820Map (&E820Map, &E820EntriesCount);
 116   ASSERT_EFI_ERROR (Status);
 117
 118   for (Loop = 0; Loop < E820EntriesCount; Loop++) {
 119     Entry    = E820Map + Loop;
 120     EntryEnd = Entry->BaseAddr + Entry->Length;
 121
 122     if ((Entry->Type == EfiAcpiAddressRangeMemory) &&
 123         (EntryEnd > HighestAddress))
 124     {
 125       if (Below4gb && (EntryEnd <= BASE_4GB)) {
 126         HighestAddress = EntryEnd;
 127       } else if (!Below4gb && (EntryEnd >= BASE_4GB)) {
 128         HighestAddress = EntryEnd;
 129       }
 130     }
 131   }
 132
 133   //
 134   // Round down the end address.
 135   //
 136   return HighestAddress & ~(UINT64)EFI_PAGE_MASK;
 137 }
 138
 139 UINT32
 140 GetSystemMemorySizeBelow4gb (
 141   VOID
 142   )
 143 {
 144   UINT8  Cmos0x34;
 145   UINT8  Cmos0x35;
 146
 147   //
 148   // In PVH case, there is no CMOS, we have to calculate the memory size
 149   // from parsing the E820
 150   //
 151   if (XenPvhDetected ()) {
 152     UINT64  HighestAddress;
 153
 154     HighestAddress = GetHighestSystemMemoryAddress (TRUE);
 155     ASSERT (HighestAddress > 0 && HighestAddress <= BASE_4GB);
 156
 157     return (UINT32)HighestAddress;
 158   }
 159
 160   //
 161   // CMOS 0x34/0x35 specifies the system memory above 16 MB.
 162   // * CMOS(0x35) is the high byte
 163   // * CMOS(0x34) is the low byte
 164   // * The size is specified in 64kb chunks
 165   // * Since this is memory above 16MB, the 16MB must be added
 166   //   into the calculation to get the total memory size.
 167   //
 168
 169   Cmos0x34 = (UINT8)CmosRead8 (0x34);
 170   Cmos0x35 = (UINT8)CmosRead8 (0x35);
 171
 172   return (UINT32)(((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB);
 173 }
 174
 175 /**
 176   Initialize the mPhysMemAddressWidth variable, based on CPUID data.
 177 **/
 178 VOID
 179 AddressWidthInitialization (
 180   VOID
 181   )
 182 {
 183   UINT32  RegEax;
 184
 185   AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
 186   if (RegEax >= 0x80000008) {
 187     AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
 188     mPhysMemAddressWidth = (UINT8)RegEax;
 189   } else {
 190     mPhysMemAddressWidth = 36;
 191   }
 192
 193   //
 194   // IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses.
 195   //
 196   ASSERT (mPhysMemAddressWidth <= 52);
 197   if (mPhysMemAddressWidth > 48) {
 198     mPhysMemAddressWidth = 48;
 199   }
 200 }
 201
 202 /**
 203   Calculate the cap for the permanent PEI memory.
 204 **/
 205 STATIC
 206 UINT32
 207 GetPeiMemoryCap (
 208   VOID
 209   )
 210 {
 211   BOOLEAN  Page1GSupport;
 212   UINT32   RegEax;
 213   UINT32   RegEdx;
 214   UINT32   Pml4Entries;
 215   UINT32   PdpEntries;
 216   UINTN    TotalPages;
 217
 218   //
 219   // If DXE is 32-bit, then just return the traditional 64 MB cap.
 220   //
 221  #ifdef MDE_CPU_IA32
 222   if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {
 223     return SIZE_64MB;
 224   }
 225
 226  #endif
 227
 228   //
 229   // Dependent on physical address width, PEI memory allocations can be
 230   // dominated by the page tables built for 64-bit DXE. So we key the cap off
 231   // of those. The code below is based on CreateIdentityMappingPageTables() in
 232   // "MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c".
 233   //
 234   Page1GSupport = FALSE;
 235   if (PcdGetBool (PcdUse1GPageTable)) {
 236     AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
 237     if (RegEax >= 0x80000001) {
 238       AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);
 239       if ((RegEdx & BIT26) != 0) {
 240         Page1GSupport = TRUE;
 241       }
 242     }
 243   }
 244
 245   if (mPhysMemAddressWidth <= 39) {
 246     Pml4Entries = 1;
 247     PdpEntries  = 1 << (mPhysMemAddressWidth - 30);
 248     ASSERT (PdpEntries <= 0x200);
 249   } else {
 250     Pml4Entries = 1 << (mPhysMemAddressWidth - 39);
 251     ASSERT (Pml4Entries <= 0x200);
 252     PdpEntries = 512;
 253   }
 254
 255   TotalPages = Page1GSupport ? Pml4Entries + 1 :
 256                (PdpEntries + 1) * Pml4Entries + 1;
 257   ASSERT (TotalPages <= 0x40201);
 258
 259   //
 260   // Add 64 MB for miscellaneous allocations. Note that for
 261   // mPhysMemAddressWidth values close to 36, the cap will actually be
 262   // dominated by this increment.
 263   //
 264   return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB);
 265 }
 266
 267 /**
 268   Publish PEI core memory
 269
 270   @return EFI_SUCCESS     The PEIM initialized successfully.
 271
 272 **/
 273 EFI_STATUS
 274 PublishPeiMemory (
 275   VOID
 276   )
 277 {
 278   EFI_STATUS            Status;
 279   EFI_PHYSICAL_ADDRESS  MemoryBase;
 280   UINT64                MemorySize;
 281   UINT32                LowerMemorySize;
 282   UINT32                PeiMemoryCap;
 283
 284   LowerMemorySize = GetSystemMemorySizeBelow4gb ();
 285
 286   if (mBootMode == BOOT_ON_S3_RESUME) {
 287     MemoryBase = mS3AcpiReservedMemoryBase;
 288     MemorySize = mS3AcpiReservedMemorySize;
 289   } else {
 290     PeiMemoryCap = GetPeiMemoryCap ();
 291     DEBUG ((
 292       DEBUG_INFO,
 293       "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",
 294       __FUNCTION__,
 295       mPhysMemAddressWidth,
 296       PeiMemoryCap >> 10
 297       ));
 298
 299     //
 300     // Determine the range of memory to use during PEI
 301     //
 302     MemoryBase =
 303       PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);
 304     MemorySize = LowerMemorySize - MemoryBase;
 305     if (MemorySize > PeiMemoryCap) {
 306       MemoryBase = LowerMemorySize - PeiMemoryCap;
 307       MemorySize = PeiMemoryCap;
 308     }
 309   }
 310
 311   //
 312   // Publish this memory to the PEI Core
 313   //
 314   Status = PublishSystemMemory (MemoryBase, MemorySize);
 315   ASSERT_EFI_ERROR (Status);
 316
 317   return Status;
 318 }
 319
 320 /**
 321   Publish system RAM and reserve memory regions
 322
 323 **/
 324 VOID
 325 InitializeRamRegions (
 326   VOID
 327   )
 328 {
 329   XenPublishRamRegions ();
 330
 331   if (mBootMode != BOOT_ON_S3_RESUME) {
 332     //
 333     // Reserve the lock box storage area
 334     //
 335     // Since this memory range will be used on S3 resume, it must be
 336     // reserved as ACPI NVS.
 337     //
 338     // If S3 is unsupported, then various drivers might still write to the
 339     // LockBox area. We ought to prevent DXE from serving allocation requests
 340     // such that they would overlap the LockBox storage.
 341     //
 342     ZeroMem (
 343       (VOID *)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase),
 344       (UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize)
 345       );
 346     BuildMemoryAllocationHob (
 347       (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase),
 348       (UINT64)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize),
 349       EfiBootServicesData
 350       );
 351   }
 352 }