OvmfPkg/XenPlatformPei/Platform.c

   1 /**@file
   2   Platform PEI driver
   3
   4   Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
   5   Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
   6   Copyright (c) 2019, Citrix Systems, Inc.
   7
   8   SPDX-License-Identifier: BSD-2-Clause-Patent
   9
  10 **/
  11
  12 //
  13 // The package level header files this module uses
  14 //
  15 #include <PiPei.h>
  16
  17 //
  18 // The Library classes this module consumes
  19 //
  20 #include <Library/BaseLib.h>
  21 #include <Library/DebugLib.h>
  22 #include <Library/HobLib.h>
  23 #include <Library/IoLib.h>
  24 #include <Library/MemoryAllocationLib.h>
  25 #include <Library/PcdLib.h>
  26 #include <Library/PciLib.h>
  27 #include <Library/PeimEntryPoint.h>
  28 #include <Library/PeiServicesLib.h>
  29 #include <Library/ResourcePublicationLib.h>
  30 #include <Guid/MemoryTypeInformation.h>
  31 #include <Ppi/MasterBootMode.h>
  32 #include <IndustryStandard/Pci22.h>
  33 #include <OvmfPlatforms.h>
  34
  35 #include "Platform.h"
  36 #include "Cmos.h"
  37
  38 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
  39   { EfiACPIMemoryNVS,       0x004 },
  40   { EfiACPIReclaimMemory,   0x008 },
  41   { EfiReservedMemoryType,  0x004 },
  42   { EfiRuntimeServicesData, 0x024 },
  43   { EfiRuntimeServicesCode, 0x030 },
  44   { EfiBootServicesCode,    0x180 },
  45   { EfiBootServicesData,    0xF00 },
  46   { EfiMaxMemoryType,       0x000 }
  47 };
  48
  49
  50 EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {
  51   {
  52     EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  53     &gEfiPeiMasterBootModePpiGuid,
  54     NULL
  55   }
  56 };
  57
  58
  59 UINT16 mHostBridgeDevId;
  60
  61 EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
  62
  63
  64 VOID
  65 AddIoMemoryBaseSizeHob (
  66   EFI_PHYSICAL_ADDRESS        MemoryBase,
  67   UINT64                      MemorySize
  68   )
  69 {
  70   BuildResourceDescriptorHob (
  71     EFI_RESOURCE_MEMORY_MAPPED_IO,
  72       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  73       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  74       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  75       EFI_RESOURCE_ATTRIBUTE_TESTED,
  76     MemoryBase,
  77     MemorySize
  78     );
  79 }
  80
  81 VOID
  82 AddReservedMemoryBaseSizeHob (
  83   EFI_PHYSICAL_ADDRESS        MemoryBase,
  84   UINT64                      MemorySize,
  85   BOOLEAN                     Cacheable
  86   )
  87 {
  88   BuildResourceDescriptorHob (
  89     EFI_RESOURCE_MEMORY_RESERVED,
  90       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  91       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  92       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  93       (Cacheable ?
  94        EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
  95        EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
  96        EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
  97        0
  98        ) |
  99       EFI_RESOURCE_ATTRIBUTE_TESTED,
 100     MemoryBase,
 101     MemorySize
 102     );
 103 }
 104
 105 VOID
 106 AddIoMemoryRangeHob (
 107   EFI_PHYSICAL_ADDRESS        MemoryBase,
 108   EFI_PHYSICAL_ADDRESS        MemoryLimit
 109   )
 110 {
 111   AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 112 }
 113
 114
 115 VOID
 116 AddMemoryBaseSizeHob (
 117   EFI_PHYSICAL_ADDRESS        MemoryBase,
 118   UINT64                      MemorySize
 119   )
 120 {
 121   BuildResourceDescriptorHob (
 122     EFI_RESOURCE_SYSTEM_MEMORY,
 123       EFI_RESOURCE_ATTRIBUTE_PRESENT |
 124       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 125       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 126       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 127       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 128       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
 129       EFI_RESOURCE_ATTRIBUTE_TESTED,
 130     MemoryBase,
 131     MemorySize
 132     );
 133 }
 134
 135
 136 VOID
 137 AddMemoryRangeHob (
 138   EFI_PHYSICAL_ADDRESS        MemoryBase,
 139   EFI_PHYSICAL_ADDRESS        MemoryLimit
 140   )
 141 {
 142   AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 143 }
 144
 145
 146 VOID
 147 MemMapInitialization (
 148   VOID
 149   )
 150 {
 151   UINT64        PciIoBase;
 152   UINT64        PciIoSize;
 153   RETURN_STATUS PcdStatus;
 154
 155   PciIoBase = 0xC000;
 156   PciIoSize = 0x4000;
 157
 158   //
 159   // Create Memory Type Information HOB
 160   //
 161   BuildGuidDataHob (
 162     &gEfiMemoryTypeInformationGuid,
 163     mDefaultMemoryTypeInformation,
 164     sizeof(mDefaultMemoryTypeInformation)
 165     );
 166
 167   //
 168   // Video memory + Legacy BIOS region
 169   //
 170   AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
 171
 172   //
 173   // Add PCI IO Port space available for PCI resource allocations.
 174   //
 175   BuildResourceDescriptorHob (
 176     EFI_RESOURCE_IO,
 177     EFI_RESOURCE_ATTRIBUTE_PRESENT     |
 178     EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
 179     PciIoBase,
 180     PciIoSize
 181     );
 182   PcdStatus = PcdSet64S (PcdPciIoBase, PciIoBase);
 183   ASSERT_RETURN_ERROR (PcdStatus);
 184   PcdStatus = PcdSet64S (PcdPciIoSize, PciIoSize);
 185   ASSERT_RETURN_ERROR (PcdStatus);
 186 }
 187
 188 VOID
 189 PciExBarInitialization (
 190   VOID
 191   )
 192 {
 193   union {
 194     UINT64 Uint64;
 195     UINT32 Uint32[2];
 196   } PciExBarBase;
 197
 198   //
 199   // We only support the 256MB size for the MMCONFIG area:
 200   // 256 buses * 32 devices * 8 functions * 4096 bytes config space.
 201   //
 202   // The masks used below enforce the Q35 requirements that the MMCONFIG area
 203   // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.
 204   //
 205   // Note that (b) also ensures that the minimum address width we have
 206   // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice
 207   // for DXE's page tables to cover the MMCONFIG area.
 208   //
 209   PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);
 210   ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);
 211   ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);
 212
 213   //
 214   // Clear the PCIEXBAREN bit first, before programming the high register.
 215   //
 216   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);
 217
 218   //
 219   // Program the high register. Then program the low register, setting the
 220   // MMCONFIG area size and enabling decoding at once.
 221   //
 222   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);
 223   PciWrite32 (
 224     DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),
 225     PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN
 226     );
 227 }
 228
 229 VOID
 230 MiscInitialization (
 231   VOID
 232   )
 233 {
 234   UINTN         PmCmd;
 235   UINTN         Pmba;
 236   UINT32        PmbaAndVal;
 237   UINT32        PmbaOrVal;
 238   UINTN         AcpiCtlReg;
 239   UINT8         AcpiEnBit;
 240   RETURN_STATUS PcdStatus;
 241
 242   //
 243   // Disable A20 Mask
 244   //
 245   IoOr8 (0x92, BIT1);
 246
 247   //
 248   // Build the CPU HOB with guest RAM size dependent address width and 16-bits
 249   // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
 250   // S3 resume as well, so we build it unconditionally.)
 251   //
 252   BuildCpuHob (mPhysMemAddressWidth, 16);
 253
 254   //
 255   // Determine platform type and save Host Bridge DID to PCD
 256   //
 257   switch (mHostBridgeDevId) {
 258     case INTEL_82441_DEVICE_ID:
 259       PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
 260       Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
 261       PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;
 262       PmbaOrVal  = PIIX4_PMBA_VALUE;
 263       AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
 264       AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;
 265       break;
 266     case INTEL_Q35_MCH_DEVICE_ID:
 267       PmCmd      = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
 268       Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
 269       PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;
 270       PmbaOrVal  = ICH9_PMBASE_VALUE;
 271       AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
 272       AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;
 273       break;
 274     default:
 275       DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
 276         __FUNCTION__, mHostBridgeDevId));
 277       ASSERT (FALSE);
 278       return;
 279   }
 280   PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
 281   ASSERT_RETURN_ERROR (PcdStatus);
 282
 283   //
 284   // If the appropriate IOspace enable bit is set, assume the ACPI PMBA
 285   // has been configured (e.g., by Xen) and skip the setup here.
 286   // This matches the logic in AcpiTimerLibConstructor ().
 287   //
 288   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
 289     //
 290     // The PEI phase should be exited with fully accessibe ACPI PM IO space:
 291     // 1. set PMBA
 292     //
 293     PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);
 294
 295     //
 296     // 2. set PCICMD/IOSE
 297     //
 298     PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
 299
 300     //
 301     // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
 302     //
 303     PciOr8 (AcpiCtlReg, AcpiEnBit);
 304   }
 305
 306   if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 307     //
 308     // Set Root Complex Register Block BAR
 309     //
 310     PciWrite32 (
 311       POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),
 312       ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN
 313       );
 314
 315     //
 316     // Set PCI Express Register Range Base Address
 317     //
 318     PciExBarInitialization ();
 319   }
 320 }
 321
 322
 323 VOID
 324 BootModeInitialization (
 325   VOID
 326   )
 327 {
 328   EFI_STATUS    Status;
 329
 330   if (CmosRead8 (0xF) == 0xFE) {
 331     mBootMode = BOOT_ON_S3_RESUME;
 332   }
 333   CmosWrite8 (0xF, 0x00);
 334
 335   Status = PeiServicesSetBootMode (mBootMode);
 336   ASSERT_EFI_ERROR (Status);
 337
 338   Status = PeiServicesInstallPpi (mPpiBootMode);
 339   ASSERT_EFI_ERROR (Status);
 340 }
 341
 342
 343 VOID
 344 ReserveEmuVariableNvStore (
 345   )
 346 {
 347   EFI_PHYSICAL_ADDRESS VariableStore;
 348   RETURN_STATUS        PcdStatus;
 349
 350   //
 351   // Allocate storage for NV variables early on so it will be
 352   // at a consistent address.  Since VM memory is preserved
 353   // across reboots, this allows the NV variable storage to survive
 354   // a VM reboot.
 355   //
 356   VariableStore =
 357     (EFI_PHYSICAL_ADDRESS)(UINTN)
 358       AllocateRuntimePages (
 359         EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))
 360         );
 361   DEBUG ((DEBUG_INFO,
 362           "Reserved variable store memory: 0x%lX; size: %dkb\n",
 363           VariableStore,
 364           (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
 365         ));
 366   PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);
 367   ASSERT_RETURN_ERROR (PcdStatus);
 368 }
 369
 370
 371 VOID
 372 DebugDumpCmos (
 373   VOID
 374   )
 375 {
 376   UINT32 Loop;
 377
 378   DEBUG ((DEBUG_INFO, "CMOS:\n"));
 379
 380   for (Loop = 0; Loop < 0x80; Loop++) {
 381     if ((Loop % 0x10) == 0) {
 382       DEBUG ((DEBUG_INFO, "%02x:", Loop));
 383     }
 384     DEBUG ((DEBUG_INFO, " %02x", CmosRead8 (Loop)));
 385     if ((Loop % 0x10) == 0xf) {
 386       DEBUG ((DEBUG_INFO, "\n"));
 387     }
 388   }
 389 }
 390
 391
 392
 393 /**
 394   Perform Platform PEI initialization.
 395
 396   @param  FileHandle      Handle of the file being invoked.
 397   @param  PeiServices     Describes the list of possible PEI Services.
 398
 399   @return EFI_SUCCESS     The PEIM initialized successfully.
 400
 401 **/
 402 EFI_STATUS
 403 EFIAPI
 404 InitializeXenPlatform (
 405   IN       EFI_PEI_FILE_HANDLE  FileHandle,
 406   IN CONST EFI_PEI_SERVICES     **PeiServices
 407   )
 408 {
 409   DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));
 410
 411   DebugDumpCmos ();
 412
 413   if (!XenDetect ()) {
 414     DEBUG ((DEBUG_ERROR, "ERROR: Xen isn't detected\n"));
 415     ASSERT (FALSE);
 416     CpuDeadLoop ();
 417   }
 418
 419   XenConnect ();
 420
 421   BootModeInitialization ();
 422   AddressWidthInitialization ();
 423
 424   //
 425   // Query Host Bridge DID
 426   //
 427   mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
 428
 429   PublishPeiMemory ();
 430
 431   InitializeRamRegions ();
 432
 433   InitializeXen ();
 434
 435   if (mBootMode != BOOT_ON_S3_RESUME) {
 436     ReserveEmuVariableNvStore ();
 437     PeiFvInitialization ();
 438     MemMapInitialization ();
 439   }
 440
 441   InstallClearCacheCallback ();
 442   AmdSevInitialize ();
 443   MiscInitialization ();
 444
 445   return EFI_SUCCESS;
 446 }