OvmfPkg/XenPlatformPei/Platform.c

   1 /**@file
   2   Platform PEI driver
   3
   4   Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
   5   Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
   6   Copyright (c) 2019, Citrix Systems, Inc.
   7
   8   SPDX-License-Identifier: BSD-2-Clause-Patent
   9
  10 **/
  11
  12 //
  13 // The package level header files this module uses
  14 //
  15 #include <PiPei.h>
  16
  17 //
  18 // The Library classes this module consumes
  19 //
  20 #include <Library/BaseLib.h>
  21 #include <Library/DebugLib.h>
  22 #include <Library/HobLib.h>
  23 #include <Library/IoLib.h>
  24 #include <Library/MemoryAllocationLib.h>
  25 #include <Library/PcdLib.h>
  26 #include <Library/PciLib.h>
  27 #include <Library/PeimEntryPoint.h>
  28 #include <Library/PeiServicesLib.h>
  29 #include <Library/ResourcePublicationLib.h>
  30 #include <Guid/MemoryTypeInformation.h>
  31 #include <Ppi/MasterBootMode.h>
  32 #include <IndustryStandard/Pci22.h>
  33 #include <OvmfPlatforms.h>
  34
  35 #include "Platform.h"
  36 #include "Cmos.h"
  37
  38 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
  39   { EfiACPIMemoryNVS,       0x004 },
  40   { EfiACPIReclaimMemory,   0x008 },
  41   { EfiReservedMemoryType,  0x004 },
  42   { EfiRuntimeServicesData, 0x024 },
  43   { EfiRuntimeServicesCode, 0x030 },
  44   { EfiBootServicesCode,    0x180 },
  45   { EfiBootServicesData,    0xF00 },
  46   { EfiMaxMemoryType,       0x000 }
  47 };
  48
  49
  50 EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {
  51   {
  52     EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  53     &gEfiPeiMasterBootModePpiGuid,
  54     NULL
  55   }
  56 };
  57
  58
  59 UINT16 mHostBridgeDevId;
  60
  61 EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
  62
  63
  64 VOID
  65 AddIoMemoryBaseSizeHob (
  66   EFI_PHYSICAL_ADDRESS        MemoryBase,
  67   UINT64                      MemorySize
  68   )
  69 {
  70   BuildResourceDescriptorHob (
  71     EFI_RESOURCE_MEMORY_MAPPED_IO,
  72       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  73       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  74       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  75       EFI_RESOURCE_ATTRIBUTE_TESTED,
  76     MemoryBase,
  77     MemorySize
  78     );
  79 }
  80
  81 VOID
  82 AddReservedMemoryBaseSizeHob (
  83   EFI_PHYSICAL_ADDRESS        MemoryBase,
  84   UINT64                      MemorySize,
  85   BOOLEAN                     Cacheable
  86   )
  87 {
  88   BuildResourceDescriptorHob (
  89     EFI_RESOURCE_MEMORY_RESERVED,
  90       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  91       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  92       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  93       (Cacheable ?
  94        EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
  95        EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
  96        EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
  97        0
  98        ) |
  99       EFI_RESOURCE_ATTRIBUTE_TESTED,
 100     MemoryBase,
 101     MemorySize
 102     );
 103 }
 104
 105 VOID
 106 AddReservedMemoryRangeHob (
 107   EFI_PHYSICAL_ADDRESS        MemoryBase,
 108   EFI_PHYSICAL_ADDRESS        MemoryLimit,
 109   BOOLEAN                     Cacheable
 110   )
 111 {
 112   AddReservedMemoryBaseSizeHob (MemoryBase,
 113     (UINT64)(MemoryLimit - MemoryBase), Cacheable);
 114 }
 115
 116 VOID
 117 AddIoMemoryRangeHob (
 118   EFI_PHYSICAL_ADDRESS        MemoryBase,
 119   EFI_PHYSICAL_ADDRESS        MemoryLimit
 120   )
 121 {
 122   AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 123 }
 124
 125
 126 VOID
 127 AddMemoryBaseSizeHob (
 128   EFI_PHYSICAL_ADDRESS        MemoryBase,
 129   UINT64                      MemorySize
 130   )
 131 {
 132   BuildResourceDescriptorHob (
 133     EFI_RESOURCE_SYSTEM_MEMORY,
 134       EFI_RESOURCE_ATTRIBUTE_PRESENT |
 135       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 136       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 137       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 138       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 139       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
 140       EFI_RESOURCE_ATTRIBUTE_TESTED,
 141     MemoryBase,
 142     MemorySize
 143     );
 144 }
 145
 146
 147 VOID
 148 AddMemoryRangeHob (
 149   EFI_PHYSICAL_ADDRESS        MemoryBase,
 150   EFI_PHYSICAL_ADDRESS        MemoryLimit
 151   )
 152 {
 153   AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 154 }
 155
 156
 157 VOID
 158 MemMapInitialization (
 159   VOID
 160   )
 161 {
 162   UINT64        PciIoBase;
 163   UINT64        PciIoSize;
 164   RETURN_STATUS PcdStatus;
 165
 166   PciIoBase = 0xC000;
 167   PciIoSize = 0x4000;
 168
 169   //
 170   // Create Memory Type Information HOB
 171   //
 172   BuildGuidDataHob (
 173     &gEfiMemoryTypeInformationGuid,
 174     mDefaultMemoryTypeInformation,
 175     sizeof(mDefaultMemoryTypeInformation)
 176     );
 177
 178   //
 179   // Video memory + Legacy BIOS region
 180   //
 181   AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
 182
 183   //
 184   // Add PCI IO Port space available for PCI resource allocations.
 185   //
 186   BuildResourceDescriptorHob (
 187     EFI_RESOURCE_IO,
 188     EFI_RESOURCE_ATTRIBUTE_PRESENT     |
 189     EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
 190     PciIoBase,
 191     PciIoSize
 192     );
 193   PcdStatus = PcdSet64S (PcdPciIoBase, PciIoBase);
 194   ASSERT_RETURN_ERROR (PcdStatus);
 195   PcdStatus = PcdSet64S (PcdPciIoSize, PciIoSize);
 196   ASSERT_RETURN_ERROR (PcdStatus);
 197 }
 198
 199 VOID
 200 PciExBarInitialization (
 201   VOID
 202   )
 203 {
 204   union {
 205     UINT64 Uint64;
 206     UINT32 Uint32[2];
 207   } PciExBarBase;
 208
 209   //
 210   // We only support the 256MB size for the MMCONFIG area:
 211   // 256 buses * 32 devices * 8 functions * 4096 bytes config space.
 212   //
 213   // The masks used below enforce the Q35 requirements that the MMCONFIG area
 214   // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.
 215   //
 216   // Note that (b) also ensures that the minimum address width we have
 217   // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice
 218   // for DXE's page tables to cover the MMCONFIG area.
 219   //
 220   PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);
 221   ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);
 222   ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);
 223
 224   //
 225   // Clear the PCIEXBAREN bit first, before programming the high register.
 226   //
 227   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);
 228
 229   //
 230   // Program the high register. Then program the low register, setting the
 231   // MMCONFIG area size and enabling decoding at once.
 232   //
 233   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);
 234   PciWrite32 (
 235     DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),
 236     PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN
 237     );
 238 }
 239
 240 VOID
 241 MiscInitialization (
 242   VOID
 243   )
 244 {
 245   UINTN         PmCmd;
 246   UINTN         Pmba;
 247   UINT32        PmbaAndVal;
 248   UINT32        PmbaOrVal;
 249   UINTN         AcpiCtlReg;
 250   UINT8         AcpiEnBit;
 251   RETURN_STATUS PcdStatus;
 252
 253   //
 254   // Disable A20 Mask
 255   //
 256   IoOr8 (0x92, BIT1);
 257
 258   //
 259   // Build the CPU HOB with guest RAM size dependent address width and 16-bits
 260   // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
 261   // S3 resume as well, so we build it unconditionally.)
 262   //
 263   BuildCpuHob (mPhysMemAddressWidth, 16);
 264
 265   //
 266   // Determine platform type and save Host Bridge DID to PCD
 267   //
 268   switch (mHostBridgeDevId) {
 269     case INTEL_82441_DEVICE_ID:
 270       PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
 271       Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
 272       PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;
 273       PmbaOrVal  = PIIX4_PMBA_VALUE;
 274       AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
 275       AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;
 276       break;
 277     case INTEL_Q35_MCH_DEVICE_ID:
 278       PmCmd      = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
 279       Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
 280       PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;
 281       PmbaOrVal  = ICH9_PMBASE_VALUE;
 282       AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
 283       AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;
 284       break;
 285     default:
 286       if (XenPvhDetected ()) {
 287         //
 288         // There is no PCI bus in this case
 289         //
 290         return;
 291       }
 292       DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
 293         __FUNCTION__, mHostBridgeDevId));
 294       ASSERT (FALSE);
 295       return;
 296   }
 297   PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
 298   ASSERT_RETURN_ERROR (PcdStatus);
 299
 300   //
 301   // If the appropriate IOspace enable bit is set, assume the ACPI PMBA
 302   // has been configured (e.g., by Xen) and skip the setup here.
 303   // This matches the logic in AcpiTimerLibConstructor ().
 304   //
 305   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
 306     //
 307     // The PEI phase should be exited with fully accessibe ACPI PM IO space:
 308     // 1. set PMBA
 309     //
 310     PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);
 311
 312     //
 313     // 2. set PCICMD/IOSE
 314     //
 315     PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
 316
 317     //
 318     // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
 319     //
 320     PciOr8 (AcpiCtlReg, AcpiEnBit);
 321   }
 322
 323   if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 324     //
 325     // Set Root Complex Register Block BAR
 326     //
 327     PciWrite32 (
 328       POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),
 329       ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN
 330       );
 331
 332     //
 333     // Set PCI Express Register Range Base Address
 334     //
 335     PciExBarInitialization ();
 336   }
 337 }
 338
 339
 340 VOID
 341 BootModeInitialization (
 342   VOID
 343   )
 344 {
 345   EFI_STATUS    Status;
 346
 347   if (CmosRead8 (0xF) == 0xFE) {
 348     mBootMode = BOOT_ON_S3_RESUME;
 349   }
 350   CmosWrite8 (0xF, 0x00);
 351
 352   Status = PeiServicesSetBootMode (mBootMode);
 353   ASSERT_EFI_ERROR (Status);
 354
 355   Status = PeiServicesInstallPpi (mPpiBootMode);
 356   ASSERT_EFI_ERROR (Status);
 357 }
 358
 359
 360 VOID
 361 ReserveEmuVariableNvStore (
 362   )
 363 {
 364   EFI_PHYSICAL_ADDRESS VariableStore;
 365   RETURN_STATUS        PcdStatus;
 366
 367   //
 368   // Allocate storage for NV variables early on so it will be
 369   // at a consistent address.  Since VM memory is preserved
 370   // across reboots, this allows the NV variable storage to survive
 371   // a VM reboot.
 372   //
 373   VariableStore =
 374     (EFI_PHYSICAL_ADDRESS)(UINTN)
 375       AllocateRuntimePages (
 376         EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))
 377         );
 378   DEBUG ((DEBUG_INFO,
 379           "Reserved variable store memory: 0x%lX; size: %dkb\n",
 380           VariableStore,
 381           (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
 382         ));
 383   PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);
 384   ASSERT_RETURN_ERROR (PcdStatus);
 385 }
 386
 387
 388 VOID
 389 DebugDumpCmos (
 390   VOID
 391   )
 392 {
 393   UINT32 Loop;
 394
 395   DEBUG ((DEBUG_INFO, "CMOS:\n"));
 396
 397   for (Loop = 0; Loop < 0x80; Loop++) {
 398     if ((Loop % 0x10) == 0) {
 399       DEBUG ((DEBUG_INFO, "%02x:", Loop));
 400     }
 401     DEBUG ((DEBUG_INFO, " %02x", CmosRead8 (Loop)));
 402     if ((Loop % 0x10) == 0xf) {
 403       DEBUG ((DEBUG_INFO, "\n"));
 404     }
 405   }
 406 }
 407
 408
 409
 410 /**
 411   Perform Platform PEI initialization.
 412
 413   @param  FileHandle      Handle of the file being invoked.
 414   @param  PeiServices     Describes the list of possible PEI Services.
 415
 416   @return EFI_SUCCESS     The PEIM initialized successfully.
 417
 418 **/
 419 EFI_STATUS
 420 EFIAPI
 421 InitializeXenPlatform (
 422   IN       EFI_PEI_FILE_HANDLE  FileHandle,
 423   IN CONST EFI_PEI_SERVICES     **PeiServices
 424   )
 425 {
 426   DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));
 427
 428   DebugDumpCmos ();
 429
 430   if (!XenDetect ()) {
 431     DEBUG ((DEBUG_ERROR, "ERROR: Xen isn't detected\n"));
 432     ASSERT (FALSE);
 433     CpuDeadLoop ();
 434   }
 435
 436   XenConnect ();
 437
 438   BootModeInitialization ();
 439   AddressWidthInitialization ();
 440
 441   //
 442   // Query Host Bridge DID
 443   //
 444   mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
 445
 446   PublishPeiMemory ();
 447
 448   InitializeRamRegions ();
 449
 450   InitializeXen ();
 451
 452   if (mBootMode != BOOT_ON_S3_RESUME) {
 453     ReserveEmuVariableNvStore ();
 454     PeiFvInitialization ();
 455     MemMapInitialization ();
 456   }
 457
 458   InstallClearCacheCallback ();
 459   AmdSevInitialize ();
 460   MiscInitialization ();
 461
 462   return EFI_SUCCESS;
 463 }