2 PCI Root Bridge Io Protocol implementation
4 Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials are
6 licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include "PciHostBridge.h"
18 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR SpaceDesp
[TypeMax
];
19 EFI_ACPI_END_TAG_DESCRIPTOR EndDesp
;
20 } RESOURCE_CONFIGURATION
;
22 RESOURCE_CONFIGURATION Configuration
= {
23 {{0x8A, 0x2B, 1, 0, 0, 0, 0, 0, 0, 0},
24 {0x8A, 0x2B, 0, 0, 0, 32, 0, 0, 0, 0},
25 {0x8A, 0x2B, 0, 0, 6, 32, 0, 0, 0, 0},
26 {0x8A, 0x2B, 0, 0, 0, 64, 0, 0, 0, 0},
27 {0x8A, 0x2B, 0, 0, 6, 64, 0, 0, 0, 0},
28 {0x8A, 0x2B, 2, 0, 0, 0, 0, 0, 0, 0}},
33 // Protocol Member Function Prototypes
37 Polls an address in memory mapped I/O space until an exit condition is met, or
40 This function provides a standard way to poll a PCI memory location. A PCI memory read
41 operation is performed at the PCI memory address specified by Address for the width specified
42 by Width. The result of this PCI memory read operation is stored in Result. This PCI memory
43 read operation is repeated until either a timeout of Delay 100 ns units has expired, or (Result &
44 Mask) is equal to Value.
46 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
47 @param[in] Width Signifies the width of the memory operations.
48 @param[in] Address The base address of the memory operations. The caller is
49 responsible for aligning Address if required.
50 @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask
51 are ignored. The bits in the bytes below Width which are zero in
52 Mask are ignored when polling the memory address.
53 @param[in] Value The comparison value used for the polling exit criteria.
54 @param[in] Delay The number of 100 ns units to poll. Note that timer available may
55 be of poorer granularity.
56 @param[out] Result Pointer to the last value read from the memory location.
58 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
59 @retval EFI_INVALID_PARAMETER Width is invalid.
60 @retval EFI_INVALID_PARAMETER Result is NULL.
61 @retval EFI_TIMEOUT Delay expired before a match occurred.
62 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
68 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
69 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
78 Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is
79 satisfied or after a defined duration.
81 This function provides a standard way to poll a PCI I/O location. A PCI I/O read operation is
82 performed at the PCI I/O address specified by Address for the width specified by Width.
83 The result of this PCI I/O read operation is stored in Result. This PCI I/O read operation is
84 repeated until either a timeout of Delay 100 ns units has expired, or (Result & Mask) is equal
87 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
88 @param[in] Width Signifies the width of the I/O operations.
89 @param[in] Address The base address of the I/O operations. The caller is responsible
90 for aligning Address if required.
91 @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask
92 are ignored. The bits in the bytes below Width which are zero in
93 Mask are ignored when polling the I/O address.
94 @param[in] Value The comparison value used for the polling exit criteria.
95 @param[in] Delay The number of 100 ns units to poll. Note that timer available may
96 be of poorer granularity.
97 @param[out] Result Pointer to the last value read from the memory location.
99 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
100 @retval EFI_INVALID_PARAMETER Width is invalid.
101 @retval EFI_INVALID_PARAMETER Result is NULL.
102 @retval EFI_TIMEOUT Delay expired before a match occurred.
103 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
109 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
110 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
119 Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
121 The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller
122 registers in the PCI root bridge memory space.
123 The memory operations are carried out exactly as requested. The caller is responsible for satisfying
124 any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.
126 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
127 @param[in] Width Signifies the width of the memory operation.
128 @param[in] Address The base address of the memory operation. The caller is
129 responsible for aligning the Address if required.
130 @param[in] Count The number of memory operations to perform. Bytes moved is
131 Width size * Count, starting at Address.
132 @param[out] Buffer For read operations, the destination buffer to store the results. For
133 write operations, the source buffer to write data from.
135 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
136 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
137 @retval EFI_INVALID_PARAMETER Buffer is NULL.
138 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
143 RootBridgeIoMemRead (
144 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
145 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
152 Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
154 The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller
155 registers in the PCI root bridge memory space.
156 The memory operations are carried out exactly as requested. The caller is responsible for satisfying
157 any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.
159 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
160 @param[in] Width Signifies the width of the memory operation.
161 @param[in] Address The base address of the memory operation. The caller is
162 responsible for aligning the Address if required.
163 @param[in] Count The number of memory operations to perform. Bytes moved is
164 Width size * Count, starting at Address.
165 @param[out] Buffer For read operations, the destination buffer to store the results. For
166 write operations, the source buffer to write data from.
168 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
169 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
170 @retval EFI_INVALID_PARAMETER Buffer is NULL.
171 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
175 RootBridgeIoMemWrite (
176 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
177 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
184 Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
186 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
187 @param[in] Width Signifies the width of the memory operations.
188 @param[in] Address The base address of the I/O operation. The caller is responsible for
189 aligning the Address if required.
190 @param[in] Count The number of I/O operations to perform. Bytes moved is Width
191 size * Count, starting at Address.
192 @param[out] Buffer For read operations, the destination buffer to store the results. For
193 write operations, the source buffer to write data from.
195 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
196 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
197 @retval EFI_INVALID_PARAMETER Buffer is NULL.
198 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
204 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
205 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
206 IN UINT64 UserAddress
,
208 IN OUT VOID
*UserBuffer
212 Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
214 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
215 @param[in] Width Signifies the width of the memory operations.
216 @param[in] Address The base address of the I/O operation. The caller is responsible for
217 aligning the Address if required.
218 @param[in] Count The number of I/O operations to perform. Bytes moved is Width
219 size * Count, starting at Address.
220 @param[out] Buffer For read operations, the destination buffer to store the results. For
221 write operations, the source buffer to write data from.
223 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
224 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
225 @retval EFI_INVALID_PARAMETER Buffer is NULL.
226 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
231 RootBridgeIoIoWrite (
232 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
233 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
234 IN UINT64 UserAddress
,
236 IN OUT VOID
*UserBuffer
240 Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI
241 root bridge memory space.
243 The CopyMem() function enables a PCI driver to copy one region of PCI root bridge memory
244 space to another region of PCI root bridge memory space. This is especially useful for video scroll
245 operation on a memory mapped video buffer.
246 The memory operations are carried out exactly as requested. The caller is responsible for satisfying
247 any alignment and memory width restrictions that a PCI root bridge on a platform might require.
249 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.
250 @param[in] Width Signifies the width of the memory operations.
251 @param[in] DestAddress The destination address of the memory operation. The caller is
252 responsible for aligning the DestAddress if required.
253 @param[in] SrcAddress The source address of the memory operation. The caller is
254 responsible for aligning the SrcAddress if required.
255 @param[in] Count The number of memory operations to perform. Bytes moved is
256 Width size * Count, starting at DestAddress and SrcAddress.
258 @retval EFI_SUCCESS The data was copied from one memory region to another memory region.
259 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
260 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
265 RootBridgeIoCopyMem (
266 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
267 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
268 IN UINT64 DestAddress
,
269 IN UINT64 SrcAddress
,
274 Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.
276 The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration
277 registers for a PCI controller.
278 The PCI Configuration operations are carried out exactly as requested. The caller is responsible for
279 any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might
282 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
283 @param[in] Width Signifies the width of the memory operations.
284 @param[in] Address The address within the PCI configuration space for the PCI controller.
285 @param[in] Count The number of PCI configuration operations to perform. Bytes
286 moved is Width size * Count, starting at Address.
287 @param[out] Buffer For read operations, the destination buffer to store the results. For
288 write operations, the source buffer to write data from.
290 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
291 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
292 @retval EFI_INVALID_PARAMETER Buffer is NULL.
293 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
298 RootBridgeIoPciRead (
299 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
300 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
307 Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.
309 The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration
310 registers for a PCI controller.
311 The PCI Configuration operations are carried out exactly as requested. The caller is responsible for
312 any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might
315 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
316 @param[in] Width Signifies the width of the memory operations.
317 @param[in] Address The address within the PCI configuration space for the PCI controller.
318 @param[in] Count The number of PCI configuration operations to perform. Bytes
319 moved is Width size * Count, starting at Address.
320 @param[out] Buffer For read operations, the destination buffer to store the results. For
321 write operations, the source buffer to write data from.
323 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
324 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
325 @retval EFI_INVALID_PARAMETER Buffer is NULL.
326 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
331 RootBridgeIoPciWrite (
332 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
333 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
340 Provides the PCI controller-specific addresses required to access system memory from a
343 The Map() function provides the PCI controller specific addresses needed to access system
344 memory. This function is used to map system memory for PCI bus master DMA accesses.
346 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
347 @param[in] Operation Indicates if the bus master is going to read or write to system memory.
348 @param[in] HostAddress The system memory address to map to the PCI controller.
349 @param[in][out] NumberOfBytes On input the number of bytes to map. On output the number of bytes that were mapped.
350 @param[out] DeviceAddress The resulting map address for the bus master PCI controller to use
351 to access the system memory's HostAddress.
352 @param[out] Mapping The value to pass to Unmap() when the bus master DMA operation is complete.
354 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
355 @retval EFI_INVALID_PARAMETER Operation is invalid.
356 @retval EFI_INVALID_PARAMETER HostAddress is NULL.
357 @retval EFI_INVALID_PARAMETER NumberOfBytes is NULL.
358 @retval EFI_INVALID_PARAMETER DeviceAddress is NULL.
359 @retval EFI_INVALID_PARAMETER Mapping is NULL.
360 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
361 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
362 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
368 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
369 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation
,
370 IN VOID
*HostAddress
,
371 IN OUT UINTN
*NumberOfBytes
,
372 OUT EFI_PHYSICAL_ADDRESS
*DeviceAddress
,
377 Completes the Map() operation and releases any corresponding resources.
379 The Unmap() function completes the Map() operation and releases any corresponding resources.
380 If the operation was an EfiPciOperationBusMasterWrite or
381 EfiPciOperationBusMasterWrite64, the data is committed to the target system memory.
382 Any resources used for the mapping are freed.
384 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
385 @param[in] Mapping The mapping value returned from Map().
387 @retval EFI_SUCCESS The range was unmapped.
388 @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().
389 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
395 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
400 Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or
401 EfiPciOperationBusMasterCommonBuffer64 mapping.
403 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
404 @param Type This parameter is not used and must be ignored.
405 @param MemoryType The type of memory to allocate, EfiBootServicesData or EfiRuntimeServicesData.
406 @param Pages The number of pages to allocate.
407 @param HostAddress A pointer to store the base system memory address of the allocated range.
408 @param Attributes The requested bit mask of attributes for the allocated range. Only
409 the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, EFI_PCI_ATTRIBUTE_MEMORY_CACHED,
410 and EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this function.
412 @retval EFI_SUCCESS The requested memory pages were allocated.
413 @retval EFI_INVALID_PARAMETER MemoryType is invalid.
414 @retval EFI_INVALID_PARAMETER HostAddress is NULL.
415 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
416 MEMORY_WRITE_COMBINE, MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.
417 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
422 RootBridgeIoAllocateBuffer (
423 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
424 IN EFI_ALLOCATE_TYPE Type
,
425 IN EFI_MEMORY_TYPE MemoryType
,
427 OUT VOID
**HostAddress
,
432 Frees memory that was allocated with AllocateBuffer().
434 The FreeBuffer() function frees memory that was allocated with AllocateBuffer().
436 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
437 @param Pages The number of pages to free.
438 @param HostAddress The base system memory address of the allocated range.
440 @retval EFI_SUCCESS The requested memory pages were freed.
441 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
442 was not allocated with AllocateBuffer().
447 RootBridgeIoFreeBuffer (
448 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
450 OUT VOID
*HostAddress
454 Flushes all PCI posted write transactions from a PCI host bridge to system memory.
456 The Flush() function flushes any PCI posted write transactions from a PCI host bridge to system
457 memory. Posted write transactions are generated by PCI bus masters when they perform write
458 transactions to target addresses in system memory.
459 This function does not flush posted write transactions from any PCI bridges. A PCI controller
460 specific action must be taken to guarantee that the posted write transactions have been flushed from
461 the PCI controller and from all the PCI bridges into the PCI host bridge. This is typically done with
462 a PCI read transaction from the PCI controller prior to calling Flush().
464 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
466 @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host
467 bridge to system memory.
468 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI
469 host bridge due to a hardware error.
475 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
479 Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the
480 attributes that a PCI root bridge is currently using.
482 The GetAttributes() function returns the mask of attributes that this PCI root bridge supports
483 and the mask of attributes that the PCI root bridge is currently using.
485 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
486 @param Supported A pointer to the mask of attributes that this PCI root bridge
487 supports setting with SetAttributes().
488 @param Attributes A pointer to the mask of attributes that this PCI root bridge is
491 @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI root
492 bridge supports is returned in Supports. If Attributes is
493 not NULL, then the attributes that the PCI root bridge is currently
494 using is returned in Attributes.
495 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
500 RootBridgeIoGetAttributes (
501 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
502 OUT UINT64
*Supported
,
503 OUT UINT64
*Attributes
507 Sets attributes for a resource range on a PCI root bridge.
509 The SetAttributes() function sets the attributes specified in Attributes for the PCI root
510 bridge on the resource range specified by ResourceBase and ResourceLength. Since the
511 granularity of setting these attributes may vary from resource type to resource type, and from
512 platform to platform, the actual resource range and the one passed in by the caller may differ. As a
513 result, this function may set the attributes specified by Attributes on a larger resource range
514 than the caller requested. The actual range is returned in ResourceBase and
515 ResourceLength. The caller is responsible for verifying that the actual range for which the
516 attributes were set is acceptable.
518 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
519 @param[in] Attributes The mask of attributes to set. If the attribute bit
520 MEMORY_WRITE_COMBINE, MEMORY_CACHED, or
521 MEMORY_DISABLE is set, then the resource range is specified by
522 ResourceBase and ResourceLength. If
523 MEMORY_WRITE_COMBINE, MEMORY_CACHED, and
524 MEMORY_DISABLE are not set, then ResourceBase and
525 ResourceLength are ignored, and may be NULL.
526 @param[in][out] ResourceBase A pointer to the base address of the resource range to be modified
527 by the attributes specified by Attributes.
528 @param[in][out] ResourceLength A pointer to the length of the resource range to be modified by the
529 attributes specified by Attributes.
531 @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.
532 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.
533 @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
538 RootBridgeIoSetAttributes (
539 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
540 IN UINT64 Attributes
,
541 IN OUT UINT64
*ResourceBase
,
542 IN OUT UINT64
*ResourceLength
546 Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI 2.0
547 resource descriptors.
549 There are only two resource descriptor types from the ACPI Specification that may be used to
550 describe the current resources allocated to a PCI root bridge. These are the QWORD Address
551 Space Descriptor (ACPI 2.0 Section 6.4.3.5.1), and the End Tag (ACPI 2.0 Section 6.4.2.8). The
552 QWORD Address Space Descriptor can describe memory, I/O, and bus number ranges for dynamic
553 or fixed resources. The configuration of a PCI root bridge is described with one or more QWORD
554 Address Space Descriptors followed by an End Tag.
556 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
557 @param[out] Resources A pointer to the ACPI 2.0 resource descriptors that describe the
558 current configuration of this PCI root bridge. The storage for the
559 ACPI 2.0 resource descriptors is allocated by this function. The
560 caller must treat the return buffer as read-only data, and the buffer
561 must not be freed by the caller.
563 @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.
564 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.
565 @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
570 RootBridgeIoConfiguration (
571 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
576 // Memory Controller Pci Root Bridge Io Module Variables
578 EFI_METRONOME_ARCH_PROTOCOL
*mMetronome
;
581 // Lookup table for increment values based on transfer widths
583 UINT8 mInStride
[] = {
584 1, // EfiPciWidthUint8
585 2, // EfiPciWidthUint16
586 4, // EfiPciWidthUint32
587 8, // EfiPciWidthUint64
588 0, // EfiPciWidthFifoUint8
589 0, // EfiPciWidthFifoUint16
590 0, // EfiPciWidthFifoUint32
591 0, // EfiPciWidthFifoUint64
592 1, // EfiPciWidthFillUint8
593 2, // EfiPciWidthFillUint16
594 4, // EfiPciWidthFillUint32
595 8 // EfiPciWidthFillUint64
599 // Lookup table for increment values based on transfer widths
601 UINT8 mOutStride
[] = {
602 1, // EfiPciWidthUint8
603 2, // EfiPciWidthUint16
604 4, // EfiPciWidthUint32
605 8, // EfiPciWidthUint64
606 1, // EfiPciWidthFifoUint8
607 2, // EfiPciWidthFifoUint16
608 4, // EfiPciWidthFifoUint32
609 8, // EfiPciWidthFifoUint64
610 0, // EfiPciWidthFillUint8
611 0, // EfiPciWidthFillUint16
612 0, // EfiPciWidthFillUint32
613 0 // EfiPciWidthFillUint64
618 Construct the Pci Root Bridge Io protocol
620 @param Protocol Point to protocol instance
621 @param HostBridgeHandle Handle of host bridge
622 @param Attri Attribute of host bridge
623 @param ResAppeture ResourceAppeture for host bridge
625 @retval EFI_SUCCESS Success to initialize the Pci Root Bridge.
629 RootBridgeConstructor (
630 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*Protocol
,
631 IN EFI_HANDLE HostBridgeHandle
,
633 IN PCI_ROOT_BRIDGE_RESOURCE_APPETURE
*ResAppeture
637 PCI_ROOT_BRIDGE_INSTANCE
*PrivateData
;
638 PCI_RESOURCE_TYPE Index
;
640 PrivateData
= DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (Protocol
);
643 // The host to pci bridge, the host memory and io addresses are
644 // direct mapped to pci addresses, so no need translate, set bases to 0.
646 PrivateData
->MemBase
= ResAppeture
->MemBase
;
647 PrivateData
->IoBase
= ResAppeture
->IoBase
;
650 // The host bridge only supports 32bit addressing for memory
651 // and standard IA32 16bit io
653 PrivateData
->MemLimit
= ResAppeture
->MemLimit
;
654 PrivateData
->IoLimit
= ResAppeture
->IoLimit
;
657 // Bus Appeture for this Root Bridge (Possible Range)
659 PrivateData
->BusBase
= ResAppeture
->BusBase
;
660 PrivateData
->BusLimit
= ResAppeture
->BusLimit
;
663 // Specific for this chipset
665 for (Index
= TypeIo
; Index
< TypeMax
; Index
++) {
666 PrivateData
->ResAllocNode
[Index
].Type
= Index
;
667 PrivateData
->ResAllocNode
[Index
].Base
= 0;
668 PrivateData
->ResAllocNode
[Index
].Length
= 0;
669 PrivateData
->ResAllocNode
[Index
].Status
= ResNone
;
672 PrivateData
->PciAddress
= 0xCF8;
673 PrivateData
->PciData
= 0xCFC;
675 PrivateData
->RootBridgeAttrib
= Attri
;
677 PrivateData
->Attributes
= 0;
678 PrivateData
->Supports
= 0;
680 Protocol
->ParentHandle
= HostBridgeHandle
;
682 Protocol
->PollMem
= RootBridgeIoPollMem
;
683 Protocol
->PollIo
= RootBridgeIoPollIo
;
685 Protocol
->Mem
.Read
= RootBridgeIoMemRead
;
686 Protocol
->Mem
.Write
= RootBridgeIoMemWrite
;
688 Protocol
->Io
.Read
= RootBridgeIoIoRead
;
689 Protocol
->Io
.Write
= RootBridgeIoIoWrite
;
691 Protocol
->CopyMem
= RootBridgeIoCopyMem
;
693 Protocol
->Pci
.Read
= RootBridgeIoPciRead
;
694 Protocol
->Pci
.Write
= RootBridgeIoPciWrite
;
696 Protocol
->Map
= RootBridgeIoMap
;
697 Protocol
->Unmap
= RootBridgeIoUnmap
;
699 Protocol
->AllocateBuffer
= RootBridgeIoAllocateBuffer
;
700 Protocol
->FreeBuffer
= RootBridgeIoFreeBuffer
;
702 Protocol
->Flush
= RootBridgeIoFlush
;
704 Protocol
->GetAttributes
= RootBridgeIoGetAttributes
;
705 Protocol
->SetAttributes
= RootBridgeIoSetAttributes
;
707 Protocol
->Configuration
= RootBridgeIoConfiguration
;
709 Protocol
->SegmentNumber
= 0;
711 Status
= gBS
->LocateProtocol (&gEfiMetronomeArchProtocolGuid
, NULL
, (VOID
**)&mMetronome
);
712 ASSERT_EFI_ERROR (Status
);
718 Check parameters for IO,MMIO,PCI read/write services of PCI Root Bridge IO.
720 The I/O operations are carried out exactly as requested. The caller is responsible
721 for satisfying any alignment and I/O width restrictions that a PI System on a
722 platform might require. For example on some platforms, width requests of
723 EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
724 be handled by the driver.
726 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
727 @param[in] OperationType I/O operation type: IO/MMIO/PCI.
728 @param[in] Width Signifies the width of the I/O or Memory operation.
729 @param[in] Address The base address of the I/O operation.
730 @param[in] Count The number of I/O operations to perform. The number of
731 bytes moved is Width size * Count, starting at Address.
732 @param[in] Buffer For read operations, the destination buffer to store the results.
733 For write operations, the source buffer from which to write data.
735 @retval EFI_SUCCESS The parameters for this request pass the checks.
736 @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
737 @retval EFI_INVALID_PARAMETER Buffer is NULL.
738 @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
739 @retval EFI_UNSUPPORTED The address range specified by Address, Width,
740 and Count is not valid for this PI system.
744 RootBridgeIoCheckParameter (
745 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
746 IN OPERATION_TYPE OperationType
,
747 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
753 PCI_ROOT_BRIDGE_INSTANCE
*PrivateData
;
754 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS
*PciRbAddr
;
760 // Check to see if Buffer is NULL
762 if (Buffer
== NULL
) {
763 return EFI_INVALID_PARAMETER
;
767 // Check to see if Width is in the valid range
769 if (Width
< EfiPciWidthUint8
|| Width
>= EfiPciWidthMaximum
) {
770 return EFI_INVALID_PARAMETER
;
774 // For FIFO type, the target address won't increase during the access,
775 // so treat Count as 1
777 if (Width
>= EfiPciWidthFifoUint8
&& Width
<= EfiPciWidthFifoUint64
) {
782 // Check to see if Width is in the valid range for I/O Port operations
784 Width
= (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
) (Width
& 0x03);
785 if ((OperationType
!= MemOperation
) && (Width
== EfiPciWidthUint64
)) {
787 return EFI_INVALID_PARAMETER
;
791 // Check to see if Address is aligned
793 if ((Address
& (UINT64
)(mInStride
[Width
] - 1)) != 0) {
794 return EFI_UNSUPPORTED
;
797 PrivateData
= DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This
);
800 // Check to see if any address associated with this transfer exceeds the maximum
801 // allowed address. The maximum address implied by the parameters passed in is
802 // Address + Size * Count. If the following condition is met, then the transfer
805 // Address + Size * Count > Limit + 1
807 // Since Limit can be the maximum integer value supported by the CPU and Count
808 // can also be the maximum integer value supported by the CPU, this range
809 // check must be adjusted to avoid all oveflow conditions.
811 // The following form of the range check is equivalent but assumes that
812 // Limit is of the form (2^n - 1).
814 if (OperationType
== IoOperation
) {
815 Base
= PrivateData
->IoBase
;
816 Limit
= PrivateData
->IoLimit
;
817 } else if (OperationType
== MemOperation
) {
818 Base
= PrivateData
->MemBase
;
819 Limit
= PrivateData
->MemLimit
;
821 PciRbAddr
= (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS
*) &Address
;
822 if (PciRbAddr
->Bus
< PrivateData
->BusBase
|| PciRbAddr
->Bus
> PrivateData
->BusLimit
) {
823 return EFI_INVALID_PARAMETER
;
826 if (PciRbAddr
->Device
> MAX_PCI_DEVICE_NUMBER
|| PciRbAddr
->Function
> MAX_PCI_FUNCTION_NUMBER
) {
827 return EFI_INVALID_PARAMETER
;
830 if (PciRbAddr
->ExtendedRegister
!= 0) {
831 Address
= PciRbAddr
->ExtendedRegister
;
833 Address
= PciRbAddr
->Register
;
836 Limit
= MAX_PCI_REG_ADDRESS
;
839 if (Address
< Base
) {
840 return EFI_INVALID_PARAMETER
;
844 if (Address
> Limit
) {
845 return EFI_UNSUPPORTED
;
848 MaxCount
= RShiftU64 (Limit
, Width
);
849 if (MaxCount
< (Count
- 1)) {
850 return EFI_UNSUPPORTED
;
852 if (Address
> LShiftU64 (MaxCount
- Count
+ 1, Width
)) {
853 return EFI_UNSUPPORTED
;
861 Internal help function for read and write memory space.
863 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
864 @param[in] Write Switch value for Read or Write.
865 @param[in] Width Signifies the width of the memory operations.
866 @param[in] UserAddress The address within the PCI configuration space for the PCI controller.
867 @param[in] Count The number of PCI configuration operations to perform. Bytes
868 moved is Width size * Count, starting at Address.
869 @param[out] UserBuffer For read operations, the destination buffer to store the results. For
870 write operations, the source buffer to write data from.
872 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
873 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
874 @retval EFI_INVALID_PARAMETER Buffer is NULL.
875 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
880 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
882 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
891 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth
;
894 Status
= RootBridgeIoCheckParameter (This
, MemOperation
, Width
, Address
, Count
, Buffer
);
895 if (EFI_ERROR (Status
)) {
899 InStride
= mInStride
[Width
];
900 OutStride
= mOutStride
[Width
];
901 OperationWidth
= (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
) (Width
& 0x03);
902 for (Uint8Buffer
= Buffer
; Count
> 0; Address
+= InStride
, Uint8Buffer
+= OutStride
, Count
--) {
904 switch (OperationWidth
) {
905 case EfiPciWidthUint8
:
906 MmioWrite8 ((UINTN
)Address
, *Uint8Buffer
);
908 case EfiPciWidthUint16
:
909 MmioWrite16 ((UINTN
)Address
, *((UINT16
*)Uint8Buffer
));
911 case EfiPciWidthUint32
:
912 MmioWrite32 ((UINTN
)Address
, *((UINT32
*)Uint8Buffer
));
914 case EfiPciWidthUint64
:
915 MmioWrite64 ((UINTN
)Address
, *((UINT64
*)Uint8Buffer
));
919 switch (OperationWidth
) {
920 case EfiPciWidthUint8
:
921 *Uint8Buffer
= MmioRead8 ((UINTN
)Address
);
923 case EfiPciWidthUint16
:
924 *((UINT16
*)Uint8Buffer
) = MmioRead16 ((UINTN
)Address
);
926 case EfiPciWidthUint32
:
927 *((UINT32
*)Uint8Buffer
) = MmioRead32 ((UINTN
)Address
);
929 case EfiPciWidthUint64
:
930 *((UINT64
*)Uint8Buffer
) = MmioRead64 ((UINTN
)Address
);
939 Internal help function for read and write IO space.
941 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
942 @param[in] Write Switch value for Read or Write.
943 @param[in] Width Signifies the width of the memory operations.
944 @param[in] UserAddress The address within the PCI configuration space for the PCI controller.
945 @param[in] Count The number of PCI configuration operations to perform. Bytes
946 moved is Width size * Count, starting at Address.
947 @param[out] UserBuffer For read operations, the destination buffer to store the results. For
948 write operations, the source buffer to write data from.
950 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
951 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
952 @retval EFI_INVALID_PARAMETER Buffer is NULL.
953 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
958 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
960 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
969 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth
;
972 Status
= RootBridgeIoCheckParameter (This
, IoOperation
, Width
, Address
, Count
, Buffer
);
973 if (EFI_ERROR (Status
)) {
977 InStride
= mInStride
[Width
];
978 OutStride
= mOutStride
[Width
];
979 OperationWidth
= (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
) (Width
& 0x03);
980 for (Uint8Buffer
= Buffer
; Count
> 0; Address
+= InStride
, Uint8Buffer
+= OutStride
, Count
--) {
982 switch (OperationWidth
) {
983 case EfiPciWidthUint8
:
984 IoWrite8 ((UINTN
)Address
, *Uint8Buffer
);
986 case EfiPciWidthUint16
:
987 IoWrite16 ((UINTN
)Address
, *((UINT16
*)Uint8Buffer
));
989 case EfiPciWidthUint32
:
990 IoWrite32 ((UINTN
)Address
, *((UINT32
*)Uint8Buffer
));
994 switch (OperationWidth
) {
995 case EfiPciWidthUint8
:
996 *Uint8Buffer
= IoRead8 ((UINTN
)Address
);
998 case EfiPciWidthUint16
:
999 *((UINT16
*)Uint8Buffer
) = IoRead16 ((UINTN
)Address
);
1001 case EfiPciWidthUint32
:
1002 *((UINT32
*)Uint8Buffer
) = IoRead32 ((UINTN
)Address
);
1011 Internal help function for read and write PCI configuration space.
1013 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1014 @param[in] Write Switch value for Read or Write.
1015 @param[in] Width Signifies the width of the memory operations.
1016 @param[in] UserAddress The address within the PCI configuration space for the PCI controller.
1017 @param[in] Count The number of PCI configuration operations to perform. Bytes
1018 moved is Width size * Count, starting at Address.
1019 @param[out] UserBuffer For read operations, the destination buffer to store the results. For
1020 write operations, the source buffer to write data from.
1022 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
1023 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
1024 @retval EFI_INVALID_PARAMETER Buffer is NULL.
1025 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1030 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1032 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1041 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth
;
1043 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS
*PciRbAddr
;
1046 Status
= RootBridgeIoCheckParameter (This
, PciOperation
, Width
, Address
, Count
, Buffer
);
1047 if (EFI_ERROR (Status
)) {
1051 PciRbAddr
= (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS
*) &Address
;
1053 PcieRegAddr
= (UINTN
) PCI_LIB_ADDRESS (
1056 PciRbAddr
->Function
,
1057 (PciRbAddr
->ExtendedRegister
!= 0) ? \
1058 PciRbAddr
->ExtendedRegister
:
1062 InStride
= mInStride
[Width
];
1063 OutStride
= mOutStride
[Width
];
1064 OperationWidth
= (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
) (Width
& 0x03);
1065 for (Uint8Buffer
= Buffer
; Count
> 0; PcieRegAddr
+= InStride
, Uint8Buffer
+= OutStride
, Count
--) {
1067 switch (OperationWidth
) {
1068 case EfiPciWidthUint8
:
1069 PciWrite8 (PcieRegAddr
, *Uint8Buffer
);
1071 case EfiPciWidthUint16
:
1072 PciWrite16 (PcieRegAddr
, *((UINT16
*)Uint8Buffer
));
1074 case EfiPciWidthUint32
:
1075 PciWrite32 (PcieRegAddr
, *((UINT32
*)Uint8Buffer
));
1079 switch (OperationWidth
) {
1080 case EfiPciWidthUint8
:
1081 *Uint8Buffer
= PciRead8 (PcieRegAddr
);
1083 case EfiPciWidthUint16
:
1084 *((UINT16
*)Uint8Buffer
) = PciRead16 (PcieRegAddr
);
1086 case EfiPciWidthUint32
:
1087 *((UINT32
*)Uint8Buffer
) = PciRead32 (PcieRegAddr
);
1097 Polls an address in memory mapped I/O space until an exit condition is met, or
1100 This function provides a standard way to poll a PCI memory location. A PCI memory read
1101 operation is performed at the PCI memory address specified by Address for the width specified
1102 by Width. The result of this PCI memory read operation is stored in Result. This PCI memory
1103 read operation is repeated until either a timeout of Delay 100 ns units has expired, or (Result &
1104 Mask) is equal to Value.
1106 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1107 @param[in] Width Signifies the width of the memory operations.
1108 @param[in] Address The base address of the memory operations. The caller is
1109 responsible for aligning Address if required.
1110 @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask
1111 are ignored. The bits in the bytes below Width which are zero in
1112 Mask are ignored when polling the memory address.
1113 @param[in] Value The comparison value used for the polling exit criteria.
1114 @param[in] Delay The number of 100 ns units to poll. Note that timer available may
1115 be of poorer granularity.
1116 @param[out] Result Pointer to the last value read from the memory location.
1118 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
1119 @retval EFI_INVALID_PARAMETER Width is invalid.
1120 @retval EFI_INVALID_PARAMETER Result is NULL.
1121 @retval EFI_TIMEOUT Delay expired before a match occurred.
1122 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1127 RootBridgeIoPollMem (
1128 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1129 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1138 UINT64 NumberOfTicks
;
1141 if (Result
== NULL
) {
1142 return EFI_INVALID_PARAMETER
;
1145 if (Width
< 0 || Width
> EfiPciWidthUint64
) {
1146 return EFI_INVALID_PARAMETER
;
1150 // No matter what, always do a single poll.
1152 Status
= This
->Mem
.Read (This
, Width
, Address
, 1, Result
);
1153 if (EFI_ERROR (Status
)) {
1156 if ((*Result
& Mask
) == Value
) {
1166 // Determine the proper # of metronome ticks to wait for polling the
1167 // location. The nuber of ticks is Roundup (Delay / mMetronome->TickPeriod)+1
1168 // The "+1" to account for the possibility of the first tick being short
1169 // because we started in the middle of a tick.
1171 // BugBug: overriding mMetronome->TickPeriod with UINT32 until Metronome
1172 // protocol definition is updated.
1174 NumberOfTicks
= DivU64x32Remainder (Delay
, (UINT32
) mMetronome
->TickPeriod
, &Remainder
);
1175 if (Remainder
!= 0) {
1180 while (NumberOfTicks
) {
1182 mMetronome
->WaitForTick (mMetronome
, 1);
1184 Status
= This
->Mem
.Read (This
, Width
, Address
, 1, Result
);
1185 if (EFI_ERROR (Status
)) {
1189 if ((*Result
& Mask
) == Value
) {
1200 Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is
1201 satisfied or after a defined duration.
1203 This function provides a standard way to poll a PCI I/O location. A PCI I/O read operation is
1204 performed at the PCI I/O address specified by Address for the width specified by Width.
1205 The result of this PCI I/O read operation is stored in Result. This PCI I/O read operation is
1206 repeated until either a timeout of Delay 100 ns units has expired, or (Result & Mask) is equal
1209 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1210 @param[in] Width Signifies the width of the I/O operations.
1211 @param[in] Address The base address of the I/O operations. The caller is responsible
1212 for aligning Address if required.
1213 @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask
1214 are ignored. The bits in the bytes below Width which are zero in
1215 Mask are ignored when polling the I/O address.
1216 @param[in] Value The comparison value used for the polling exit criteria.
1217 @param[in] Delay The number of 100 ns units to poll. Note that timer available may
1218 be of poorer granularity.
1219 @param[out] Result Pointer to the last value read from the memory location.
1221 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
1222 @retval EFI_INVALID_PARAMETER Width is invalid.
1223 @retval EFI_INVALID_PARAMETER Result is NULL.
1224 @retval EFI_TIMEOUT Delay expired before a match occurred.
1225 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1230 RootBridgeIoPollIo (
1231 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1232 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1241 UINT64 NumberOfTicks
;
1245 // No matter what, always do a single poll.
1248 if (Result
== NULL
) {
1249 return EFI_INVALID_PARAMETER
;
1252 if (Width
< 0 || Width
> EfiPciWidthUint64
) {
1253 return EFI_INVALID_PARAMETER
;
1256 Status
= This
->Io
.Read (This
, Width
, Address
, 1, Result
);
1257 if (EFI_ERROR (Status
)) {
1260 if ((*Result
& Mask
) == Value
) {
1270 // Determine the proper # of metronome ticks to wait for polling the
1271 // location. The number of ticks is Roundup (Delay / mMetronome->TickPeriod)+1
1272 // The "+1" to account for the possibility of the first tick being short
1273 // because we started in the middle of a tick.
1275 NumberOfTicks
= DivU64x32Remainder (Delay
, (UINT32
)mMetronome
->TickPeriod
, &Remainder
);
1276 if (Remainder
!= 0) {
1281 while (NumberOfTicks
) {
1283 mMetronome
->WaitForTick (mMetronome
, 1);
1285 Status
= This
->Io
.Read (This
, Width
, Address
, 1, Result
);
1286 if (EFI_ERROR (Status
)) {
1290 if ((*Result
& Mask
) == Value
) {
1301 Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
1303 The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller
1304 registers in the PCI root bridge memory space.
1305 The memory operations are carried out exactly as requested. The caller is responsible for satisfying
1306 any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.
1308 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1309 @param[in] Width Signifies the width of the memory operation.
1310 @param[in] Address The base address of the memory operation. The caller is
1311 responsible for aligning the Address if required.
1312 @param[in] Count The number of memory operations to perform. Bytes moved is
1313 Width size * Count, starting at Address.
1314 @param[out] Buffer For read operations, the destination buffer to store the results. For
1315 write operations, the source buffer to write data from.
1317 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
1318 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
1319 @retval EFI_INVALID_PARAMETER Buffer is NULL.
1320 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1325 RootBridgeIoMemRead (
1326 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1327 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1333 return RootBridgeIoMemRW (This
, FALSE
, Width
, Address
, Count
, Buffer
);
1337 Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
1339 The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller
1340 registers in the PCI root bridge memory space.
1341 The memory operations are carried out exactly as requested. The caller is responsible for satisfying
1342 any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.
1344 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1345 @param[in] Width Signifies the width of the memory operation.
1346 @param[in] Address The base address of the memory operation. The caller is
1347 responsible for aligning the Address if required.
1348 @param[in] Count The number of memory operations to perform. Bytes moved is
1349 Width size * Count, starting at Address.
1350 @param[out] Buffer For read operations, the destination buffer to store the results. For
1351 write operations, the source buffer to write data from.
1353 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
1354 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
1355 @retval EFI_INVALID_PARAMETER Buffer is NULL.
1356 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1360 RootBridgeIoMemWrite (
1361 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1362 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1368 return RootBridgeIoMemRW (This
, TRUE
, Width
, Address
, Count
, Buffer
);
1372 Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
1374 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1375 @param[in] Width Signifies the width of the memory operations.
1376 @param[in] Address The base address of the I/O operation. The caller is responsible for
1377 aligning the Address if required.
1378 @param[in] Count The number of I/O operations to perform. Bytes moved is Width
1379 size * Count, starting at Address.
1380 @param[out] Buffer For read operations, the destination buffer to store the results. For
1381 write operations, the source buffer to write data from.
1383 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
1384 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
1385 @retval EFI_INVALID_PARAMETER Buffer is NULL.
1386 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1391 RootBridgeIoIoRead (
1392 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1393 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1399 return RootBridgeIoIoRW (This
, FALSE
, Width
, Address
, Count
, Buffer
);
1403 Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
1405 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1406 @param[in] Width Signifies the width of the memory operations.
1407 @param[in] Address The base address of the I/O operation. The caller is responsible for
1408 aligning the Address if required.
1409 @param[in] Count The number of I/O operations to perform. Bytes moved is Width
1410 size * Count, starting at Address.
1411 @param[out] Buffer For read operations, the destination buffer to store the results. For
1412 write operations, the source buffer to write data from.
1414 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
1415 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
1416 @retval EFI_INVALID_PARAMETER Buffer is NULL.
1417 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1422 RootBridgeIoIoWrite (
1423 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1424 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1430 return RootBridgeIoIoRW (This
, TRUE
, Width
, Address
, Count
, Buffer
);
1434 Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI
1435 root bridge memory space.
1437 The CopyMem() function enables a PCI driver to copy one region of PCI root bridge memory
1438 space to another region of PCI root bridge memory space. This is especially useful for video scroll
1439 operation on a memory mapped video buffer.
1440 The memory operations are carried out exactly as requested. The caller is responsible for satisfying
1441 any alignment and memory width restrictions that a PCI root bridge on a platform might require.
1443 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.
1444 @param[in] Width Signifies the width of the memory operations.
1445 @param[in] DestAddress The destination address of the memory operation. The caller is
1446 responsible for aligning the DestAddress if required.
1447 @param[in] SrcAddress The source address of the memory operation. The caller is
1448 responsible for aligning the SrcAddress if required.
1449 @param[in] Count The number of memory operations to perform. Bytes moved is
1450 Width size * Count, starting at DestAddress and SrcAddress.
1452 @retval EFI_SUCCESS The data was copied from one memory region to another memory region.
1453 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
1454 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1459 RootBridgeIoCopyMem (
1460 IN
struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1461 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1462 IN UINT64 DestAddress
,
1463 IN UINT64 SrcAddress
,
1473 if (Width
< 0 || Width
> EfiPciWidthUint64
) {
1474 return EFI_INVALID_PARAMETER
;
1477 if (DestAddress
== SrcAddress
) {
1481 Stride
= (UINTN
)(1 << Width
);
1484 if ((DestAddress
> SrcAddress
) && (DestAddress
< (SrcAddress
+ Count
* Stride
))) {
1486 SrcAddress
= SrcAddress
+ (Count
-1) * Stride
;
1487 DestAddress
= DestAddress
+ (Count
-1) * Stride
;
1490 for (Index
= 0;Index
< Count
;Index
++) {
1491 Status
= RootBridgeIoMemRead (
1498 if (EFI_ERROR (Status
)) {
1501 Status
= RootBridgeIoMemWrite (
1508 if (EFI_ERROR (Status
)) {
1512 SrcAddress
+= Stride
;
1513 DestAddress
+= Stride
;
1515 SrcAddress
-= Stride
;
1516 DestAddress
-= Stride
;
1523 Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.
1525 The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration
1526 registers for a PCI controller.
1527 The PCI Configuration operations are carried out exactly as requested. The caller is responsible for
1528 any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might
1531 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1532 @param[in] Width Signifies the width of the memory operations.
1533 @param[in] Address The address within the PCI configuration space for the PCI controller.
1534 @param[in] Count The number of PCI configuration operations to perform. Bytes
1535 moved is Width size * Count, starting at Address.
1536 @param[out] Buffer For read operations, the destination buffer to store the results. For
1537 write operations, the source buffer to write data from.
1539 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
1540 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
1541 @retval EFI_INVALID_PARAMETER Buffer is NULL.
1542 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1547 RootBridgeIoPciRead (
1548 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1549 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1555 return RootBridgeIoPciRW (This
, FALSE
, Width
, Address
, Count
, Buffer
);
1559 Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.
1561 The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration
1562 registers for a PCI controller.
1563 The PCI Configuration operations are carried out exactly as requested. The caller is responsible for
1564 any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might
1567 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1568 @param[in] Width Signifies the width of the memory operations.
1569 @param[in] Address The address within the PCI configuration space for the PCI controller.
1570 @param[in] Count The number of PCI configuration operations to perform. Bytes
1571 moved is Width size * Count, starting at Address.
1572 @param[out] Buffer For read operations, the destination buffer to store the results. For
1573 write operations, the source buffer to write data from.
1575 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
1576 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
1577 @retval EFI_INVALID_PARAMETER Buffer is NULL.
1578 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1583 RootBridgeIoPciWrite (
1584 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1585 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1591 return RootBridgeIoPciRW (This
, TRUE
, Width
, Address
, Count
, Buffer
);
1595 Provides the PCI controller-specific addresses required to access system memory from a
1598 The Map() function provides the PCI controller specific addresses needed to access system
1599 memory. This function is used to map system memory for PCI bus master DMA accesses.
1601 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1602 @param[in] Operation Indicates if the bus master is going to read or write to system memory.
1603 @param[in] HostAddress The system memory address to map to the PCI controller.
1604 @param[in][out] NumberOfBytes On input the number of bytes to map. On output the number of bytes that were mapped.
1605 @param[out] DeviceAddress The resulting map address for the bus master PCI controller to use
1606 to access the system memory's HostAddress.
1607 @param[out] Mapping The value to pass to Unmap() when the bus master DMA operation is complete.
1609 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
1610 @retval EFI_INVALID_PARAMETER Operation is invalid.
1611 @retval EFI_INVALID_PARAMETER HostAddress is NULL.
1612 @retval EFI_INVALID_PARAMETER NumberOfBytes is NULL.
1613 @retval EFI_INVALID_PARAMETER DeviceAddress is NULL.
1614 @retval EFI_INVALID_PARAMETER Mapping is NULL.
1615 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
1616 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
1617 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1623 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1624 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation
,
1625 IN VOID
*HostAddress
,
1626 IN OUT UINTN
*NumberOfBytes
,
1627 OUT EFI_PHYSICAL_ADDRESS
*DeviceAddress
,
1632 EFI_PHYSICAL_ADDRESS PhysicalAddress
;
1635 if (HostAddress
== NULL
|| NumberOfBytes
== NULL
|| DeviceAddress
== NULL
|| Mapping
== NULL
) {
1636 return EFI_INVALID_PARAMETER
;
1640 // Initialize the return values to their defaults
1645 // Make sure that Operation is valid
1647 if (Operation
< 0 || Operation
>= EfiPciOperationMaximum
) {
1648 return EFI_INVALID_PARAMETER
;
1652 // Most PCAT like chipsets can not handle performing DMA above 4GB.
1653 // If any part of the DMA transfer being mapped is above 4GB, then
1654 // map the DMA transfer to a buffer below 4GB.
1656 PhysicalAddress
= (EFI_PHYSICAL_ADDRESS
) (UINTN
) HostAddress
;
1657 if ((PhysicalAddress
+ *NumberOfBytes
) > 0x100000000ULL
) {
1660 // Common Buffer operations can not be remapped. If the common buffer
1661 // if above 4GB, then it is not possible to generate a mapping, so return
1664 if (Operation
== EfiPciOperationBusMasterCommonBuffer
|| Operation
== EfiPciOperationBusMasterCommonBuffer64
) {
1665 return EFI_UNSUPPORTED
;
1669 // Allocate a MAP_INFO structure to remember the mapping when Unmap() is
1672 Status
= gBS
->AllocatePool (
1673 EfiBootServicesData
,
1677 if (EFI_ERROR (Status
)) {
1683 // Return a pointer to the MAP_INFO structure in Mapping
1688 // Initialize the MAP_INFO structure
1690 MapInfo
->Operation
= Operation
;
1691 MapInfo
->NumberOfBytes
= *NumberOfBytes
;
1692 MapInfo
->NumberOfPages
= EFI_SIZE_TO_PAGES(*NumberOfBytes
);
1693 MapInfo
->HostAddress
= PhysicalAddress
;
1694 MapInfo
->MappedHostAddress
= 0x00000000ffffffff;
1697 // Allocate a buffer below 4GB to map the transfer to.
1699 Status
= gBS
->AllocatePages (
1701 EfiBootServicesData
,
1702 MapInfo
->NumberOfPages
,
1703 &MapInfo
->MappedHostAddress
1705 if (EFI_ERROR (Status
)) {
1706 gBS
->FreePool (MapInfo
);
1712 // If this is a read operation from the Bus Master's point of view,
1713 // then copy the contents of the real buffer into the mapped buffer
1714 // so the Bus Master can read the contents of the real buffer.
1716 if (Operation
== EfiPciOperationBusMasterRead
|| Operation
== EfiPciOperationBusMasterRead64
) {
1718 (VOID
*)(UINTN
)MapInfo
->MappedHostAddress
,
1719 (VOID
*)(UINTN
)MapInfo
->HostAddress
,
1720 MapInfo
->NumberOfBytes
1725 // The DeviceAddress is the address of the maped buffer below 4GB
1727 *DeviceAddress
= MapInfo
->MappedHostAddress
;
1730 // The transfer is below 4GB, so the DeviceAddress is simply the HostAddress
1732 *DeviceAddress
= PhysicalAddress
;
1739 Completes the Map() operation and releases any corresponding resources.
1741 The Unmap() function completes the Map() operation and releases any corresponding resources.
1742 If the operation was an EfiPciOperationBusMasterWrite or
1743 EfiPciOperationBusMasterWrite64, the data is committed to the target system memory.
1744 Any resources used for the mapping are freed.
1746 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1747 @param[in] Mapping The mapping value returned from Map().
1749 @retval EFI_SUCCESS The range was unmapped.
1750 @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().
1751 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
1757 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1764 // See if the Map() operation associated with this Unmap() required a mapping buffer.
1765 // If a mapping buffer was not required, then this function simply returns EFI_SUCCESS.
1767 if (Mapping
!= NULL
) {
1769 // Get the MAP_INFO structure from Mapping
1771 MapInfo
= (MAP_INFO
*)Mapping
;
1774 // If this is a write operation from the Bus Master's point of view,
1775 // then copy the contents of the mapped buffer into the real buffer
1776 // so the processor can read the contents of the real buffer.
1778 if (MapInfo
->Operation
== EfiPciOperationBusMasterWrite
|| MapInfo
->Operation
== EfiPciOperationBusMasterWrite64
) {
1780 (VOID
*)(UINTN
)MapInfo
->HostAddress
,
1781 (VOID
*)(UINTN
)MapInfo
->MappedHostAddress
,
1782 MapInfo
->NumberOfBytes
1787 // Free the mapped buffer and the MAP_INFO structure.
1789 gBS
->FreePages (MapInfo
->MappedHostAddress
, MapInfo
->NumberOfPages
);
1790 gBS
->FreePool (Mapping
);
1796 Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or
1797 EfiPciOperationBusMasterCommonBuffer64 mapping.
1799 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1800 @param Type This parameter is not used and must be ignored.
1801 @param MemoryType The type of memory to allocate, EfiBootServicesData or EfiRuntimeServicesData.
1802 @param Pages The number of pages to allocate.
1803 @param HostAddress A pointer to store the base system memory address of the allocated range.
1804 @param Attributes The requested bit mask of attributes for the allocated range. Only
1805 the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, EFI_PCI_ATTRIBUTE_MEMORY_CACHED,
1806 and EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this function.
1808 @retval EFI_SUCCESS The requested memory pages were allocated.
1809 @retval EFI_INVALID_PARAMETER MemoryType is invalid.
1810 @retval EFI_INVALID_PARAMETER HostAddress is NULL.
1811 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
1812 MEMORY_WRITE_COMBINE, MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.
1813 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
1818 RootBridgeIoAllocateBuffer (
1819 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1820 IN EFI_ALLOCATE_TYPE Type
,
1821 IN EFI_MEMORY_TYPE MemoryType
,
1823 OUT VOID
**HostAddress
,
1824 IN UINT64 Attributes
1828 EFI_PHYSICAL_ADDRESS PhysicalAddress
;
1831 // Validate Attributes
1833 if (Attributes
& EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER
) {
1834 return EFI_UNSUPPORTED
;
1838 // Check for invalid inputs
1840 if (HostAddress
== NULL
) {
1841 return EFI_INVALID_PARAMETER
;
1845 // The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData
1847 if (MemoryType
!= EfiBootServicesData
&& MemoryType
!= EfiRuntimeServicesData
) {
1848 return EFI_INVALID_PARAMETER
;
1852 // Limit allocations to memory below 4GB
1854 PhysicalAddress
= (EFI_PHYSICAL_ADDRESS
)(0xffffffff);
1856 Status
= gBS
->AllocatePages (AllocateMaxAddress
, MemoryType
, Pages
, &PhysicalAddress
);
1857 if (EFI_ERROR (Status
)) {
1861 *HostAddress
= (VOID
*)(UINTN
)PhysicalAddress
;
1867 Frees memory that was allocated with AllocateBuffer().
1869 The FreeBuffer() function frees memory that was allocated with AllocateBuffer().
1871 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1872 @param Pages The number of pages to free.
1873 @param HostAddress The base system memory address of the allocated range.
1875 @retval EFI_SUCCESS The requested memory pages were freed.
1876 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
1877 was not allocated with AllocateBuffer().
1882 RootBridgeIoFreeBuffer (
1883 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1885 OUT VOID
*HostAddress
1888 return gBS
->FreePages ((EFI_PHYSICAL_ADDRESS
) (UINTN
) HostAddress
, Pages
);
1892 Flushes all PCI posted write transactions from a PCI host bridge to system memory.
1894 The Flush() function flushes any PCI posted write transactions from a PCI host bridge to system
1895 memory. Posted write transactions are generated by PCI bus masters when they perform write
1896 transactions to target addresses in system memory.
1897 This function does not flush posted write transactions from any PCI bridges. A PCI controller
1898 specific action must be taken to guarantee that the posted write transactions have been flushed from
1899 the PCI controller and from all the PCI bridges into the PCI host bridge. This is typically done with
1900 a PCI read transaction from the PCI controller prior to calling Flush().
1902 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1904 @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host
1905 bridge to system memory.
1906 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI
1907 host bridge due to a hardware error.
1913 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
1917 // not supported yet
1923 Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the
1924 attributes that a PCI root bridge is currently using.
1926 The GetAttributes() function returns the mask of attributes that this PCI root bridge supports
1927 and the mask of attributes that the PCI root bridge is currently using.
1929 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1930 @param Supported A pointer to the mask of attributes that this PCI root bridge
1931 supports setting with SetAttributes().
1932 @param Attributes A pointer to the mask of attributes that this PCI root bridge is
1935 @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI root
1936 bridge supports is returned in Supports. If Attributes is
1937 not NULL, then the attributes that the PCI root bridge is currently
1938 using is returned in Attributes.
1939 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
1944 RootBridgeIoGetAttributes (
1945 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1946 OUT UINT64
*Supported
,
1947 OUT UINT64
*Attributes
1950 PCI_ROOT_BRIDGE_INSTANCE
*PrivateData
;
1952 PrivateData
= DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This
);
1954 if (Attributes
== NULL
&& Supported
== NULL
) {
1955 return EFI_INVALID_PARAMETER
;
1959 // Set the return value for Supported and Attributes
1962 *Supported
= PrivateData
->Supports
;
1966 *Attributes
= PrivateData
->Attributes
;
1973 Sets attributes for a resource range on a PCI root bridge.
1975 The SetAttributes() function sets the attributes specified in Attributes for the PCI root
1976 bridge on the resource range specified by ResourceBase and ResourceLength. Since the
1977 granularity of setting these attributes may vary from resource type to resource type, and from
1978 platform to platform, the actual resource range and the one passed in by the caller may differ. As a
1979 result, this function may set the attributes specified by Attributes on a larger resource range
1980 than the caller requested. The actual range is returned in ResourceBase and
1981 ResourceLength. The caller is responsible for verifying that the actual range for which the
1982 attributes were set is acceptable.
1984 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1985 @param[in] Attributes The mask of attributes to set. If the attribute bit
1986 MEMORY_WRITE_COMBINE, MEMORY_CACHED, or
1987 MEMORY_DISABLE is set, then the resource range is specified by
1988 ResourceBase and ResourceLength. If
1989 MEMORY_WRITE_COMBINE, MEMORY_CACHED, and
1990 MEMORY_DISABLE are not set, then ResourceBase and
1991 ResourceLength are ignored, and may be NULL.
1992 @param[in][out] ResourceBase A pointer to the base address of the resource range to be modified
1993 by the attributes specified by Attributes.
1994 @param[in][out] ResourceLength A pointer to the length of the resource range to be modified by the
1995 attributes specified by Attributes.
1997 @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.
1998 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.
1999 @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
2004 RootBridgeIoSetAttributes (
2005 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
2006 IN UINT64 Attributes
,
2007 IN OUT UINT64
*ResourceBase
,
2008 IN OUT UINT64
*ResourceLength
2011 PCI_ROOT_BRIDGE_INSTANCE
*PrivateData
;
2013 PrivateData
= DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This
);
2016 if ((Attributes
& (~(PrivateData
->Supports
))) != 0) {
2017 return EFI_UNSUPPORTED
;
2022 // This is a generic driver for a PC-AT class system. It does not have any
2023 // chipset specific knowlegde, so none of the attributes can be set or
2024 // cleared. Any attempt to set attribute that are already set will succeed,
2025 // and any attempt to set an attribute that is not supported will fail.
2027 if (Attributes
& (~PrivateData
->Attributes
)) {
2028 return EFI_UNSUPPORTED
;
2035 Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI 2.0
2036 resource descriptors.
2038 There are only two resource descriptor types from the ACPI Specification that may be used to
2039 describe the current resources allocated to a PCI root bridge. These are the QWORD Address
2040 Space Descriptor (ACPI 2.0 Section 6.4.3.5.1), and the End Tag (ACPI 2.0 Section 6.4.2.8). The
2041 QWORD Address Space Descriptor can describe memory, I/O, and bus number ranges for dynamic
2042 or fixed resources. The configuration of a PCI root bridge is described with one or more QWORD
2043 Address Space Descriptors followed by an End Tag.
2045 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
2046 @param[out] Resources A pointer to the ACPI 2.0 resource descriptors that describe the
2047 current configuration of this PCI root bridge. The storage for the
2048 ACPI 2.0 resource descriptors is allocated by this function. The
2049 caller must treat the return buffer as read-only data, and the buffer
2050 must not be freed by the caller.
2052 @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.
2053 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.
2054 @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
2059 RootBridgeIoConfiguration (
2060 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
2061 OUT VOID
**Resources
2064 PCI_ROOT_BRIDGE_INSTANCE
*PrivateData
;
2067 PrivateData
= DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This
);
2069 for (Index
= 0; Index
< TypeMax
; Index
++) {
2070 if (PrivateData
->ResAllocNode
[Index
].Status
== ResAllocated
) {
2071 Configuration
.SpaceDesp
[Index
].AddrRangeMin
= PrivateData
->ResAllocNode
[Index
].Base
;
2072 Configuration
.SpaceDesp
[Index
].AddrRangeMax
= PrivateData
->ResAllocNode
[Index
].Base
+ PrivateData
->ResAllocNode
[Index
].Length
- 1;
2073 Configuration
.SpaceDesp
[Index
].AddrLen
= PrivateData
->ResAllocNode
[Index
].Length
;
2077 *Resources
= &Configuration
;