PerformancePkg/Library/DxeTscTimerLib/DxeTscTimerLib.c

   1 /** @file
   2   A Dxe Timer Library implementation which uses the Time Stamp Counter in the processor.
   3
   4   For Pentium 4 processors, Intel Xeon processors (family [0FH], models [03H and higher]);
   5     for Intel Core Solo and Intel Core Duo processors (family [06H], model [0EH]);
   6     for the Intel Xeon processor 5100 series and Intel Core 2 Duo processors (family [06H], model [0FH]);
   7     for Intel Core 2 and Intel Xeon processors (family [06H], display_model [17H]);
   8     for Intel Atom processors (family [06H], display_model [1CH]):
   9   the time-stamp counter increments at a constant rate.
  10   That rate may be set by the maximum core-clock to bus-clock ratio of the processor or may be set by
  11   the maximum resolved frequency at which the processor is booted. The maximum resolved frequency may
  12   differ from the maximum qualified frequency of the processor.
  13
  14   The specific processor configuration determines the behavior. Constant TSC behavior ensures that the
  15   duration of each clock tick is uniform and supports the use of the TSC as a wall clock timer even if
  16   the processor core changes frequency. This is the architectural behavior moving forward.
  17
  18   A Processor's support for invariant TSC is indicated by CPUID.0x80000007.EDX[8].
  19
  20   Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.<BR>
  21   This program and the accompanying materials
  22   are licensed and made available under the terms and conditions of the BSD License
  23   which accompanies this distribution. The full text of the license may be found at
  24   http://opensource.org/licenses/bsd-license.php
  25
  26   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  27   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  28
  29 **/
  30
  31 #include <PiDxe.h>
  32 #include <Ich/GenericIch.h>
  33
  34 #include <Library/TimerLib.h>
  35 #include <Library/BaseLib.h>
  36 #include <Library/IoLib.h>
  37 #include <Library/PciLib.h>
  38 #include <Library/PcdLib.h>
  39 #include <Library/HobLib.h>
  40
  41 #include <Guid/TscFrequency.h>
  42
  43 UINT64   mTscFrequency;
  44
  45 /** The constructor function determines the actual TSC frequency.
  46
  47   First, Get TSC frequency from TSC frequency GUID HOB,
  48   If the HOB is not found, calculate it.
  49
  50   The TSC counting frequency is determined by comparing how far it counts
  51   during a 1ms period as determined by the ACPI timer. The ACPI timer is
  52   used because it counts at a known frequency.
  53   If ACPI I/O space not enabled, this function will enable it. Then the
  54   TSC is sampled, followed by waiting for 3579 clocks of the ACPI timer, or 1ms.
  55   The TSC is then sampled again. The difference multiplied by 1000 is the TSC
  56   frequency. There will be a small error because of the overhead of reading
  57   the ACPI timer. An attempt is made to determine and compensate for this error.
  58   This function will always return EFI_SUCCESS.
  59
  60   @retval EFI_SUCCESS   The constructor always returns EFI_SUCCESS.
  61
  62 **/
  63 EFI_STATUS
  64 EFIAPI
  65 DxeTscTimerLibConstructor (
  66   IN EFI_HANDLE        ImageHandle,
  67   IN EFI_SYSTEM_TABLE  *SystemTable
  68   )
  69 {
  70   EFI_HOB_GUID_TYPE       *GuidHob;
  71   VOID        *DataInHob;
  72   UINT64      StartTSC;
  73   UINT64      EndTSC;
  74   UINT32      TimerAddr;
  75   UINT32      Ticks;
  76
  77   //
  78   // Get TSC frequency from TSC frequency GUID HOB.
  79   //
  80   GuidHob = GetFirstGuidHob (&gEfiTscFrequencyGuid);
  81   if (GuidHob != NULL) {
  82     DataInHob = GET_GUID_HOB_DATA (GuidHob);
  83     mTscFrequency = * (UINT64 *) DataInHob;
  84     return EFI_SUCCESS;
  85   }
  86
  87   //
  88   // TSC frequency GUID HOB is not found, calculate it.
  89   //
  90
  91   //
  92   // If ACPI I/O space is not enabled yet, program ACPI I/O base address and enable it.
  93   //
  94   if ((PciRead8 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_CNT)) & B_ICH_LPC_ACPI_CNT_ACPI_EN) == 0) {
  95     PciWrite16 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_BASE), PcdGet16 (PcdPerfPkgAcpiIoPortBaseAddress));
  96     PciOr8 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_CNT), B_ICH_LPC_ACPI_CNT_ACPI_EN);
  97   }
  98
  99   //
 100   // ACPI I/O space should be enabled now, locate the ACPI Timer.
 101   // ACPI I/O base address maybe have be initialized by other driver with different value,
 102   // So get it from PCI space directly.
 103   //
 104   TimerAddr = ((PciRead16 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_BASE))) & B_ICH_LPC_ACPI_BASE_BAR) + R_ACPI_PM1_TMR;
 105   Ticks    = IoRead32 (TimerAddr) + (3579);   // Set Ticks to 1ms in the future
 106   StartTSC = AsmReadTsc();                    // Get base value for the TSC
 107   //
 108   // Wait until the ACPI timer has counted 1ms.
 109   // Timer wrap-arounds are handled correctly by this function.
 110   // When the current ACPI timer value is greater than 'Ticks', the while loop will exit.
 111   //
 112   while (((Ticks - IoRead32 (TimerAddr)) & BIT23) == 0) {
 113     CpuPause();
 114   }
 115   EndTSC = AsmReadTsc();    // TSC value 1ms later
 116
 117   mTscFrequency =   MultU64x32 (
 118                       (EndTSC - StartTSC),    // Number of TSC counts in 1ms
 119                       1000                    // Number of ms in a second
 120                     );
 121   //
 122   // mTscFrequency is now equal to the number of TSC counts per second
 123   //
 124   return EFI_SUCCESS;
 125 }
 126
 127 /**  Stalls the CPU for at least the given number of ticks.
 128
 129   Stalls the CPU for at least the given number of ticks. It's invoked by
 130   MicroSecondDelay() and NanoSecondDelay().
 131
 132   @param[in]  Delay     A period of time to delay in ticks.
 133
 134 **/
 135 VOID
 136 InternalX86Delay (
 137   IN      UINT64                    Delay
 138   )
 139 {
 140   UINT64                             Ticks;
 141
 142   //
 143   // The target timer count is calculated here
 144   //
 145   Ticks = AsmReadTsc() + Delay;
 146
 147   //
 148   // Wait until time out
 149   // Timer wrap-arounds are NOT handled correctly by this function.
 150   // Thus, this function must be called within 10 years of reset since
 151   // Intel guarantees a minimum of 10 years before the TSC wraps.
 152   //
 153   while (AsmReadTsc() <= Ticks) CpuPause();
 154 }
 155
 156 /**  Stalls the CPU for at least the specified number of MicroSeconds.
 157
 158   @param[in]  MicroSeconds  The minimum number of microseconds to delay.
 159
 160   @return The value of MicroSeconds input.
 161
 162 **/
 163 UINTN
 164 EFIAPI
 165 MicroSecondDelay (
 166   IN      UINTN                     MicroSeconds
 167   )
 168 {
 169   InternalX86Delay (
 170     DivU64x32 (
 171       MultU64x64 (
 172         mTscFrequency,
 173         MicroSeconds
 174       ),
 175       1000000u
 176     )
 177   );
 178   return MicroSeconds;
 179 }
 180
 181 /**  Stalls the CPU for at least the specified number of NanoSeconds.
 182
 183   @param[in]  NanoSeconds The minimum number of nanoseconds to delay.
 184
 185   @return The value of NanoSeconds input.
 186
 187 **/
 188 UINTN
 189 EFIAPI
 190 NanoSecondDelay (
 191   IN      UINTN                     NanoSeconds
 192   )
 193 {
 194   InternalX86Delay (
 195     DivU64x32 (
 196       MultU64x32 (
 197         mTscFrequency,
 198         (UINT32)NanoSeconds
 199       ),
 200     1000000000u
 201     )
 202   );
 203   return NanoSeconds;
 204 }
 205
 206 /**  Retrieves the current value of the 64-bit free running Time-Stamp counter.
 207
 208   The time-stamp counter (as implemented in the P6 family, Pentium, Pentium M,
 209   Pentium 4, Intel Xeon, Intel Core Solo and Intel Core Duo processors and
 210   later processors) is a 64-bit counter that is set to 0 following a RESET of
 211   the processor.  Following a RESET, the counter increments even when the
 212   processor is halted by the HLT instruction or the external STPCLK# pin. Note
 213   that the assertion of the external DPSLP# pin may cause the time-stamp
 214   counter to stop.
 215
 216   The properties of the counter can be retrieved by the
 217   GetPerformanceCounterProperties() function.
 218
 219   @return The current value of the free running performance counter.
 220
 221 **/
 222 UINT64
 223 EFIAPI
 224 GetPerformanceCounter (
 225   VOID
 226   )
 227 {
 228   return AsmReadTsc();
 229 }
 230
 231 /**  Retrieves the 64-bit frequency in Hz and the range of performance counter
 232   values.
 233
 234   If StartValue is not NULL, then the value that the performance counter starts
 235   with, 0x0, is returned in StartValue. If EndValue is not NULL, then the value
 236   that the performance counter end with, 0xFFFFFFFFFFFFFFFF, is returned in
 237   EndValue.
 238
 239   The 64-bit frequency of the performance counter, in Hz, is always returned.
 240   To determine average processor clock frequency, Intel recommends the use of
 241   EMON logic to count processor core clocks over the period of time for which
 242   the average is required.
 243
 244
 245   @param[out]   StartValue  Pointer to where the performance counter's starting value is saved, or NULL.
 246   @param[out]   EndValue    Pointer to where the performance counter's ending value is saved, or NULL.
 247
 248   @return The frequency in Hz.
 249
 250 **/
 251 UINT64
 252 EFIAPI
 253 GetPerformanceCounterProperties (
 254   OUT      UINT64                    *StartValue,  OPTIONAL
 255   OUT      UINT64                    *EndValue     OPTIONAL
 256   )
 257 {
 258   if (StartValue != NULL) {
 259     *StartValue = 0;
 260   }
 261   if (EndValue != NULL) {
 262     *EndValue = 0xFFFFFFFFFFFFFFFFull;
 263   }
 264
 265   return mTscFrequency;
 266 }