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1 /** @file
2 CPU power management control methods
3
4 Copyright (c) 2013-2015 Intel Corporation.
5
6 SPDX-License-Identifier: BSD-2-Clause-Patent
7
8 **/
9
10 DefinitionBlock (
11 "CPUPM.aml",
12 "SSDT",
13 0x01,
14 "SsgPmm",
15 "CpuPm",
16 0x0010
17 )
18 {
19 External(\_PR.CPU0, DeviceObj)
20 External(CFGD, FieldUnitObj)
21
22 Scope(\)
23 {
24 // Config DWord, modified during POST
25 // Bit definitions are the same as PPMFlags:
26 // CFGD[0] = PPM_GV3 = GV3
27 // CFGD[1] = PPM_TURBO = Turbo Mode
28 // CFGD[2] = PPM_SUPER_LFM = N/2 Ratio
29 // CFGD[4] = PPM_C1 = C1 Capable, Enabled
30 // CFGD[5] = PPM_C2 = C2 Capable, Enabled
31 // CFGD[6] = PPM_C3 = C3 Capable, Enabled
32 // CFGD[7] = PPM_C4 = C4 Capable, Enabled
33 // CFGD[8] = PPM_C5 = C5/Deep C4 Capable, Enabled
34 // CFGD[9] = PPM_C6 = C6 Capable, Enabled
35 // CFGD[10] = PPM_C1E = C1E Enabled
36 // CFGD[11] = PPM_C2E = C2E Enabled
37 // CFGD[12] = PPM_C3E = C3E Enabled
38 // CFGD[13] = PPM_C4E = C4E Enabled
39 // CFGD[14] = PPM_HARD_C4E = Hard C4E Capable, Enabled
40 // CFGD[16] = PPM_TM1 = Thermal Monitor 1
41 // CFGD[17] = PPM_TM2 = Thermal Monitor 2
42 // CFGD[19] = PPM_PHOT = Bi-directional ProcHot
43 // CFGD[21] = PPM_MWAIT_EXT = MWAIT extensions supported
44 // CFGD[24] = PPM_CMP = CMP supported, Enabled
45 // CFGD[28] = PPM_TSTATE = CPU T states supported
46 //
47 // Name(CFGD, 0x80000000)
48 // External Defined in GNVS
49
50 Name(PDC0,0x80000000) // CPU0 _PDC Flags.
51
52 // We load it in AcpiPlatform
53 //Name(SSDT,Package()
54 //{
55 // "CPU0IST ", 0x80000000, 0x80000000,
56 // "CPU1IST ", 0x80000000, 0x80000000,
57 // "CPU0CST ", 0x80000000, 0x80000000,
58 // "CPU1CST ", 0x80000000, 0x80000000,
59 //})
60 }
61 Scope(\_PR.CPU0)
62 {
63 Method(_PDC, 1)
64 {
65 //
66 // Store result of PDC.
67 //
68 CreateDWordField(Arg0,8,CAP0) // Point to 3rd DWORD.
69 Store(CAP0,PDC0) // Store It in PDC0.
70 }
71 }
72
73 }