QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PciHostBridge.asi

   1 /** @file
   2 PCI Host Bridge Definitions
   3
   4 Copyright (c) 2013-2015 Intel Corporation.
   5
   6 SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9
  10
  11 Name(PBRS, ResourceTemplate() {
  12    WORDBusNumber(            //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
  13       ResourceProducer,      // bit 0 of general flags is 1
  14       MinFixed,              // Range is fixed
  15       MaxFixed,              // Range is fixed
  16       PosDecode,             // PosDecode
  17       0x0000,                // Granularity
  18       0x0000,                // Min
  19       0x001f,                // Max
  20       0x0000,                // Translation
  21       0x0020                 // Range Length = Max-Min+1
  22    )
  23
  24    WORDIO(                   //Consumed-and-produced resource (all I/O below CF8)
  25       ResourceProducer,      // bit 0 of general flags is 0
  26       MinFixed,              // Range is fixed
  27       MaxFixed,              // Range is fixed
  28       PosDecode,
  29       EntireRange,
  30       0x0000,                // Granularity
  31       0x0000,                // Min
  32       0x0cf7,                // Max
  33       0x0000,                // Translation
  34       0x0cf8                 // Range Length
  35    )
  36
  37    IO(                       //Consumed resource (CF8-CFF)
  38       Decode16,
  39       0x0cf8,
  40       0xcf8,
  41       1,
  42       8
  43    )
  44
  45    WORDIO(                   //Consumed-and-produced resource (all I/O above CFF)
  46       ResourceProducer,      // bit 0 of general flags is 0
  47       MinFixed,              // Range is fixed
  48       MaxFixed,              // Range is fixed
  49       PosDecode,
  50       EntireRange,
  51       0x0000,                // Granularity
  52       0x0d00,                // Min
  53       0xffff,                // Max
  54       0x0000,                // Translation
  55       0xf300                 // Range Length
  56    )
  57
  58    DWORDMEMORY(              // descriptor for dos area(0->0xa0000)
  59       ResourceProducer,      // bit 0 of general flags is 0
  60       PosDecode,
  61       MinFixed,              // Range is fixed
  62       MaxFixed,              // Range is Fixed
  63       Cacheable,
  64       ReadWrite,
  65       0x00000000,            // Granularity
  66       0x000a0000,            // Min
  67       0x000bffff,            // Max
  68       0x00000000,            // Translation
  69       0x00020000             // Range Length
  70    )
  71
  72    DWORDMemory(              // Consumed-and-produced resource for pci memory mapped memory
  73       ResourceProducer,      // bit 0 of general flags is 0
  74       PosDecode,             // positive Decode
  75       MinFixed,              // Range is fixed
  76       MaxFixed,              // Range is fixed
  77       Cacheable,
  78       ReadWrite,
  79       0x00000000,            // Granularity
  80       0x00000000,            // Min (calculated dynamically)
  81
  82       0xfebfffff,            // Max = IO Apic base address - 1
  83       0x00000000,            // Translation
  84       0xfec00000,            // Range Length (calculated dynamically)
  85       ,                      // Optional field left blank
  86       ,                      // Optional field left blank
  87       MEM1                   // Name declaration for this descriptor
  88    )
  89
  90 })          // end of CRES Buffer
  91
  92
  93 Method(_CRS, 0x0, NotSerialized)
  94 {
  95     CreateDWordField(PBRS, \_SB.PCI0.MEM1._MIN, MMIN)
  96     CreateDWordField(PBRS, \_SB.PCI0.MEM1._MAX, MMAX)
  97     CreateDWordField(PBRS, \_SB.PCI0.MEM1._LEN, MLEN)
  98
  99     // HMBOUND is PCI memory base
 100     And(MNRD(0x03, 0x08), 0xFFFFF000, MMIN)
 101     Add(Subtract(MMAX, MMIN), 1, MLEN)
 102
 103     Return(PBRS)
 104 }
 105
 106 // Message Nework Registers
 107 OperationRegion(MNR, PCI_Config, 0xD0, 0x10)
 108 Field(MNR, DWordAcc, NoLock, Preserve)
 109 {
 110     MCR, 32,           // Message Control Register
 111     MDR, 32            // Message Data Register
 112 }
 113
 114 // Message Nework Read Method
 115 // Arg0 = Port
 116 // Arg1 = RegAddress
 117 // return 32 bit register value
 118 Method(MNRD, 2, Serialized)
 119 {
 120     Or(ShiftLeft(Arg0, 16), ShiftLeft(Arg1, 8), Local0)
 121     Or(Local0, 0x100000F0, Local0)
 122     Store(Local0, MCR)
 123     Return(MDR)
 124 }
 125
 126 // Message Nework Write Method
 127 // Arg0 = Port
 128 // Arg1 = RegAddress
 129 // Arg2 = 32 bit write value
 130 Method(MNWR, 3, Serialized)
 131 {
 132     Store(Arg2, MDR)
 133     Or(ShiftLeft(Arg0, 16), ShiftLeft(Arg1, 8), Local0)
 134     Or(Local0, 0x110000F0, Local0)
 135     Store(Local0, MCR)
 136 }
 137
 138 Method(_PRT, 0, NotSerialized)
 139 {
 140   If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing
 141   {
 142     Return (
 143       Package()
 144       {
 145         // Bus 0, Device 20 - IOSFAHB Bridge
 146         Package() {0x0014ffff, 0, \_SB.PCI0.LPC.LNKA, 0}, // INTA
 147         Package() {0x0014ffff, 1, \_SB.PCI0.LPC.LNKB, 0}, // INTB
 148         Package() {0x0014ffff, 2, \_SB.PCI0.LPC.LNKC, 0}, // INTC
 149         Package() {0x0014ffff, 3, \_SB.PCI0.LPC.LNKD, 0}, // INTD
 150
 151         // Bus 0, Device 21 - IOSFAHB Bridge
 152         Package() {0x0015ffff, 0, \_SB.PCI0.LPC.LNKA, 0}, // INTA
 153         Package() {0x0015ffff, 1, \_SB.PCI0.LPC.LNKB, 0}, // INTB
 154         Package() {0x0015ffff, 2, \_SB.PCI0.LPC.LNKC, 0}, // INTC
 155         Package() {0x0015ffff, 3, \_SB.PCI0.LPC.LNKD, 0}, // INTD
 156
 157         // Bus 0, Device 23 - PCIe port 0
 158         Package() {0x0017ffff, 0, \_SB.PCI0.LPC.LNKE, 0}, // INTA
 159         Package() {0x0017ffff, 1, \_SB.PCI0.LPC.LNKF, 0}, // INTB
 160         Package() {0x0017ffff, 2, \_SB.PCI0.LPC.LNKG, 0}, // INTC
 161         Package() {0x0017ffff, 3, \_SB.PCI0.LPC.LNKH, 0}, // INTD
 162
 163         // Bus 0, Device 31
 164         Package() {0x001fffff, 0, \_SB.PCI0.LPC.LNKA, 0}, // LPC Bridge
 165       }
 166     )
 167   }
 168   else {
 169     Return (
 170       Package()
 171       {
 172         // Bus 0, Device 20 - IOSFAHB Bridge
 173         Package() {0x0014ffff, 0, 0, 16}, // INTA
 174         Package() {0x0014ffff, 1, 0, 17}, // INTB
 175         Package() {0x0014ffff, 2, 0, 18}, // INTC
 176         Package() {0x0014ffff, 3, 0, 19}, // INTD
 177
 178         // Bus 0, Device 21 - IOSFAHB Bridge
 179         Package() {0x0015ffff, 0, 0, 16}, // INTA
 180         Package() {0x0015ffff, 1, 0, 17}, // INTB
 181         Package() {0x0015ffff, 2, 0, 18}, // INTC
 182         Package() {0x0015ffff, 3, 0, 19}, // INTD
 183
 184         // Bus 0, Device 23 - PCIe port 0
 185         Package() {0x0017ffff, 0, 0, 20}, // INTA
 186         Package() {0x0017ffff, 1, 0, 21}, // INTB
 187         Package() {0x0017ffff, 2, 0, 22}, // INTC
 188         Package() {0x0017ffff, 3, 0, 23}, // INTD
 189
 190         // Bus 0, Device 31
 191         Package() {0x001fffff, 0, 0, 16}, // LPC Bridge
 192       }
 193     )
 194   }
 195 }