QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Platform.asl

   1 /** @file
   2 Contains root level name space objects for the platform
   3
   4 Copyright (c) 2013-2019 Intel Corporation.
   5
   6 SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9
  10 //
  11 // OS TYPE DEFINITION
  12 //
  13 #define WINDOWS_XP          0x01
  14 #define WINDOWS_XP_SP1      0x02
  15 #define WINDOWS_XP_SP2      0x04
  16 #define WINDOWS_2003        0x08
  17 #define WINDOWS_Vista       0x10
  18 #define WINDOWS_WIN7        0x11
  19 #define WINDOWS_WIN8        0x12
  20 #define WINDOWS_WIN8_1      0x13
  21 #define LINUX               0xF0
  22
  23 //
  24 // GPIO Interrupt Connection Resource Descriptor (GpioInt) usage.
  25 // GpioInt() descriptors maybe used in this file and included .asi files.
  26 //
  27 // The mapping below was provided by the first OS user that requested
  28 // GpioInt() support.
  29 // Other OS users that need GpioInt() support must use the following mapping.
  30 //
  31 #define QUARK_GPIO8_MAPPING         0x00
  32 #define QUARK_GPIO9_MAPPING         0x01
  33 #define QUARK_GPIO_SUS0_MAPPING     0x02
  34 #define QUARK_GPIO_SUS1_MAPPING     0x03
  35 #define QUARK_GPIO_SUS2_MAPPING     0x04
  36 #define QUARK_GPIO_SUS3_MAPPING     0x05
  37 #define QUARK_GPIO_SUS4_MAPPING     0x06
  38 #define QUARK_GPIO_SUS5_MAPPING     0x07
  39 #define QUARK_GPIO0_MAPPING         0x08
  40 #define QUARK_GPIO1_MAPPING         0x09
  41 #define QUARK_GPIO2_MAPPING         0x0A
  42 #define QUARK_GPIO3_MAPPING         0x0B
  43 #define QUARK_GPIO4_MAPPING         0x0C
  44 #define QUARK_GPIO5_MAPPING         0x0D
  45 #define QUARK_GPIO6_MAPPING         0x0E
  46 #define QUARK_GPIO7_MAPPING         0x0F
  47
  48 DefinitionBlock (
  49   "Platform.aml",
  50   "DSDT",
  51   1,
  52   "INTEL ",
  53   "QuarkNcS",
  54   3)
  55 {
  56     //
  57     // Global Variables
  58     //
  59     Name(\GPIC, 0x0)
  60
  61     //
  62     // Port 80
  63     //
  64     OperationRegion (DBG0, SystemIO, 0x80, 1)
  65     Field (DBG0, ByteAcc, NoLock, Preserve)
  66     { IO80,8 }
  67
  68     //
  69     // Access CMOS range
  70     //
  71     OperationRegion (ACMS, SystemIO, 0x72, 2)
  72     Field (ACMS, ByteAcc, NoLock, Preserve)
  73     { INDX, 8, DATA, 8 }
  74
  75     //
  76     // Global NVS Memory Block
  77     //
  78     OperationRegion (MNVS, SystemMemory, 0xFFFF0000, 512)
  79     Field (MNVS, ByteAcc, NoLock, Preserve)
  80     {
  81       OSTP, 32,
  82       CFGD, 32,
  83       HPEA, 32,  // HPET Enabled ?
  84
  85       P1BB, 32,  // Pm1blkIoBaseAddress;
  86       PBAB, 32,  // PmbaIoBaseAddress;
  87       GP0B, 32,  // Gpe0blkIoBaseAddress;
  88       GPAB, 32,  // GbaIoBaseAddress;
  89
  90       SMBB, 32,  // SmbaIoBaseAddress;
  91       NRV1, 32,  // GNVS reserved field 1.
  92       WDTB, 32,  // WdtbaIoBaseAddress;
  93
  94       HPTB, 32,  // HpetBaseAddress;
  95       HPTS, 32,  // HpetSize;
  96       PEXB, 32,  // PciExpressBaseAddress;
  97       PEXS, 32,  // PciExpressSize;
  98
  99       RCBB, 32,  // RcbaMmioBaseAddress;
 100       RCBS, 32,  // RcbaMmioSize;
 101       APCB, 32,  // IoApicBaseAddress;
 102       APCS, 32,  // IoApicSize;
 103
 104       TPMP, 32,  // TpmPresent ?
 105       DBGP, 32,  // DBG2 Present?
 106       PTYP, 32,  // Set to one of EFI_PLATFORM_TYPE enums.
 107       ALTS, 32,  // Use alternate I2c SLA addresses.
 108     }
 109
 110     OperationRegion (GPEB, SystemIO, 0x1100, 0x40)  //GPE Block
 111     Field (GPEB, AnyAcc, NoLock, Preserve)
 112     {
 113       Offset(0x10),
 114       SMIE, 32,                 // SMI Enable
 115       SMIS, 32,                 // SMI Status
 116     }
 117
 118     //
 119     //  Processor Objects
 120     //
 121     Scope(\_PR) {
 122         //
 123         // IO base will be updated at runtime with search key "PRIO"
 124         //
 125         Processor (CPU0, 0x01, 0x4F495250, 0x06) {}
 126     }
 127
 128     //
 129     // System Sleep States
 130     //
 131     Name (\_S0,Package (){0,0,0,0})
 132     Name (\_S3,Package (){5,0,0,0})
 133     Name (\_S4,Package (){6,0,0,0})
 134     Name (\_S5,Package (){7,0,0,0})
 135
 136     //
 137     //  General Purpose Event
 138     //
 139     Scope(\_GPE)
 140     {
 141         //
 142         // EGPE generated GPE
 143         //
 144         Method(_L0D, 0x0, NotSerialized)
 145         {
 146             //
 147             // Check EGPE for this wake event
 148             //
 149             Notify (\_SB.SLPB, 0x02)
 150
 151         }
 152
 153         //
 154         // GPIO generated GPE
 155         //
 156         Method(_L0E, 0x0, NotSerialized)
 157         {
 158             //
 159             // Check GPIO for this wake event
 160             //
 161             Notify (\_SB.PWRB, 0x02)
 162
 163         }
 164
 165         //
 166         // SCLT generated GPE
 167         //
 168         Method(_L0F, 0x0, NotSerialized)
 169         {
 170             //
 171             // Check SCLT for this wake event
 172             //
 173             Notify (\_SB.PCI0.SDIO, 0x02)
 174             Notify (\_SB.PCI0.URT0, 0x02)
 175             Notify (\_SB.PCI0.USBD, 0x02)
 176             Notify (\_SB.PCI0.EHCI, 0x02)
 177             Notify (\_SB.PCI0.OHCI, 0x02)
 178             Notify (\_SB.PCI0.URT1, 0x02)
 179             Notify (\_SB.PCI0.ENT0, 0x02)
 180             Notify (\_SB.PCI0.ENT1, 0x02)
 181             Notify (\_SB.PCI0.SPI0, 0x02)
 182             Notify (\_SB.PCI0.SPI1, 0x02)
 183             Notify (\_SB.PCI0.GIP0, 0x02)
 184
 185         }
 186
 187         //
 188         // Remote Management Unit generated GPE
 189         //
 190         Method(_L10, 0x0, NotSerialized)
 191         {
 192             //
 193             // Check Remote Management Unit for this wake event.
 194             //
 195         }
 196
 197         //
 198         // PCIE generated GPE
 199         //
 200         Method(_L11, 0x0, NotSerialized)
 201         {
 202             //
 203             // Check PCIE for this wake event
 204             //
 205             Notify (\_SB.PCI0.PEX0, 0x02)
 206             Notify (\_SB.PCI0.PEX1, 0x02)
 207         }
 208     }
 209
 210     //
 211     // define Sleeping button as mentioned in ACPI spec 2.0
 212     //
 213     Device (\_SB.SLPB)
 214     {
 215         Name (_HID, EISAID ("PNP0C0E"))
 216         Method (_PRW, 0, NotSerialized)
 217         {
 218             Return (Package (0x02) {0x0D,0x04})
 219         }
 220     }
 221
 222     //
 223     // define Power Button
 224     //
 225      Device (\_SB.PWRB)
 226     {
 227         Name (_HID, EISAID ("PNP0C0C"))
 228         Method (_PRW, 0, NotSerialized)
 229         {
 230             Return (Package (0x02) {0x0E,0x04})
 231         }
 232     }
 233     //
 234     // System Wake up
 235     //
 236     Method(_WAK, 1, Serialized)
 237     {
 238        // Do nothing here
 239        Return (0)
 240     }
 241
 242     //
 243     // System sleep down
 244     //
 245     Method (_PTS, 1, NotSerialized)
 246     {
 247         // Get ready for S3 sleep
 248         if (Lequal(Arg0,3))
 249         {
 250                 Store(0xffffffff,SMIS)     // clear SMI status
 251                 Store(SMIE, Local0)        // SMI Enable
 252                 Or(Local0,0x4,SMIE)        // Generate SMI on sleep
 253         }
 254     }
 255
 256     //
 257     // Determing PIC mode
 258     //
 259     Method(\_PIC, 1, NotSerialized)
 260     {
 261         Store(Arg0,\GPIC)
 262     }
 263
 264     //
 265     //  System Bus
 266     //
 267     Scope(\_SB)
 268     {
 269         Device(PCI0)
 270         {
 271             Name(_HID,EISAID ("PNP0A08"))          // PCI Express Root Bridge
 272             Name(_CID,EISAID ("PNP0A03"))          // Compatible PCI Root Bridge
 273
 274             Name(_ADR,0x00000000)                  // Device (HI WORD)=0, Func (LO WORD)=0
 275             Method (_INI)
 276             {
 277                 Store(LINUX, OSTP)                 // Set the default os is Linux
 278                 If (CondRefOf (_OSI))
 279                 {
 280                     //
 281                     //_OSI is supported, so it is WinXp or Win2003Server
 282                     //
 283                     If (\_OSI("Windows 2001"))
 284                     {
 285                         Store (WINDOWS_XP, OSTP)
 286                     }
 287                     If (\_OSI("Windows 2001 SP1"))
 288                     {
 289                         Store (WINDOWS_XP_SP1, OSTP)
 290                     }
 291                     If (\_OSI("Windows 2001 SP2"))
 292                     {
 293                         Store (WINDOWS_XP_SP2, OSTP)
 294                     }
 295                     If (\_OSI("Windows 2001.1"))
 296                     {
 297                         Store (WINDOWS_2003, OSTP)
 298                     }
 299                     If (\_OSI("Windows 2006"))
 300                     {
 301                         Store (WINDOWS_Vista, OSTP)
 302                     }
 303                     If (\_OSI("Windows 2009"))
 304                     {
 305                         Store (WINDOWS_WIN7, OSTP)
 306                     }
 307                     If (\_OSI("Windows 2012"))
 308                     {
 309                         Store (WINDOWS_WIN8, OSTP)
 310                     }
 311                     If (\_OSI("Windows 2013"))
 312                     {
 313                         Store (WINDOWS_WIN8_1, OSTP)
 314                     }
 315                     If (\_OSI("Linux"))
 316                     {
 317                       Store (LINUX, OSTP)
 318                     }
 319                 }
 320             }
 321
 322             Include ("PciHostBridge.asi")     // PCI0 Host bridge
 323             Include ("QNC.asi")               // QNC miscellaneous
 324             Include ("PcieExpansionPrt.asi")  // PCIe expansion bridges/devices
 325             Include ("QuarkSouthCluster.asi") // Quark South Cluster devices
 326             Include ("QNCLpc.asi")            // LPC bridge device
 327             Include ("QNCApic.asi")           // QNC I/O Apic device
 328
 329         }
 330
 331         //
 332         // Include asi files for I2C and SPI onboard devices.
 333         // Devices placed here instead of below relevant controllers.
 334         // Hardware topology information is maintained by the
 335         // ResourceSource arg to the I2CSerialBus/SPISerialBus macros
 336         // within the device asi files.
 337         //
 338         Include ("Tpm.asi")          // TPM device.
 339         Include ("CY8C9540A.asi")    // CY8C9540A 40Bit I/O Expander & EEPROM
 340         Include ("PCAL9555A.asi")    // NXP PCAL9555A I/O expander.
 341         Include ("PCA9685.asi")      // NXP PCA9685 PWM/LED controller.
 342         Include ("CAT24C08.asi")     // ONSEMI CAT24C08 I2C 8KB EEPROM.
 343         Include ("AD7298.asi")       // Analog devices AD7298 ADC.
 344         Include ("ADC108S102.asi")   // TI ADC108S102 ADC.
 345         Include ("GpioClient.asi")   // Software device to expose GPIO
 346     }
 347 }