QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt1.0.aslc

   1 /** @file
   2 This file describes the contents of the ACPI Fixed ACPI Description Table
   3 (FADT).  Some additional ACPI values are defined in Acpi1_0.h and Acpi2_0.h.
   4 All changes to the FADT contents should be done in this file.
   5
   6 Copyright (c) 2013-2015 Intel Corporation.
   7
   8 SPDX-License-Identifier: BSD-2-Clause-Patent
   9
  10 **/
  11
  12 #include "Fadt.h"
  13
  14 EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE FADT = {
  15   EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
  16   sizeof (EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE),
  17   EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
  18   0,                          // to make sum of entire table == 0
  19   EFI_ACPI_OEM_ID,            // OEMID is a 6 bytes long field
  20   EFI_ACPI_OEM_TABLE_ID,      // OEM table identification(8 bytes long)
  21   EFI_ACPI_OEM_REVISION,      // OEM revision number
  22   EFI_ACPI_CREATOR_ID,        // ASL compiler vendor ID
  23   EFI_ACPI_CREATOR_REVISION,  // ASL compiler revision number
  24   0,                     // Physical addesss of FACS
  25   0,                     // Physical address of DSDT
  26   INT_MODEL,             // System Interrupt Model
  27   RESERVED,              // reserved
  28   SCI_INT_VECTOR,        // System vector of SCI interrupt
  29   SMI_CMD_IO_PORT,       // Port address of SMI command port
  30   ACPI_ENABLE,           // value to write to port smi_cmd to enable ACPI
  31   ACPI_DISABLE,          // value to write to port smi_cmd to disable ACPI
  32   S4BIOS_REQ,            // Value to write to SMI CMD port to enter the S4BIOS state
  33   RESERVED,              // reserved - must be zero
  34   PM1a_EVT_BLK_ADDRESS,  // Port address of Power Mgt 1a Event Reg Blk
  35   PM1b_EVT_BLK_ADDRESS,  // Port address of Power Mgt 1b Event Reg Blk
  36   PM1a_CNT_BLK_ADDRESS,  // Port address of Power Mgt 1a Ctrl Reg Blk
  37   PM1b_CNT_BLK_ADDRESS,  // Port address of Power Mgt 1b Ctrl Reg Blk
  38   PM2_CNT_BLK_ADDRESS,   // Port address of Power Mgt 2  Ctrl Reg Blk
  39   PM_TMR_BLK_ADDRESS,    // Port address of Power Mgt Timer Ctrl Reg Blk
  40   GPE0_BLK_ADDRESS,      // Port addr of General Purpose Event 0 Reg Blk
  41   GPE1_BLK_ADDRESS,      // Port addr of General Purpose Event 1 Reg Blk
  42   PM1_EVT_LEN,           // Byte Length of ports at pm1X_evt_blk
  43   PM1_CNT_LEN,           // Byte Length of ports at pm1X_cnt_blk
  44   PM2_CNT_LEN,           // Byte Length of ports at pm2_cnt_blk
  45   PM_TM_LEN,             // Byte Length of ports at pm_tm_blk
  46   GPE0_BLK_LEN,          // Byte Length of ports at gpe0_blk
  47   GPE1_BLK_LEN,          // Byte Length of ports at gpe1_blk
  48   GPE1_BASE,             // offset in gpe model where gpe1 events start
  49   RESERVED,              // reserved
  50   P_LVL2_LAT,            // worst case HW latency to enter/exit C2 state
  51   P_LVL3_LAT,            // worst case HW latency to enter/exit C3 state
  52   FLUSH_SIZE,            // Size of area read to flush caches
  53   FLUSH_STRIDE,          // Stride used in flushing caches
  54   DUTY_OFFSET,           // bit location of duty cycle field in p_cnt reg
  55   DUTY_WIDTH,            // bit width of duty cycle field in p_cnt reg
  56   DAY_ALRM,              // index to day-of-month alarm in RTC CMOS RAM
  57   MON_ALRM,              // index to month-of-year alarm in RTC CMOS RAM
  58   CENTURY,               // index to century in RTC CMOS RAM
  59   RESERVED,              // reserved
  60   RESERVED,              // reserved
  61   RESERVED,              // reserved
  62   FLAG
  63 };
  64
  65 VOID*
  66 ReferenceAcpiTable (
  67   VOID
  68   )
  69
  70 {
  71   //
  72   // Reference the table being generated to prevent the optimizer from removing the
  73   // data structure from the exeutable
  74   //
  75   return (VOID*)&FADT;
  76 }