QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/SpiFlashDevice.c

   1 /** @file
   2   SPI flash device description.
   3
   4   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7
   8 **/
   9
  10 #include "SpiFlashDevice.h"
  11
  12 #define FLASH_SIZE  (FixedPcdGet32 (PcdFlashAreaSize))
  13
  14 SPI_INIT_TABLE  mSpiInitTable[] = {
  15   //
  16   // Macronix 32Mbit part
  17   //
  18   {
  19     SPI_MX25L3205_ID1,
  20     SPI_MX25L3205_ID2,
  21     SPI_MX25L3205_ID3,
  22     {
  23       SPI_COMMAND_WRITE_ENABLE,
  24       SPI_COMMAND_WRITE_S_EN
  25     },
  26     {
  27       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle33MHz, EnumSpiOperationJedecId},
  28       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle33MHz, EnumSpiOperationOther},
  29       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},
  30       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},
  31       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle20MHz, EnumSpiOperationReadData},
  32       {EnumSpiOpcodeWrite,       SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},
  33       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle33MHz, EnumSpiOperationReadStatus},
  34       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}
  35     },
  36     (UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset
  37     FLASH_SIZE   // BIOS image size in flash
  38   },
  39   //
  40   // Winbond 32Mbit part
  41   //
  42   {
  43     SPI_W25X32_ID1,
  44     SF_DEVICE_ID0_W25QXX,
  45     SF_DEVICE_ID1_W25Q32,
  46     {
  47       SPI_COMMAND_WRITE_ENABLE,
  48       SPI_COMMAND_WRITE_S_EN
  49     },
  50     {
  51       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},
  52       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},
  53       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
  54       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
  55       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},
  56       {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
  57       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
  58       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
  59     },
  60     (UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset
  61     FLASH_SIZE   // BIOS image size in flash
  62   },
  63   //
  64   // Winbond 32Mbit part
  65   //
  66   {
  67     SPI_W25X32_ID1,
  68     SPI_W25X32_ID2,
  69     SPI_W25X32_ID3,
  70     {
  71       SPI_COMMAND_WRITE_ENABLE,
  72       SPI_COMMAND_WRITE_S_EN
  73     },
  74     {
  75       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle33MHz, EnumSpiOperationJedecId},
  76       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle33MHz, EnumSpiOperationOther},
  77       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},
  78       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},
  79       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle33MHz, EnumSpiOperationReadData},
  80       {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle33MHz, EnumSpiOperationErase_4K_Byte},
  81       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle33MHz, EnumSpiOperationReadStatus},
  82       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}
  83     },
  84     (UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset
  85     FLASH_SIZE   // BIOS image size in flash
  86   },
  87   //
  88   // Atmel 32Mbit part
  89   //
  90   {
  91     SPI_AT26DF321_ID1,
  92     SPI_AT26DF321_ID2,  // issue: byte 2 identifies family/density for Atmel
  93     SPI_AT26DF321_ID3,
  94     {
  95       SPI_COMMAND_WRITE_ENABLE,
  96       SPI_COMMAND_WRITE_S_EN
  97     },
  98     {
  99       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle33MHz, EnumSpiOperationJedecId},
 100       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle33MHz, EnumSpiOperationOther},
 101       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},
 102       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},
 103       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle33MHz, EnumSpiOperationReadData},
 104       {EnumSpiOpcodeWrite,       SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},
 105       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle33MHz, EnumSpiOperationReadStatus},
 106       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}
 107     },
 108     (UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset
 109     FLASH_SIZE   // BIOS image size in flash
 110   },
 111
 112   //
 113   // Intel 32Mbit part bottom boot
 114   //
 115   {
 116     SPI_QH25F320_ID1,
 117     SPI_QH25F320_ID2,
 118     SPI_QH25F320_ID3,
 119     {
 120       SPI_COMMAND_WRITE_ENABLE,
 121       SPI_COMMAND_WRITE_ENABLE
 122     },
 123     {
 124       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle33MHz, EnumSpiOperationJedecId},
 125       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle33MHz, EnumSpiOperationOther},
 126       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},
 127       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},
 128       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle33MHz, EnumSpiOperationReadData},
 129       {EnumSpiOpcodeWrite,       SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},
 130       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle33MHz, EnumSpiOperationReadStatus},
 131       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}
 132     },
 133     0,           // BIOS Start Offset
 134     FLASH_SIZE   // BIOS image size in flash
 135   },
 136   //
 137   // SST 64Mbit part
 138   //
 139   {
 140     SPI_SST25VF080B_ID1,      // VendorId
 141     SF_DEVICE_ID0_25VF064C,   // DeviceId 0
 142     SF_DEVICE_ID1_25VF064C,   // DeviceId 1
 143     {
 144       SPI_COMMAND_WRITE_ENABLE,
 145       SPI_COMMAND_WRITE_S_EN
 146     },
 147     {
 148       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},
 149       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},
 150       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
 151       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
 152       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},
 153       {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
 154       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
 155       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
 156     },
 157     0x800000 - FLASH_SIZE,          // BIOS Start Offset
 158     FLASH_SIZE   // BIOS image size in flash
 159   },
 160   //
 161   // NUMONYX 64Mbit part
 162   //
 163   {
 164     SF_VENDOR_ID_NUMONYX,     // VendorId
 165     SF_DEVICE_ID0_M25PX64,    // DeviceId 0
 166     SF_DEVICE_ID1_M25PX64,    // DeviceId 1
 167     {
 168       SPI_COMMAND_WRITE_ENABLE,
 169       SPI_COMMAND_WRITE_S_EN
 170     },
 171     {
 172       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},
 173       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},
 174       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
 175       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
 176       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},
 177       {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
 178       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
 179       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
 180     },
 181     0x800000 - FLASH_SIZE,          // BIOS Start Offset
 182     FLASH_SIZE   // BIOS image size in flash
 183   },
 184   //
 185   // Atmel 64Mbit part
 186   //
 187   {
 188     SF_VENDOR_ID_ATMEL,       // VendorId
 189     SF_DEVICE_ID0_AT25DF641,  // DeviceId 0
 190     SF_DEVICE_ID1_AT25DF641,  // DeviceId 1
 191     {
 192       SPI_COMMAND_WRITE_ENABLE,
 193       SPI_COMMAND_WRITE_S_EN
 194     },
 195     {
 196       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},
 197       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},
 198       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
 199       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
 200       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},
 201       {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
 202       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
 203       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
 204     },
 205     0x800000 - FLASH_SIZE,          // BIOS Start Offset
 206     FLASH_SIZE   // BIOS image size in flash
 207   },
 208
 209   //
 210   // Spansion 64Mbit part
 211   //
 212   {
 213     SF_VENDOR_ID_SPANSION,       // VendorId
 214     SF_DEVICE_ID0_S25FL064K,  // DeviceId 0
 215     SF_DEVICE_ID1_S25FL064K,  // DeviceId 1
 216     {
 217       SPI_COMMAND_WRITE_ENABLE,
 218       SPI_COMMAND_WRITE_S_EN
 219     },
 220     {
 221       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},
 222       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},
 223       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
 224       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
 225       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},
 226       {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
 227       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
 228       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
 229     },
 230     0x800000 - FLASH_SIZE,          // BIOS Start Offset
 231     FLASH_SIZE   // BIOS image size in flash
 232   },
 233
 234   //
 235   // Macronix 64Mbit part bottom boot
 236   //
 237   {
 238     SF_VENDOR_ID_MX,          // VendorId
 239     SF_DEVICE_ID0_25L6405D,   // DeviceId 0
 240     SF_DEVICE_ID1_25L6405D,   // DeviceId 1
 241     {
 242       SPI_COMMAND_WRITE_ENABLE,
 243       SPI_COMMAND_WRITE_S_EN
 244     },
 245     {
 246       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},
 247       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},
 248       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
 249       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
 250       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},
 251       {EnumSpiOpcodeWrite,       SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte},
 252       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
 253       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
 254     },
 255     0x800000 - FLASH_SIZE,          // BIOS Start Offset
 256     FLASH_SIZE   // BIOS image size in flash
 257   },
 258   //
 259   // Winbond 64Mbit part bottom boot
 260   //
 261   {
 262     SPI_W25X64_ID1,
 263     SF_DEVICE_ID0_W25QXX,
 264     SF_DEVICE_ID1_W25Q64,
 265     {
 266       SPI_COMMAND_WRITE_ENABLE,
 267       SPI_COMMAND_WRITE_S_EN
 268     },
 269     {
 270       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},
 271       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},
 272       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
 273       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
 274       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},
 275       {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
 276       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
 277       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
 278     },
 279     0x800000 - FLASH_SIZE,          // BIOS Start Offset
 280     FLASH_SIZE   // BIOS image size in flash
 281   },
 282   //
 283   // Winbond 64Mbit part bottom boot
 284   //
 285   {
 286     SPI_W25X64_ID1,
 287     SPI_W25X64_ID2,
 288     SPI_W25X64_ID3,
 289     {
 290       SPI_COMMAND_WRITE_ENABLE,
 291       SPI_COMMAND_WRITE_S_EN
 292     },
 293     {
 294       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},
 295       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},
 296       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
 297       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
 298       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},
 299       {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
 300       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
 301       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
 302     },
 303     0x800000 - FLASH_SIZE,          // BIOS Start Offset
 304     FLASH_SIZE   // BIOS image size in flash
 305   },
 306   //
 307   // Intel 64Mbit part bottom boot
 308   //
 309   {
 310     SPI_QH25F640_ID1,
 311     SPI_QH25F640_ID2,
 312     SPI_QH25F640_ID3,
 313     {
 314       SPI_COMMAND_WRITE_ENABLE,
 315       SPI_COMMAND_WRITE_S_EN
 316     },
 317     {
 318       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle33MHz, EnumSpiOperationJedecId},
 319       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle33MHz, EnumSpiOperationOther},
 320       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},
 321       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},
 322       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle33MHz, EnumSpiOperationReadData},
 323       {EnumSpiOpcodeWrite,       SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},
 324       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle33MHz, EnumSpiOperationReadStatus},
 325       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}
 326     },
 327     0x800000 - FLASH_SIZE,          // BIOS Start Offset
 328     FLASH_SIZE   // BIOS image size in flash
 329   }
 330 };