QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/SpiFlashDevice.h

   1 /** @file
   2   SPI flash device header file.
   3
   4   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7 **/
   8
   9 #ifndef _SPI_FLASH_DEVICE_H_
  10 #define _SPI_FLASH_DEVICE_H_
  11
  12 #include <PiDxe.h>
  13 #include <Protocol/Spi.h>
  14 #include <Protocol/FirmwareVolumeBlock.h>
  15
  16 //
  17 // Supported SPI Flash Devices
  18 //
  19 typedef enum {
  20   EnumSpiFlash25L3205D,   // Macronix 32Mbit part
  21   EnumSpiFlashW25Q32,     // Winbond 32Mbit part
  22   EnumSpiFlashW25X32,     // Winbond 32Mbit part
  23   EnumSpiFlashAT25DF321,  // Atmel 32Mbit part
  24   EnumSpiFlashQH25F320,   // Intel 32Mbit part
  25   EnumSpiFlash25VF064C,   // SST 64Mbit part
  26   EnumSpiFlashM25PX64,    // NUMONYX 64Mbit part
  27   EnumSpiFlashAT25DF641,  // Atmel 64Mbit part
  28   EnumSpiFlashS25FL064K,  // Spansion 64Mbit part
  29   EnumSpiFlash25L6405D,   // Macronix 64Mbit part
  30   EnumSpiFlashW25Q64,     // Winbond 64Mbit part
  31   EnumSpiFlashW25X64,     // Winbond 64Mbit part
  32   EnumSpiFlashQH25F640,   // Intel 64Mbit part
  33   EnumSpiFlashMax
  34 } SPI_FLASH_TYPES_SUPPORTED;
  35
  36 //
  37 // Flash Device commands
  38 //
  39 // If a supported device uses a command different from the list below, a device specific command
  40 // will be defined just below it's JEDEC id section.
  41 //
  42 #define SPI_COMMAND_WRITE                 0x02
  43 #define SPI_COMMAND_WRITE_AAI             0xAD
  44 #define SPI_COMMAND_READ                  0x03
  45 #define SPI_COMMAND_ERASE                 0x20
  46 #define SPI_COMMAND_WRITE_DISABLE         0x04
  47 #define SPI_COMMAND_READ_S                0x05
  48 #define SPI_COMMAND_WRITE_ENABLE          0x06
  49 #define SPI_COMMAND_READ_ID               0xAB
  50 #define SPI_COMMAND_JEDEC_ID              0x9F
  51 #define SPI_COMMAND_WRITE_S_EN            0x50
  52 #define SPI_COMMAND_WRITE_S               0x01
  53 #define SPI_COMMAND_CHIP_ERASE            0xC7
  54 #define SPI_COMMAND_BLOCK_ERASE           0xD8
  55
  56 //
  57 // Flash JEDEC device ids
  58 //
  59 // SST 8Mbit part
  60 //
  61 #define SPI_SST25VF080B_ID1               0xBF
  62 #define SPI_SST25VF080B_ID2               0x25
  63 #define SPI_SST25VF080B_ID3               0x8E
  64 //
  65 // SST 16Mbit part
  66 //
  67 #define SPI_SST25VF016B_ID1               0xBF
  68 #define SPI_SST25VF016B_ID2               0x25
  69 #define SPI_SST25V016BF_ID3               0x41
  70 //
  71 // Macronix 32Mbit part
  72 //
  73 // MX25 part does not support WRITE_AAI comand (0xAD)
  74 //
  75 #define SPI_MX25L3205_ID1                 0xC2
  76 #define SPI_MX25L3205_ID2                 0x20
  77 #define SPI_MX25L3205_ID3                 0x16
  78 //
  79 // Intel 32Mbit part bottom boot
  80 //
  81 #define SPI_QH25F320_ID1                  0x89
  82 #define SPI_QH25F320_ID2                  0x89
  83 #define SPI_QH25F320_ID3                  0x12  // 32Mbit bottom boot
  84 //
  85 // Intel 64Mbit part bottom boot
  86 //
  87 #define SPI_QH25F640_ID1                  0x89
  88 #define SPI_QH25F640_ID2                  0x89
  89 #define SPI_QH25F640_ID3                  0x13  // 64Mbit bottom boot
  90 //
  91 // QH part does not support command 0x20 for erase; only 0xD8 (sector erase)
  92 // QH part has 0x40 command for erase of parameter block (8 x 8K blocks at bottom of part)
  93 // 0x40 command ignored if address outside of parameter block range
  94 //
  95 #define SPI_QH25F320_COMMAND_PBLOCK_ERASE 0x40
  96 //
  97 // Winbond 32Mbit part
  98 //
  99 #define SPI_W25X32_ID1                    0xEF
 100 #define SPI_W25X32_ID2                    0x30  // Memory Type
 101 #define SPI_W25X32_ID3                    0x16  // Capacity
 102 #define SF_DEVICE_ID1_W25Q32              0x16
 103
 104 //
 105 // Winbond 64Mbit part
 106 //
 107 #define SPI_W25X64_ID1                    0xEF
 108 #define SPI_W25X64_ID2                    0x30  // Memory Type
 109 #define SPI_W25X64_ID3                    0x17  // Capacity
 110 #define SF_DEVICE_ID0_W25QXX              0x40
 111 #define SF_DEVICE_ID1_W25Q64              0x17
 112 //
 113 // Winbond 128Mbit part
 114 //
 115 #define SF_DEVICE_ID0_W25Q128             0x40
 116 #define SF_DEVICE_ID1_W25Q128             0x18
 117
 118 //
 119 // Atmel 32Mbit part
 120 //
 121 #define SPI_AT26DF321_ID1                 0x1F
 122 #define SPI_AT26DF321_ID2                 0x47  // [7:5]=Family, [4:0]=Density
 123 #define SPI_AT26DF321_ID3                 0x00
 124
 125 #define SF_VENDOR_ID_ATMEL                0x1F
 126 #define SF_DEVICE_ID0_AT25DF641           0x48
 127 #define SF_DEVICE_ID1_AT25DF641           0x00
 128
 129 //
 130 // SST 8Mbit part
 131 //
 132 #define SPI_SST25VF080B_ID1               0xBF
 133 #define SPI_SST25VF080B_ID2               0x25
 134 #define SPI_SST25VF080B_ID3               0x8E
 135 #define SF_DEVICE_ID0_25VF064C            0x25
 136 #define SF_DEVICE_ID1_25VF064C            0x4B
 137
 138 //
 139 // SST 16Mbit part
 140 //
 141 #define SPI_SST25VF016B_ID1               0xBF
 142 #define SPI_SST25VF016B_ID2               0x25
 143 #define SPI_SST25V016BF_ID3               0x41
 144
 145 //
 146 // Winbond 32Mbit part
 147 //
 148 #define SPI_W25X32_ID1                    0xEF
 149 #define SPI_W25X32_ID2                    0x30  // Memory Type
 150 #define SPI_W25X32_ID3                    0x16  // Capacity
 151
 152 #define  SF_VENDOR_ID_MX             0xC2
 153 #define  SF_DEVICE_ID0_25L6405D      0x20
 154 #define  SF_DEVICE_ID1_25L6405D      0x17
 155
 156 #define  SF_VENDOR_ID_NUMONYX        0x20
 157 #define  SF_DEVICE_ID0_M25PX64       0x71
 158 #define  SF_DEVICE_ID1_M25PX64       0x17
 159
 160 //
 161 // Spansion 64Mbit part
 162 //
 163 #define SF_VENDOR_ID_SPANSION             0xEF
 164 #define SF_DEVICE_ID0_S25FL064K           0x40
 165 #define SF_DEVICE_ID1_S25FL064K           0x00
 166
 167 //
 168 // index for prefix opcodes
 169 //
 170 #define SPI_WREN_INDEX                    0   // Prefix Opcode 0: SPI_COMMAND_WRITE_ENABLE
 171 #define SPI_EWSR_INDEX                    1   // Prefix Opcode 1: SPI_COMMAND_WRITE_S_EN
 172 #define BIOS_CTRL                         0xDC
 173
 174 #define PFAB_CARD_DEVICE_ID               0x5150
 175 #define PFAB_CARD_VENDOR_ID               0x8086
 176 #define PFAB_CARD_SETUP_REGISTER          0x40
 177 #define PFAB_CARD_SETUP_BYTE              0x0d
 178
 179
 180 #endif