QuarkPlatformPkg/Include/PlatformBoards.h

   1 /** @file
   2 Board config definitions for each of the boards supported by this platform
   3 package.
   4
   5 Copyright (c) 2013 Intel Corporation.
   6
   7 SPDX-License-Identifier: BSD-2-Clause-Patent
   8
   9
  10 **/
  11 #include "Platform.h"
  12
  13 #ifndef __PLATFORM_BOARDS_H__
  14 #define __PLATFORM_BOARDS_H__
  15
  16 //
  17 // Constant definition
  18 //
  19
  20 //
  21 // Default resume well TPM reset.
  22 //
  23 #define PLATFORM_RESUMEWELL_TPM_RST_GPIO                5
  24
  25 //
  26 // Basic Configs for GPIO table definitions.
  27 //
  28 #define NULL_LEGACY_GPIO_INITIALIZER                    {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}
  29 #define ALL_INPUT_LEGACY_GPIO_INITIALIZER               {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x3f,0x00,0x00,0x00,0x00,0x00,0x3f,0x00}
  30 #define QUARK_EMULATION_LEGACY_GPIO_INITIALIZER         ALL_INPUT_LEGACY_GPIO_INITIALIZER
  31 #define CLANTON_PEAK_SVP_LEGACY_GPIO_INITIALIZER        {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x3f,0x00,0x00,0x3f,0x3f,0x00,0x3f,0x00}
  32 #define KIPS_BAY_LEGACY_GPIO_INITIALIZER                {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x25,0x10,0x00,0x00,0x00,0x00,0x3f,0x00}
  33 #define CROSS_HILL_LEGACY_GPIO_INITIALIZER              {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x03,0x10,0x00,0x03,0x03,0x00,0x3f,0x00}
  34 #define CLANTON_HILL_LEGACY_GPIO_INITIALIZER            {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x06,0x10,0x00,0x04,0x04,0x00,0x3f,0x00}
  35 #define GALILEO_LEGACY_GPIO_INITIALIZER                 {0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x21,0x14,0x00,0x00,0x00,0x00,0x3f,0x00}
  36 #define GALILEO_GEN2_LEGACY_GPIO_INITIALIZER            {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x1c,0x02,0x00,0x00,0x00,0x00,0x3f,0x00}
  37
  38 #define NULL_GPIO_CONTROLLER_INITIALIZER                {0,0,0,0,0,0,0,0}
  39 #define ALL_INPUT_GPIO_CONTROLLER_INITIALIZER           NULL_GPIO_CONTROLLER_INITIALIZER
  40 #define QUARK_EMULATION_GPIO_CONTROLLER_INITIALIZER     NULL_GPIO_CONTROLLER_INITIALIZER
  41 #define CLANTON_PEAK_SVP_GPIO_CONTROLLER_INITIALIZER    NULL_GPIO_CONTROLLER_INITIALIZER
  42 #define KIPS_BAY_GPIO_CONTROLLER_INITIALIZER            {0x05,0x05,0,0,0,0,0,0}
  43 #define CROSS_HILL_GPIO_CONTROLLER_INITIALIZER          {0x0D,0x2D,0,0,0,0,0,0}
  44 #define CLANTON_HILL_GPIO_CONTROLLER_INITIALIZER        {0x01,0x39,0,0,0,0,0,0}
  45 #define GALILEO_GPIO_CONTROLLER_INITIALIZER             {0x05,0x15,0,0,0,0,0,0}
  46 #define GALILEO_GEN2_GPIO_CONTROLLER_INITIALIZER        {0x05,0x05,0,0,0,0,0,0}
  47
  48 //
  49 // Legacy Gpio to be used to assert / deassert PCI express PERST# signal
  50 // on Galileo Gen 2 platform.
  51 //
  52 #define GALILEO_GEN2_PCIEXP_PERST_RESUMEWELL_GPIO       0
  53
  54 //
  55 // Io expander slave address.
  56 //
  57
  58 //
  59 // On Galileo value of Jumper J2 determines slave address of io expander.
  60 //
  61 #define GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO     5
  62 #define GALILEO_IOEXP_J2HI_7BIT_SLAVE_ADDR              0x20
  63 #define GALILEO_IOEXP_J2LO_7BIT_SLAVE_ADDR              0x21
  64
  65 //
  66 // Three IO Expmanders at fixed addresses on Galileo Gen2.
  67 //
  68 #define GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR             0x25
  69 #define GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR             0x26
  70 #define GALILEO_GEN2_IOEXP2_7BIT_SLAVE_ADDR             0x27
  71
  72 //
  73 // Led GPIOs for flash update / recovery.
  74 //
  75 #define GALILEO_FLASH_UPDATE_LED_RESUMEWELL_GPIO        1
  76 #define GALILEO_GEN2_FLASH_UPDATE_LED_RESUMEWELL_GPIO   5
  77
  78 //
  79 // Legacy GPIO config struct for each element in PLATFORM_LEGACY_GPIO_TABLE_DEFINITION.
  80 //
  81 typedef struct {
  82   UINT32  CoreWellEnable;               ///< Value for QNC NC Reg R_QNC_GPIO_CGEN_CORE_WELL.
  83   UINT32  CoreWellIoSelect;             ///< Value for QNC NC Reg R_QNC_GPIO_CGIO_CORE_WELL.
  84   UINT32  CoreWellLvlForInputOrOutput;  ///< Value for QNC NC Reg R_QNC_GPIO_CGLVL_CORE_WELL.
  85   UINT32  CoreWellTriggerPositiveEdge;  ///< Value for QNC NC Reg R_QNC_GPIO_CGTPE_CORE_WELL.
  86   UINT32  CoreWellTriggerNegativeEdge;  ///< Value for QNC NC Reg R_QNC_GPIO_CGTNE_CORE_WELL.
  87   UINT32  CoreWellGPEEnable;            ///< Value for QNC NC Reg R_QNC_GPIO_CGGPE_CORE_WELL.
  88   UINT32  CoreWellSMIEnable;            ///< Value for QNC NC Reg R_QNC_GPIO_CGSMI_CORE_WELL.
  89   UINT32  CoreWellTriggerStatus;        ///< Value for QNC NC Reg R_QNC_GPIO_CGTS_CORE_WELL.
  90   UINT32  CoreWellNMIEnable;            ///< Value for QNC NC Reg R_QNC_GPIO_CGNMIEN_CORE_WELL.
  91   UINT32  ResumeWellEnable;             ///< Value for QNC NC Reg R_QNC_GPIO_RGEN_RESUME_WELL.
  92   UINT32  ResumeWellIoSelect;           ///< Value for QNC NC Reg R_QNC_GPIO_RGIO_RESUME_WELL.
  93   UINT32  ResumeWellLvlForInputOrOutput;///< Value for QNC NC Reg R_QNC_GPIO_RGLVL_RESUME_WELL.
  94   UINT32  ResumeWellTriggerPositiveEdge;///< Value for QNC NC Reg R_QNC_GPIO_RGTPE_RESUME_WELL.
  95   UINT32  ResumeWellTriggerNegativeEdge;///< Value for QNC NC Reg R_QNC_GPIO_RGTNE_RESUME_WELL.
  96   UINT32  ResumeWellGPEEnable;          ///< Value for QNC NC Reg R_QNC_GPIO_RGGPE_RESUME_WELL.
  97   UINT32  ResumeWellSMIEnable;          ///< Value for QNC NC Reg R_QNC_GPIO_RGSMI_RESUME_WELL.
  98   UINT32  ResumeWellTriggerStatus;      ///< Value for QNC NC Reg R_QNC_GPIO_RGTS_RESUME_WELL.
  99   UINT32  ResumeWellNMIEnable;          ///< Value for QNC NC Reg R_QNC_GPIO_RGNMIEN_RESUME_WELL.
 100 } BOARD_LEGACY_GPIO_CONFIG;
 101
 102 //
 103 // GPIO controller config struct for each element in PLATFORM_GPIO_CONTROLLER_CONFIG_DEFINITION.
 104 //
 105 typedef struct {
 106   UINT32  PortADR;                      ///< Value for IOH REG GPIO_SWPORTA_DR.
 107   UINT32  PortADir;                     ///< Value for IOH REG GPIO_SWPORTA_DDR.
 108   UINT32  IntEn;                        ///< Value for IOH REG GPIO_INTEN.
 109   UINT32  IntMask;                      ///< Value for IOH REG GPIO_INTMASK.
 110   UINT32  IntType;                      ///< Value for IOH REG GPIO_INTTYPE_LEVEL.
 111   UINT32  IntPolarity;                  ///< Value for IOH REG GPIO_INT_POLARITY.
 112   UINT32  Debounce;                     ///< Value for IOH REG GPIO_DEBOUNCE.
 113   UINT32  LsSync;                       ///< Value for IOH REG GPIO_LS_SYNC.
 114 } BOARD_GPIO_CONTROLLER_CONFIG;
 115
 116 ///
 117 /// Table of BOARD_LEGACY_GPIO_CONFIG structures for each board supported
 118 /// by this platform package.
 119 /// Table indexed with EFI_PLATFORM_TYPE enum value.
 120 ///
 121 #define PLATFORM_LEGACY_GPIO_TABLE_DEFINITION \
 122   /* EFI_PLATFORM_TYPE - TypeUnknown*/\
 123   NULL_LEGACY_GPIO_INITIALIZER,\
 124   /* EFI_PLATFORM_TYPE - QuarkEmulation*/\
 125   QUARK_EMULATION_LEGACY_GPIO_INITIALIZER,\
 126   /* EFI_PLATFORM_TYPE - ClantonPeakSVP*/\
 127   CLANTON_PEAK_SVP_LEGACY_GPIO_INITIALIZER,\
 128   /* EFI_PLATFORM_TYPE - KipsBay*/\
 129   KIPS_BAY_LEGACY_GPIO_INITIALIZER,\
 130   /* EFI_PLATFORM_TYPE - CrossHill*/\
 131   CROSS_HILL_LEGACY_GPIO_INITIALIZER,\
 132   /* EFI_PLATFORM_TYPE - ClantonHill*/\
 133   CLANTON_HILL_LEGACY_GPIO_INITIALIZER,\
 134   /* EFI_PLATFORM_TYPE - Galileo*/\
 135   GALILEO_LEGACY_GPIO_INITIALIZER,\
 136   /* EFI_PLATFORM_TYPE - TypePlatformRsv7*/\
 137   NULL_LEGACY_GPIO_INITIALIZER,\
 138   /* EFI_PLATFORM_TYPE - GalileoGen2*/\
 139   GALILEO_GEN2_LEGACY_GPIO_INITIALIZER,\
 140
 141 ///
 142 /// Table of BOARD_GPIO_CONTROLLER_CONFIG structures for each board
 143 /// supported by this platform package.
 144 /// Table indexed with EFI_PLATFORM_TYPE enum value.
 145 ///
 146 #define PLATFORM_GPIO_CONTROLLER_CONFIG_DEFINITION \
 147   /* EFI_PLATFORM_TYPE - TypeUnknown*/\
 148   NULL_GPIO_CONTROLLER_INITIALIZER,\
 149   /* EFI_PLATFORM_TYPE - QuarkEmulation*/\
 150   QUARK_EMULATION_GPIO_CONTROLLER_INITIALIZER,\
 151   /* EFI_PLATFORM_TYPE - ClantonPeakSVP*/\
 152   CLANTON_PEAK_SVP_GPIO_CONTROLLER_INITIALIZER,\
 153   /* EFI_PLATFORM_TYPE - KipsBay*/\
 154   KIPS_BAY_GPIO_CONTROLLER_INITIALIZER,\
 155   /* EFI_PLATFORM_TYPE - CrossHill*/\
 156   CROSS_HILL_GPIO_CONTROLLER_INITIALIZER,\
 157   /* EFI_PLATFORM_TYPE - ClantonHill*/\
 158   CLANTON_HILL_GPIO_CONTROLLER_INITIALIZER,\
 159   /* EFI_PLATFORM_TYPE - Galileo*/\
 160   GALILEO_GPIO_CONTROLLER_INITIALIZER,\
 161   /* EFI_PLATFORM_TYPE - TypePlatformRsv7 */\
 162   NULL_GPIO_CONTROLLER_INITIALIZER,\
 163   /* EFI_PLATFORM_TYPE - GalileoGen2*/\
 164   GALILEO_GEN2_GPIO_CONTROLLER_INITIALIZER,\
 165
 166 #endif