QuarkPlatformPkg/Library/PlatformPcieHelperLib/SocUnit.c

   1 /** @file
   2 System On Chip Unit (SOCUnit) routines.
   3
   4 Copyright (c) 2013-2015 Intel Corporation.
   5
   6 SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9
  10 #include "CommonHeader.h"
  11
  12 /** Early initialisation of the SOC Unit
  13
  14   @retval   EFI_SUCCESS               Operation success.
  15
  16 **/
  17 EFI_STATUS
  18 EFIAPI
  19 SocUnitEarlyInitialisation (
  20   VOID
  21   )
  22 {
  23   UINT32      NewValue;
  24
  25   //
  26   // Set the mixer load resistance
  27   //
  28   NewValue = QNCPortIORead (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0);
  29   NewValue &= OCFGPIMIXLOAD_1_0_MASK;
  30   QNCPortIOWrite (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0, NewValue);
  31
  32   NewValue = QNCPortIORead (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1);
  33   NewValue &= OCFGPIMIXLOAD_1_0_MASK;
  34   QNCPortIOWrite (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1, NewValue);
  35
  36   return EFI_SUCCESS;
  37 }
  38
  39 /** Tasks to release PCI controller from reset pre wait for PLL Lock.
  40
  41   @retval   EFI_SUCCESS               Operation success.
  42
  43 **/
  44 EFI_STATUS
  45 EFIAPI
  46 SocUnitReleasePcieControllerPreWaitPllLock (
  47   IN CONST EFI_PLATFORM_TYPE              PlatformType
  48   )
  49 {
  50   UINT32      NewValue;
  51
  52   //
  53   // Assert PERST# and validate time assertion time.
  54   //
  55   PlatformPERSTAssert (PlatformType);
  56   ASSERT (PCIEXP_PERST_MIN_ASSERT_US <= (PCIEXP_DELAY_US_POST_CMNRESET_RESET + PCIEXP_DELAY_US_WAIT_PLL_LOCK + PCIEXP_DELAY_US_POST_SBI_RESET));
  57
  58   //
  59   // PHY Common lane reset.
  60   //
  61   NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);
  62   NewValue |= SOCCLKEN_CONFIG_PHY_I_CMNRESET_L;
  63   QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);
  64
  65   //
  66   // Wait post common lane reset.
  67   //
  68   MicroSecondDelay (PCIEXP_DELAY_US_POST_CMNRESET_RESET);
  69
  70   //
  71   // PHY Sideband interface reset.
  72   // Controller main reset
  73   //
  74   NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);
  75   NewValue |= (SOCCLKEN_CONFIG_SBI_RST_100_CORE_B | SOCCLKEN_CONFIG_PHY_I_SIDE_RST_L);
  76   QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);
  77
  78   return EFI_SUCCESS;
  79 }
  80
  81 /** Tasks to release PCI controller from reset after PLL has locked
  82
  83   @retval   EFI_SUCCESS               Operation success.
  84
  85 **/
  86 EFI_STATUS
  87 EFIAPI
  88 SocUnitReleasePcieControllerPostPllLock (
  89   IN CONST EFI_PLATFORM_TYPE              PlatformType
  90   )
  91 {
  92   UINT32 NewValue;
  93
  94   //
  95   // Controller sideband interface reset.
  96   //
  97   NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);
  98   NewValue |= SOCCLKEN_CONFIG_SBI_BB_RST_B;
  99   QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);
 100
 101   //
 102   // Wait post sideband interface reset.
 103   //
 104   MicroSecondDelay (PCIEXP_DELAY_US_POST_SBI_RESET);
 105
 106   //
 107   // Deassert PERST#.
 108   //
 109   PlatformPERSTDeAssert (PlatformType);
 110
 111   //
 112   // Wait post de assert PERST#.
 113   //
 114   MicroSecondDelay (PCIEXP_DELAY_US_POST_PERST_DEASSERT);
 115
 116   //
 117   // Controller primary interface reset.
 118   //
 119   NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);
 120   NewValue |= SOCCLKEN_CONFIG_BB_RST_B;
 121   QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);
 122
 123   return EFI_SUCCESS;
 124 }
 125