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1 /** @file
2 Platform SEC Library for Quark.
3
4 Copyright (c) 2013-2015 Intel Corporation.
5
6 SPDX-License-Identifier: BSD-2-Clause-Patent
7
8
9 **/
10
11 #include <PiPei.h>
12
13 #include <Ppi/SecPlatformInformation.h>
14 #include <Ppi/TemporaryRamSupport.h>
15 #include <Library/PcdLib.h>
16 #include <Library/BaseLib.h>
17 #include <Library/DebugLib.h>
18 #include <Library/BaseMemoryLib.h>
19 #include <Library/HobLib.h>
20 #include <Library/MtrrLib.h>
21
22 /**
23
24 Entry point to the C language phase of SEC. After the SEC assembly
25 code has initialized some temporary memory and set up the stack,
26 the control is transferred to this function.
27
28 @param SizeOfRam Size of the temporary memory available for use.
29 @param TempRamBase Base address of temporary ram
30 @param BootFirmwareVolume Base address of the Boot Firmware Volume.
31
32 **/
33 VOID
34 EFIAPI
35 SecStartup (
36 IN UINT32 SizeOfRam,
37 IN UINT32 TempRamBase,
38 IN VOID *BootFirmwareVolume
39 );
40
41 /**
42 Auto-generated function that calls the library constructors for all of the module's
43 dependent libraries. This function must be called by the SEC Core once a stack has
44 been established.
45
46 **/
47 VOID
48 EFIAPI
49 ProcessLibraryConstructorList (
50 VOID
51 );
52
53 /**
54
55 Entry point to the C language phase of PlatformSecLib. After the SEC assembly
56 code has initialized some temporary memory and set up the stack, control is
57 transferred to this function.
58
59 **/
60 VOID
61 EFIAPI
62 PlatformSecLibStartup (
63 VOID
64 )
65 {
66 //
67 // Process all library constructor functions linked to SecCore.
68 // This function must be called before any library functions are called
69 //
70 ProcessLibraryConstructorList ();
71
72 //
73 // Set write back cache attribute for SPI FLASH
74 //
75 MtrrSetMemoryAttribute (
76 PcdGet32 (PcdFlashAreaBaseAddress),
77 PcdGet32 (PcdFlashAreaSize),
78 CacheWriteBack
79 );
80
81 //
82 // Set write back cache attribute for 512KB Embedded SRAM
83 //
84 MtrrSetMemoryAttribute (
85 PcdGet32 (PcdEsramStage1Base),
86 SIZE_512KB,
87 CacheWriteBack
88 );
89
90 //
91 // Pass control to SecCore module passing in the size of the temporary RAM in
92 // Embedded SRAM, the base address of the temporary RAM in Embedded SRAM, and
93 // the base address of the boot firmware volume. The top 32KB of the 512 KB
94 // embedded SRAM are used as temporary RAM.
95 //
96 SecStartup (
97 SIZE_32KB,
98 PcdGet32 (PcdEsramStage1Base) + SIZE_512KB - SIZE_32KB,
99 (VOID *)(UINTN)PcdGet32 (PcdFlashFvRecoveryBase)
100 );
101 }
102
103 /**
104 A developer supplied function to perform platform specific operations.
105
106 It's a developer supplied function to perform any operations appropriate to a
107 given platform. It's invoked just before passing control to PEI core by SEC
108 core. Platform developer may modify the SecCoreData and PPI list that is
109 passed to PEI Core.
110
111 @param SecCoreData The same parameter as passing to PEI core. It
112 could be overridden by this function.
113 @param PpiList The default PPI list passed from generic SEC
114 part.
115
116 @return The final PPI list that platform wishes to passed to PEI core.
117
118 **/
119 EFI_PEI_PPI_DESCRIPTOR *
120 EFIAPI
121 SecPlatformMain (
122 IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData,
123 IN EFI_PEI_PPI_DESCRIPTOR *PpiList
124 )
125 {
126 return NULL;
127 }
128
129 /**
130 This interface conveys state information out of the Security (SEC) phase into PEI.
131
132 @param PeiServices Pointer to the PEI Services Table.
133 @param StructureSize Pointer to the variable describing size of the input buffer.
134 @param PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
135
136 @retval EFI_SUCCESS The data was successfully returned.
137 @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
138
139 **/
140 EFI_STATUS
141 EFIAPI
142 SecPlatformInformation (
143 IN CONST EFI_PEI_SERVICES **PeiServices,
144 IN OUT UINT64 *StructureSize,
145 OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
146 )
147 {
148 UINT32 *BIST;
149 UINT32 Size;
150 UINT32 Count;
151 EFI_HOB_GUID_TYPE *GuidHob;
152 UINT32 *TopOfStack;
153
154 //
155 // Top of the stack is the top of the 512KB Embedded SRAM region
156 //
157 TopOfStack = (UINT32 *)(UINTN)(PcdGet32 (PcdEsramStage1Base) + SIZE_512KB);
158
159 GuidHob = GetFirstGuidHob (&gEfiSecPlatformInformationPpiGuid);
160 if (GuidHob != NULL) {
161 Size = GET_GUID_HOB_DATA_SIZE (GuidHob);
162 BIST = GET_GUID_HOB_DATA (GuidHob);
163 } else {
164 //
165 // The entries of BIST information, together with the number of them,
166 // reside in the bottom of stack, left untouched by normal stack operation.
167 // This routine copies the BIST information to the buffer pointed by
168 // PlatformInformationRecord for output.
169 //
170 Count = *(TopOfStack - 1);
171 Size = Count * sizeof (IA32_HANDOFF_STATUS);
172 BIST = (UINT32 *) ((UINT32) TopOfStack - sizeof (UINT32) - Size);
173
174 //
175 // Copy Data from Stack to Hob to avoid data is lost after memory is ready.
176 //
177 BuildGuidDataHob (
178 &gEfiSecPlatformInformationPpiGuid,
179 BIST,
180 (UINTN)Size
181 );
182 GuidHob = GetFirstGuidHob (&gEfiSecPlatformInformationPpiGuid);
183 Size = GET_GUID_HOB_DATA_SIZE (GuidHob);
184 BIST = GET_GUID_HOB_DATA (GuidHob);
185 }
186
187 if ((*StructureSize) < (UINT64) Size) {
188 *StructureSize = Size;
189 return EFI_BUFFER_TOO_SMALL;
190 }
191
192 *StructureSize = Size;
193 CopyMem (PlatformInformationRecord, BIST, Size);
194
195 return EFI_SUCCESS;
196 }
197
198 /**
199 This interface disables temporary memory in SEC Phase.
200 **/
201 VOID
202 EFIAPI
203 SecPlatformDisableTemporaryMemory (
204 VOID
205 )
206 {
207 }