QuarkPlatformPkg/Platform/SpiFvbServices/SpiFlashDevice.c

   1 /** @file
   2 Initializes Platform Specific Drivers.
   3
   4 Copyright (c) 2013-2015 Intel Corporation.
   5
   6 This program and the accompanying materials
   7 are licensed and made available under the terms and conditions of the BSD License
   8 which accompanies this distribution.  The full text of the license may be found at
   9 http://opensource.org/licenses/bsd-license.php
  10
  11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14
  15 **/
  16
  17 #include "SpiFlashDevice.h"
  18
  19 #define FLASH_SIZE  (FixedPcdGet32 (PcdFlashAreaSize))
  20
  21 SPI_INIT_TABLE  mSpiInitTable[] = {
  22   //
  23   // Macronix 32Mbit part
  24   //
  25   {
  26     SPI_MX25L3205_ID1,
  27     SPI_MX25L3205_ID2,
  28     SPI_MX25L3205_ID3,
  29     {
  30       SPI_COMMAND_WRITE_ENABLE,
  31       SPI_COMMAND_WRITE_S_EN
  32     },
  33     {
  34       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle33MHz, EnumSpiOperationJedecId},
  35       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle33MHz, EnumSpiOperationOther},
  36       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},
  37       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},
  38       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle20MHz, EnumSpiOperationReadData},
  39       {EnumSpiOpcodeWrite,       SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},
  40       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle33MHz, EnumSpiOperationReadStatus},
  41       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}
  42     },
  43     0x400000 - FLASH_SIZE, // BIOS Start Offset
  44     FLASH_SIZE   // BIOS image size in flash
  45   },
  46   //
  47   // Winbond 32Mbit part
  48   //
  49   {
  50     SPI_W25X32_ID1,
  51     SF_DEVICE_ID0_W25QXX,
  52     SF_DEVICE_ID1_W25Q32,
  53     {
  54       SPI_COMMAND_WRITE_ENABLE,
  55       SPI_COMMAND_WRITE_S_EN
  56     },
  57     {
  58       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},
  59       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},
  60       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
  61       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
  62       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},
  63       {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
  64       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
  65       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
  66     },
  67     0x400000 - FLASH_SIZE, // BIOS Start Offset
  68     FLASH_SIZE   // BIOS image size in flash
  69   },
  70   //
  71   // Winbond 32Mbit part
  72   //
  73   {
  74     SPI_W25X32_ID1,
  75     SPI_W25X32_ID2,
  76     SPI_W25X32_ID3,
  77     {
  78       SPI_COMMAND_WRITE_ENABLE,
  79       SPI_COMMAND_WRITE_S_EN
  80     },
  81     {
  82       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle33MHz, EnumSpiOperationJedecId},
  83       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle33MHz, EnumSpiOperationOther},
  84       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},
  85       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},
  86       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle33MHz, EnumSpiOperationReadData},
  87       {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle33MHz, EnumSpiOperationErase_4K_Byte},
  88       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle33MHz, EnumSpiOperationReadStatus},
  89       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}
  90     },
  91     0x400000 - FLASH_SIZE, // BIOS Start Offset
  92     FLASH_SIZE   // BIOS image size in flash
  93   },
  94   //
  95   // Atmel 32Mbit part
  96   //
  97   {
  98     SPI_AT26DF321_ID1,
  99     SPI_AT26DF321_ID2,  // issue: byte 2 identifies family/density for Atmel
 100     SPI_AT26DF321_ID3,
 101     {
 102       SPI_COMMAND_WRITE_ENABLE,
 103       SPI_COMMAND_WRITE_S_EN
 104     },
 105     {
 106       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle33MHz, EnumSpiOperationJedecId},
 107       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle33MHz, EnumSpiOperationOther},
 108       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},
 109       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},
 110       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle33MHz, EnumSpiOperationReadData},
 111       {EnumSpiOpcodeWrite,       SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},
 112       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle33MHz, EnumSpiOperationReadStatus},
 113       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}
 114     },
 115     0x400000 - FLASH_SIZE, // BIOS Start Offset
 116     FLASH_SIZE   // BIOS image size in flash
 117   },
 118
 119   //
 120   // Intel 32Mbit part bottom boot
 121   //
 122   {
 123     SPI_QH25F320_ID1,
 124     SPI_QH25F320_ID2,
 125     SPI_QH25F320_ID3,
 126     {
 127       SPI_COMMAND_WRITE_ENABLE,
 128       SPI_COMMAND_WRITE_ENABLE
 129     },
 130     {
 131       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle33MHz, EnumSpiOperationJedecId},
 132       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle33MHz, EnumSpiOperationOther},
 133       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},
 134       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},
 135       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle33MHz, EnumSpiOperationReadData},
 136       {EnumSpiOpcodeWrite,       SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},
 137       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle33MHz, EnumSpiOperationReadStatus},
 138       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}
 139     },
 140     0,           // BIOS Start Offset
 141     FLASH_SIZE   // BIOS image size in flash
 142   },
 143   //
 144   // SST 64Mbit part
 145   //
 146   {
 147     SPI_SST25VF080B_ID1,      // VendorId
 148     SF_DEVICE_ID0_25VF064C,   // DeviceId 0
 149     SF_DEVICE_ID1_25VF064C,   // DeviceId 1
 150     {
 151       SPI_COMMAND_WRITE_ENABLE,
 152       SPI_COMMAND_WRITE_S_EN
 153     },
 154     {
 155       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},
 156       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},
 157       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
 158       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
 159       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},
 160       {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
 161       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
 162       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
 163     },
 164     0x800000 - FLASH_SIZE,          // BIOS Start Offset
 165     FLASH_SIZE   // BIOS image size in flash
 166   },
 167   //
 168   // NUMONYX 64Mbit part
 169   //
 170   {
 171     SF_VENDOR_ID_NUMONYX,     // VendorId
 172     SF_DEVICE_ID0_M25PX64,    // DeviceId 0
 173     SF_DEVICE_ID1_M25PX64,    // DeviceId 1
 174     {
 175       SPI_COMMAND_WRITE_ENABLE,
 176       SPI_COMMAND_WRITE_S_EN
 177     },
 178     {
 179       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},
 180       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},
 181       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
 182       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
 183       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},
 184       {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
 185       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
 186       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
 187     },
 188     0x800000 - FLASH_SIZE,          // BIOS Start Offset
 189     FLASH_SIZE   // BIOS image size in flash
 190   },
 191   //
 192   // Atmel 64Mbit part
 193   //
 194   {
 195     SF_VENDOR_ID_ATMEL,       // VendorId
 196     SF_DEVICE_ID0_AT25DF641,  // DeviceId 0
 197     SF_DEVICE_ID1_AT25DF641,  // DeviceId 1
 198     {
 199       SPI_COMMAND_WRITE_ENABLE,
 200       SPI_COMMAND_WRITE_S_EN
 201     },
 202     {
 203       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},
 204       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},
 205       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
 206       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
 207       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},
 208       {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
 209       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
 210       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
 211     },
 212     0x800000 - FLASH_SIZE,          // BIOS Start Offset
 213     FLASH_SIZE   // BIOS image size in flash
 214   },
 215
 216   //
 217   // Spansion 64Mbit part
 218   //
 219   {
 220     SF_VENDOR_ID_SPANSION,       // VendorId
 221     SF_DEVICE_ID0_S25FL064K,  // DeviceId 0
 222     SF_DEVICE_ID1_S25FL064K,  // DeviceId 1
 223     {
 224       SPI_COMMAND_WRITE_ENABLE,
 225       SPI_COMMAND_WRITE_S_EN
 226     },
 227     {
 228       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},
 229       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},
 230       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
 231       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
 232       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},
 233       {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
 234       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
 235       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
 236     },
 237     0x800000 - FLASH_SIZE,          // BIOS Start Offset
 238     FLASH_SIZE   // BIOS image size in flash
 239   },
 240
 241   //
 242   // Macronix 64Mbit part bottom boot
 243   //
 244   {
 245     SF_VENDOR_ID_MX,          // VendorId
 246     SF_DEVICE_ID0_25L6405D,   // DeviceId 0
 247     SF_DEVICE_ID1_25L6405D,   // DeviceId 1
 248     {
 249       SPI_COMMAND_WRITE_ENABLE,
 250       SPI_COMMAND_WRITE_S_EN
 251     },
 252     {
 253       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},
 254       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},
 255       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
 256       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
 257       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},
 258       {EnumSpiOpcodeWrite,       SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte},
 259       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
 260       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
 261     },
 262     0x800000 - FLASH_SIZE,          // BIOS Start Offset
 263     FLASH_SIZE   // BIOS image size in flash
 264   },
 265   //
 266   // Winbond 64Mbit part bottom boot
 267   //
 268   {
 269     SPI_W25X64_ID1,
 270     SF_DEVICE_ID0_W25QXX,
 271     SF_DEVICE_ID1_W25Q64,
 272     {
 273       SPI_COMMAND_WRITE_ENABLE,
 274       SPI_COMMAND_WRITE_S_EN
 275     },
 276     {
 277       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},
 278       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},
 279       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
 280       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
 281       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},
 282       {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
 283       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
 284       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
 285     },
 286     0x800000 - FLASH_SIZE,          // BIOS Start Offset
 287     FLASH_SIZE   // BIOS image size in flash
 288   },
 289   //
 290   // Winbond 64Mbit part bottom boot
 291   //
 292   {
 293     SPI_W25X64_ID1,
 294     SPI_W25X64_ID2,
 295     SPI_W25X64_ID3,
 296     {
 297       SPI_COMMAND_WRITE_ENABLE,
 298       SPI_COMMAND_WRITE_S_EN
 299     },
 300     {
 301       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},
 302       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},
 303       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
 304       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
 305       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},
 306       {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
 307       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
 308       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
 309     },
 310     0x800000 - FLASH_SIZE,          // BIOS Start Offset
 311     FLASH_SIZE   // BIOS image size in flash
 312   },
 313   //
 314   // Intel 64Mbit part bottom boot
 315   //
 316   {
 317     SPI_QH25F640_ID1,
 318     SPI_QH25F640_ID2,
 319     SPI_QH25F640_ID3,
 320     {
 321       SPI_COMMAND_WRITE_ENABLE,
 322       SPI_COMMAND_WRITE_S_EN
 323     },
 324     {
 325       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle33MHz, EnumSpiOperationJedecId},
 326       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle33MHz, EnumSpiOperationOther},
 327       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},
 328       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},
 329       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle33MHz, EnumSpiOperationReadData},
 330       {EnumSpiOpcodeWrite,       SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},
 331       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle33MHz, EnumSpiOperationReadStatus},
 332       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}
 333     },
 334     0x800000 - FLASH_SIZE,          // BIOS Start Offset
 335     FLASH_SIZE   // BIOS image size in flash
 336   }
 337 };