2 Memory controller configuration.
4 Copyright (c) 2013-2015 Intel Corporation.
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #ifndef __DDR_MEMORY_CONTROLLER_H__
16 #define __DDR_MEMORY_CONTROLLER_H__
19 // DDR timing data definitions.
20 // These are used to create bitmaps of valid timing configurations.
23 #define DUAL_CHANNEL_DDR_TIMING_DATA_FREQUENCY_UNKNOWN 0xFF
24 #define DUAL_CHANNEL_DDR_TIMING_DATA_REFRESH_RATE_UNKNOWN 0xFF
26 #define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_20 0x01
27 #define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_25 0x00
28 #define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_30 0x02
29 #define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_ALL 0x03
32 #define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_02 0x02
33 #define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_03 0x01
34 #define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_04 0x00
35 #define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_ALL 0x03
37 #define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_02 0x02
38 #define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_03 0x01
39 #define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_04 0x00
40 #define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_ALL 0x03
42 #define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_05 0x05
43 #define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_06 0x04
44 #define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_07 0x03
45 #define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_08 0x02
46 #define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_09 0x01
47 #define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_10 0x00
48 #define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_ALL 0x07
50 #define DUAL_CHANNEL_DDR_DATA_TYPE_REGISTERED 0x01
51 #define DUAL_CHANNEL_DDR_DATA_TYPE_UNREGISTERED 0x02
52 #define DUAL_CHANNEL_DDR_DATA_TYPE_BUFFERED 0x04
53 #define DUAL_CHANNEL_DDR_DATA_TYPE_UNBUFFERED 0x08
54 #define DUAL_CHANNEL_DDR_DATA_TYPE_SDR 0x10
55 #define DUAL_CHANNEL_DDR_DATA_TYPE_DDR 0x20
59 // Maximum number of SDRAM channels supported by the memory controller
61 #define MAX_CHANNELS 1
64 // Maximum number of DIMM sockets supported by the memory controller
69 // Maximum number of sides supported per DIMM
74 // Maximum number of "Socket Sets", where a "Socket Set is a set of matching
75 // DIMM's from the various channels
77 #define MAX_SOCKET_SETS 2
80 // Maximum number of rows supported by the memory controller
82 #define MAX_ROWS (MAX_SIDES * MAX_SOCKETS)
85 // Maximum number of memory ranges supported by the memory controller
87 #define MAX_RANGES (MAX_ROWS + 5)
90 // Maximum Number of Log entries
92 #define MEMORY_LOG_MAX_INDEX 16
95 typedef struct _MEMORY_LOG_ENTRY
{
96 EFI_STATUS_CODE_VALUE Event
;
97 EFI_STATUS_CODE_TYPE Severity
;
101 typedef struct _MEMORY_LOG
{
103 MEMORY_LOG_ENTRY Entry
[MEMORY_LOG_MAX_INDEX
];
111 #define DUAL_CHANNEL_DDR_ECC_TYPE_NONE 0x01 // No error checking
112 #define DUAL_CHANNEL_DDR_ECC_TYPE_EC 0x02 // Error checking only
113 #define DUAL_CHANNEL_DDR_ECC_TYPE_SECC 0x04 // Software Scrubbing ECC
114 #define DUAL_CHANNEL_DDR_ECC_TYPE_HECC 0x08 // Hardware Scrubbing ECC
115 #define DUAL_CHANNEL_DDR_ECC_TYPE_CKECC 0x10 // Chip Kill ECC
118 // Row configuration status values
120 #define DUAL_CHANNEL_DDR_ROW_CONFIG_SUCCESS 0x00 // No error
121 #define DUAL_CHANNEL_DDR_ROW_CONFIG_UNKNOWN 0x01 // Pattern mismatch, no memory
122 #define DUAL_CHANNEL_DDR_ROW_CONFIG_UNSUPPORTED 0x02 // Memory type not supported
123 #define DUAL_CHANNEL_DDR_ROW_CONFIG_ADDRESS_ERROR 0x03 // Row/Col/Bnk mismatch
124 #define DUAL_CHANNEL_DDR_ROW_CONFIG_ECC_ERROR 0x04 // Received ECC error
125 #define DUAL_CHANNEL_DDR_ROW_CONFIG_NOT_PRESENT 0x05 // Row is not present
126 #define DUAL_CHANNEL_DDR_ROW_CONFIG_DISABLED 0x06 // Row is disabled
130 // Memory range types
133 DualChannelDdrMainMemory
,
134 DualChannelDdrSmramCacheable
,
135 DualChannelDdrSmramNonCacheable
,
136 DualChannelDdrGraphicsMemoryCacheable
,
137 DualChannelDdrGraphicsMemoryNonCacheable
,
138 DualChannelDdrReservedMemory
,
139 DualChannelDdrMaxMemoryRangeType
140 } DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE
;
143 // Memory map range information
146 EFI_PHYSICAL_ADDRESS PhysicalAddress
;
147 EFI_PHYSICAL_ADDRESS CpuAddress
;
148 EFI_PHYSICAL_ADDRESS RangeLength
;
149 DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE Type
;
150 } DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE
;
152 unsigned dramType
:1; /**< Type: 0 = RESERVED; 1 = DDR2 */
153 unsigned dramWidth
:1; /**< Width: 0 = x8; 1 = x16 */
154 unsigned dramDensity
:2; /**< Density: 00b = 2Gb; 01b = 1Gb; 10b = 512Mb; 11b = 256Mb */
155 unsigned dramSpeed
:1; /**< Speed Grade: 0 = RESERVED; 1 = 800MT/s;*/
156 unsigned dramTimings
:3; /**< Timings: 4-4-4, 5-5-5, 6-6-6 */
157 unsigned dramRanks
:1; /**< Ranks: 0 = Single Rank; 1 = Dual Rank */
158 } DramGeometry
; /**< DRAM Geometry Descriptor */
160 typedef union _RegDRP
{
163 unsigned rank0Enabled
:1; /**< Rank 0 Enable */
164 unsigned rank0DevWidth
:2; /**< DRAM Device Width (x8,x16) */
165 unsigned rank0DevDensity
:2; /**< DRAM Device Density (256Mb,512Mb,1Gb,2Gb) */
166 unsigned reserved2
:1;
167 unsigned rank1Enabled
:1; /**< Rank 1 Enable */
168 unsigned reserved3
:5;
169 unsigned dramType
:1; /**< DRAM Type (0=DDR2) */
170 unsigned reserved4
:5;
171 unsigned reserved5
:14;
173 } RegDRP
; /**< DRAM Rank Population and Interface Register */
179 unsigned dramFrequency
:3; /**< DRAM Frequency (000=RESERVED,010=667,011=800) */
180 unsigned tRP
:2; /**< Precharge to Activate Delay (3,4,5,6) */
181 unsigned reserved1
:1;
182 unsigned tRCD
:2; /**< Activate to CAS Delay (3,4,5,6) */
183 unsigned reserved2
:1;
184 unsigned tCL
:2; /**< CAS Latency (3,4,5,6) */
185 unsigned reserved3
:21;
187 } RegDTR0
; /**< DRAM Timing Register 0 */
192 unsigned tWRRD_dly
:2; /**< Additional Write to Read Delay (0,1,2,3) */
193 unsigned reserved1
:1;
194 unsigned tRDWR_dly
:2; /**< Additional Read to Write Delay (0,1,2,3) */
195 unsigned reserved2
:1;
196 unsigned tRDRD_dr_dly
:1; /**< Additional Read to Read Delay (1,2) */
197 unsigned reserved3
:1;
198 unsigned tRD_dly
:3; /**< Additional Read Data Sampling Delay (0-7) */
199 unsigned reserved4
:1;
200 unsigned tRCVEN_halfclk_dly
:4; /**< Additional RCVEN Half Clock Delay Control */
201 unsigned reserved5
:1;
202 unsigned readDqDelay
:2; /**< Read DQ Delay */
203 unsigned reserved6
:13;
205 } RegDTR1
; /**< DRAM Timing Register 1 */
210 unsigned ckStaticDisable
:1; /**< CK/CK# Static Disable */
211 unsigned reserved1
:3;
212 unsigned ckeStaticDisable
:2; /**< CKE Static Disable */
213 unsigned reserved2
:8;
214 unsigned refreshPeriod
:2; /**< Refresh Period (disabled,128clks,3.9us,7.8us) */
215 unsigned refreshQueueDepth
:2; /**< Refresh Queue Depth (1,2,4,8) */
216 unsigned reserved5
:13;
217 unsigned initComplete
:1; /**< Initialization Complete */
222 // MRC Data Structure
235 UINT8 refreshPeriod
; /**< Placeholder for the chosen refresh
236 * period. This value will NOT be
237 * programmed into DCO until all
238 * initialization is done.
240 UINT8 ddr2Odt
; /**< 0 = Disabled, 1 = 75 ohm, 2 = 150ohm, 3 = 50ohm */
241 UINT8 sku
; /**< Detected QuarkNcSocId SKU */
242 UINT8 capabilities
; /**< Capabilities Available on this part */
243 UINT8 state
; /**< NORMAL_BOOT, S3_RESUME */
244 UINT32 memSize
; /**< Memory size */
245 UINT16 pmBase
; /**< PM Base */
246 UINT16 mrcVersion
; /**< MRC Version */
247 UINT32 hecbase
; /**< HECBASE shifted left 16 bits */
248 DramGeometry geometry
; /**< DRAM Geometry */
249 } MRC_DATA_STRUCTURE
; /**< QuarkNcSocId Memory Parameters for MRC */
251 typedef struct _EFI_MEMINIT_CONFIG_DATA
{
252 MRC_DATA_STRUCTURE MrcData
;
253 } EFI_MEMINIT_CONFIG_DATA
;