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git.proxmox.com Git - mirror_edk2.git/blob - QuarkSocPkg/QuarkNorthCluster/Include/Library/QNCAccessLib.h
290902c67feb8cbdfde0fb8cb64f88c646d6f4e3
2 Library functions for Setting QNC internal network port
4 Copyright (c) 2013-2015 Intel Corporation.
6 SPDX-License-Identifier: BSD-2-Clause-Patent
10 #ifndef __QNC_ACCESS_LIB_H__
11 #define __QNC_ACCESS_LIB_H__
13 #include <IntelQNCRegs.h>
15 #define MESSAGE_READ_DW(Port, Reg) \
16 (UINT32)((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
18 #define MESSAGE_WRITE_DW(Port, Reg) \
19 (UINT32)((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
21 #define ALT_MESSAGE_READ_DW(Port, Reg) \
22 (UINT32)((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
24 #define ALT_MESSAGE_WRITE_DW(Port, Reg) \
25 (UINT32)((QUARK_ALT_OPCODE_WRITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
27 #define MESSAGE_IO_READ_DW(Port, Reg) \
28 (UINT32)((QUARK_OPCODE_IO_READ << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
30 #define MESSAGE_IO_WRITE_DW(Port, Reg) \
31 (UINT32)((QUARK_OPCODE_IO_WRITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
33 #define MESSAGE_SHADOW_DW(Port, Reg) \
34 (UINT32)((QUARK_DRAM_BASE_ADDR_READY << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
38 Read required data from QNC internal message network
48 Write prepared data into QNC internal message network.
60 Read required data from QNC internal message network
70 Write prepared data into QNC internal message network.
82 Read required data from QNC internal message network
92 Write prepared data into QNC internal message network.
104 This is for the special consideration for QNC MMIO write, as required by FWG,
105 a reading must be performed after MMIO writing to ensure the expected write
106 is processed and data is flushed into chipset
113 QNC_MEM_IO_WIDTH Width
,
133 UINT32 ImrBaseOffset
,
157 QncGetPciExpressBaseAddress (