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1 /** @file
2 Library functions for Setting QNC internal network port
3
4 Copyright (c) 2013-2015 Intel Corporation.
5
6 SPDX-License-Identifier: BSD-2-Clause-Patent
7
8 **/
9
10 #ifndef __QNC_ACCESS_LIB_H__
11 #define __QNC_ACCESS_LIB_H__
12
13 #include <IntelQNCRegs.h>
14
15 #define MESSAGE_READ_DW(Port, Reg) \
16 (UINT32)((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
17
18 #define MESSAGE_WRITE_DW(Port, Reg) \
19 (UINT32)((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
20
21 #define ALT_MESSAGE_READ_DW(Port, Reg) \
22 (UINT32)((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
23
24 #define ALT_MESSAGE_WRITE_DW(Port, Reg) \
25 (UINT32)((QUARK_ALT_OPCODE_WRITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
26
27 #define MESSAGE_IO_READ_DW(Port, Reg) \
28 (UINT32)((QUARK_OPCODE_IO_READ << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
29
30 #define MESSAGE_IO_WRITE_DW(Port, Reg) \
31 (UINT32)((QUARK_OPCODE_IO_WRITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
32
33 #define MESSAGE_SHADOW_DW(Port, Reg) \
34 (UINT32)((QUARK_DRAM_BASE_ADDR_READY << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0)
35
36
37 /**
38 Read required data from QNC internal message network
39 **/
40 UINT32
41 EFIAPI
42 QNCPortRead(
43 UINT8 Port,
44 UINT32 RegAddress
45 );
46
47 /**
48 Write prepared data into QNC internal message network.
49
50 **/
51 VOID
52 EFIAPI
53 QNCPortWrite (
54 UINT8 Port,
55 UINT32 RegAddress,
56 UINT32 WriteValue
57 );
58
59 /**
60 Read required data from QNC internal message network
61 **/
62 UINT32
63 EFIAPI
64 QNCAltPortRead(
65 UINT8 Port,
66 UINT32 RegAddress
67 );
68
69 /**
70 Write prepared data into QNC internal message network.
71
72 **/
73 VOID
74 EFIAPI
75 QNCAltPortWrite (
76 UINT8 Port,
77 UINT32 RegAddress,
78 UINT32 WriteValue
79 );
80
81 /**
82 Read required data from QNC internal message network
83 **/
84 UINT32
85 EFIAPI
86 QNCPortIORead(
87 UINT8 Port,
88 UINT32 RegAddress
89 );
90
91 /**
92 Write prepared data into QNC internal message network.
93
94 **/
95 VOID
96 EFIAPI
97 QNCPortIOWrite (
98 UINT8 Port,
99 UINT32 RegAddress,
100 UINT32 WriteValue
101 );
102
103 /**
104 This is for the special consideration for QNC MMIO write, as required by FWG,
105 a reading must be performed after MMIO writing to ensure the expected write
106 is processed and data is flushed into chipset
107
108 **/
109 RETURN_STATUS
110 EFIAPI
111 QNCMmIoWrite (
112 UINT32 MmIoAddress,
113 QNC_MEM_IO_WIDTH Width,
114 UINT32 DataNumber,
115 VOID *pData
116 );
117
118 UINT32
119 EFIAPI
120 QncHsmmcRead (
121 VOID
122 );
123
124 VOID
125 EFIAPI
126 QncHsmmcWrite (
127 UINT32 WriteValue
128 );
129
130 VOID
131 EFIAPI
132 QncImrWrite (
133 UINT32 ImrBaseOffset,
134 UINT32 ImrLow,
135 UINT32 ImrHigh,
136 UINT32 ImrReadMask,
137 UINT32 ImrWriteMask
138 );
139
140 VOID
141 EFIAPI
142 QncIClkAndThenOr (
143 UINT32 RegAddress,
144 UINT32 AndValue,
145 UINT32 OrValue
146 );
147
148 VOID
149 EFIAPI
150 QncIClkOr (
151 UINT32 RegAddress,
152 UINT32 OrValue
153 );
154
155 UINTN
156 EFIAPI
157 QncGetPciExpressBaseAddress (
158 VOID
159 );
160
161 #endif