QuarkSocPkg/QuarkNorthCluster/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c

   1 /** @file
   2 The Quark CPU specific programming for PiSmmCpuDxeSmm module.
   3
   4 Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
   5 SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7 **/
   8
   9 #include <PiSmm.h>
  10 #include <Library/SmmCpuFeaturesLib.h>
  11 #include <Register/SmramSaveStateMap.h>
  12 #include <Library/BaseLib.h>
  13 #include <Library/DebugLib.h>
  14 #include <Library/QNCAccessLib.h>
  15
  16 #define  EFI_MSR_SMRR_PHYS_MASK_VALID          BIT11
  17 #define  EFI_MSR_SMRR_MASK                     0xFFFFF000
  18
  19 /**
  20   Called during the very first SMI into System Management Mode to initialize
  21   CPU features, including SMBASE, for the currently executing CPU.  Since this
  22   is the first SMI, the SMRAM Save State Map is at the default address of
  23   SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET.  The currently executing
  24   CPU is specified by CpuIndex and CpuIndex can be used to access information
  25   about the currently executing CPU in the ProcessorInfo array and the
  26   HotPlugCpuData data structure.
  27
  28   @param[in] CpuIndex        The index of the CPU to initialize.  The value
  29                              must be between 0 and the NumberOfCpus field in
  30                              the System Management System Table (SMST).
  31   @param[in] IsMonarch       TRUE if the CpuIndex is the index of the CPU that
  32                              was elected as monarch during System Management
  33                              Mode initialization.
  34                              FALSE if the CpuIndex is not the index of the CPU
  35                              that was elected as monarch during System
  36                              Management Mode initialization.
  37   @param[in] ProcessorInfo   Pointer to an array of EFI_PROCESSOR_INFORMATION
  38                              structures.  ProcessorInfo[CpuIndex] contains the
  39                              information for the currently executing CPU.
  40   @param[in] CpuHotPlugData  Pointer to the CPU_HOT_PLUG_DATA structure that
  41                              contains the ApidId and SmBase arrays.
  42 **/
  43 VOID
  44 EFIAPI
  45 SmmCpuFeaturesInitializeProcessor (
  46   IN UINTN                      CpuIndex,
  47   IN BOOLEAN                    IsMonarch,
  48   IN EFI_PROCESSOR_INFORMATION  *ProcessorInfo,
  49   IN CPU_HOT_PLUG_DATA          *CpuHotPlugData
  50   )
  51 {
  52   SMRAM_SAVE_STATE_MAP  *CpuState;
  53
  54   //
  55   // Configure SMBASE.
  56   //
  57   CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
  58   CpuState->x86.SMBASE = CpuHotPlugData->SmBase[CpuIndex];
  59
  60   //
  61   // SMRR size cannot be less than 4-KBytes
  62   // SMRR size must be of length 2^n
  63   // SMRR base alignment cannot be less than SMRR length
  64   //
  65   if ((CpuHotPlugData->SmrrSize < SIZE_4KB) ||
  66       (CpuHotPlugData->SmrrSize != GetPowerOfTwo32 (CpuHotPlugData->SmrrSize)) ||
  67       ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase)) {
  68     DEBUG ((EFI_D_ERROR, "SMM Base/Size does not meet alignment/size requirement!\n"));
  69     CpuDeadLoop ();
  70   }
  71
  72   //
  73   // Use QNC to initialize SMRR on Quark
  74   //
  75   QNCPortWrite(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSBASE, CpuHotPlugData->SmrrBase);
  76   QNCPortWrite(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK, (~(CpuHotPlugData->SmrrSize - 1) & EFI_MSR_SMRR_MASK) | EFI_MSR_SMRR_PHYS_MASK_VALID);
  77 }
  78
  79 /**
  80   This function updates the SMRAM save state on the currently executing CPU
  81   to resume execution at a specific address after an RSM instruction.  This
  82   function must evaluate the SMRAM save state to determine the execution mode
  83   the RSM instruction resumes and update the resume execution address with
  84   either NewInstructionPointer32 or NewInstructionPoint.  The auto HALT restart
  85   flag in the SMRAM save state must always be cleared.  This function returns
  86   the value of the instruction pointer from the SMRAM save state that was
  87   replaced.  If this function returns 0, then the SMRAM save state was not
  88   modified.
  89
  90   This function is called during the very first SMI on each CPU after
  91   SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode
  92   to signal that the SMBASE of each CPU has been updated before the default
  93   SMBASE address is used for the first SMI to the next CPU.
  94
  95   @param[in] CpuIndex                 The index of the CPU to hook.  The value
  96                                       must be between 0 and the NumberOfCpus
  97                                       field in the System Management System Table
  98                                       (SMST).
  99   @param[in] CpuState                 Pointer to SMRAM Save State Map for the
 100                                       currently executing CPU.
 101   @param[in] NewInstructionPointer32  Instruction pointer to use if resuming to
 102                                       32-bit execution mode from 64-bit SMM.
 103   @param[in] NewInstructionPointer    Instruction pointer to use if resuming to
 104                                       same execution mode as SMM.
 105
 106   @retval 0    This function did modify the SMRAM save state.
 107   @retval > 0  The original instruction pointer value from the SMRAM save state
 108                before it was replaced.
 109 **/
 110 UINT64
 111 EFIAPI
 112 SmmCpuFeaturesHookReturnFromSmm (
 113   IN UINTN                 CpuIndex,
 114   IN SMRAM_SAVE_STATE_MAP  *CpuState,
 115   IN UINT64                NewInstructionPointer32,
 116   IN UINT64                NewInstructionPointer
 117   )
 118 {
 119   return 0;
 120 }
 121
 122 /**
 123   Hook point in normal execution mode that allows the one CPU that was elected
 124   as monarch during System Management Mode initialization to perform additional
 125   initialization actions immediately after all of the CPUs have processed their
 126   first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE
 127   into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().
 128 **/
 129 VOID
 130 EFIAPI
 131 SmmCpuFeaturesSmmRelocationComplete (
 132   VOID
 133   )
 134 {
 135 }
 136
 137 /**
 138   Return the size, in bytes, of a custom SMI Handler in bytes.  If 0 is
 139   returned, then a custom SMI handler is not provided by this library,
 140   and the default SMI handler must be used.
 141
 142   @retval 0    Use the default SMI handler.
 143   @retval > 0  Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler()
 144                The caller is required to allocate enough SMRAM for each CPU to
 145                support the size of the custom SMI handler.
 146 **/
 147 UINTN
 148 EFIAPI
 149 SmmCpuFeaturesGetSmiHandlerSize (
 150   VOID
 151   )
 152 {
 153   return 0;
 154 }
 155
 156 /**
 157   Install a custom SMI handler for the CPU specified by CpuIndex.  This function
 158   is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater
 159   than zero and is called by the CPU that was elected as monarch during System
 160   Management Mode initialization.
 161
 162   @param[in] CpuIndex   The index of the CPU to install the custom SMI handler.
 163                         The value must be between 0 and the NumberOfCpus field
 164                         in the System Management System Table (SMST).
 165   @param[in] SmBase     The SMBASE address for the CPU specified by CpuIndex.
 166   @param[in] SmiStack   The stack to use when an SMI is processed by the
 167                         the CPU specified by CpuIndex.
 168   @param[in] StackSize  The size, in bytes, if the stack used when an SMI is
 169                         processed by the CPU specified by CpuIndex.
 170   @param[in] GdtBase    The base address of the GDT to use when an SMI is
 171                         processed by the CPU specified by CpuIndex.
 172   @param[in] GdtSize    The size, in bytes, of the GDT used when an SMI is
 173                         processed by the CPU specified by CpuIndex.
 174   @param[in] IdtBase    The base address of the IDT to use when an SMI is
 175                         processed by the CPU specified by CpuIndex.
 176   @param[in] IdtSize    The size, in bytes, of the IDT used when an SMI is
 177                         processed by the CPU specified by CpuIndex.
 178   @param[in] Cr3        The base address of the page tables to use when an SMI
 179                         is processed by the CPU specified by CpuIndex.
 180 **/
 181 VOID
 182 EFIAPI
 183 SmmCpuFeaturesInstallSmiHandler (
 184   IN UINTN   CpuIndex,
 185   IN UINT32  SmBase,
 186   IN VOID    *SmiStack,
 187   IN UINTN   StackSize,
 188   IN UINTN   GdtBase,
 189   IN UINTN   GdtSize,
 190   IN UINTN   IdtBase,
 191   IN UINTN   IdtSize,
 192   IN UINT32  Cr3
 193   )
 194 {
 195 }
 196
 197 /**
 198   Determines if MTRR registers must be configured to set SMRAM cache-ability
 199   when executing in System Management Mode.
 200
 201   @retval TRUE   MTRR registers must be configured to set SMRAM cache-ability.
 202   @retval FALSE  MTRR registers do not need to be configured to set SMRAM
 203                    cache-ability.
 204 **/
 205 BOOLEAN
 206 EFIAPI
 207 SmmCpuFeaturesNeedConfigureMtrrs (
 208   VOID
 209   )
 210 {
 211   return TRUE;
 212 }
 213
 214 /**
 215   Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
 216   returns TRUE.
 217 **/
 218 VOID
 219 EFIAPI
 220 SmmCpuFeaturesDisableSmrr (
 221   VOID
 222   )
 223 {
 224   //
 225   // Use QNC to disable SMRR on Quark
 226   //
 227   QNCPortWrite(
 228     QUARK_NC_HOST_BRIDGE_SB_PORT_ID,
 229     QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK,
 230     QNCPortRead(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK) & ~EFI_MSR_SMRR_PHYS_MASK_VALID
 231     );
 232 }
 233
 234 /**
 235   Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
 236   returns TRUE.
 237 **/
 238 VOID
 239 EFIAPI
 240 SmmCpuFeaturesReenableSmrr (
 241   VOID
 242   )
 243 {
 244   //
 245   // Use QNC to enable SMRR on Quark
 246   //
 247   QNCPortWrite(
 248     QUARK_NC_HOST_BRIDGE_SB_PORT_ID,
 249     QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK,
 250     QNCPortRead(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK) | EFI_MSR_SMRR_PHYS_MASK_VALID
 251     );
 252 }
 253
 254 /**
 255   Processor specific hook point each time a CPU enters System Management Mode.
 256
 257   @param[in] CpuIndex  The index of the CPU that has entered SMM.  The value
 258                        must be between 0 and the NumberOfCpus field in the
 259                        System Management System Table (SMST).
 260 **/
 261 VOID
 262 EFIAPI
 263 SmmCpuFeaturesRendezvousEntry (
 264   IN UINTN  CpuIndex
 265   )
 266 {
 267 }
 268
 269 /**
 270   Processor specific hook point each time a CPU exits System Management Mode.
 271
 272   @param[in] CpuIndex  The index of the CPU that is exiting SMM.  The value must
 273                        be between 0 and the NumberOfCpus field in the System
 274                        Management System Table (SMST).
 275 **/
 276 VOID
 277 EFIAPI
 278 SmmCpuFeaturesRendezvousExit (
 279   IN UINTN  CpuIndex
 280   )
 281 {
 282 }
 283
 284 /**
 285   Check to see if an SMM register is supported by a specified CPU.
 286
 287   @param[in] CpuIndex  The index of the CPU to check for SMM register support.
 288                        The value must be between 0 and the NumberOfCpus field
 289                        in the System Management System Table (SMST).
 290   @param[in] RegName   Identifies the SMM register to check for support.
 291
 292   @retval TRUE   The SMM register specified by RegName is supported by the CPU
 293                  specified by CpuIndex.
 294   @retval FALSE  The SMM register specified by RegName is not supported by the
 295                  CPU specified by CpuIndex.
 296 **/
 297 BOOLEAN
 298 EFIAPI
 299 SmmCpuFeaturesIsSmmRegisterSupported (
 300   IN UINTN         CpuIndex,
 301   IN SMM_REG_NAME  RegName
 302   )
 303 {
 304   return FALSE;
 305 }
 306
 307 /**
 308   Returns the current value of the SMM register for the specified CPU.
 309   If the SMM register is not supported, then 0 is returned.
 310
 311   @param[in] CpuIndex  The index of the CPU to read the SMM register.  The
 312                        value must be between 0 and the NumberOfCpus field in
 313                        the System Management System Table (SMST).
 314   @param[in] RegName   Identifies the SMM register to read.
 315
 316   @return  The value of the SMM register specified by RegName from the CPU
 317            specified by CpuIndex.
 318 **/
 319 UINT64
 320 EFIAPI
 321 SmmCpuFeaturesGetSmmRegister (
 322   IN UINTN         CpuIndex,
 323   IN SMM_REG_NAME  RegName
 324   )
 325 {
 326   return 0;
 327 }
 328
 329 /**
 330   Sets the value of an SMM register on a specified CPU.
 331   If the SMM register is not supported, then no action is performed.
 332
 333   @param[in] CpuIndex  The index of the CPU to write the SMM register.  The
 334                        value must be between 0 and the NumberOfCpus field in
 335                        the System Management System Table (SMST).
 336   @param[in] RegName   Identifies the SMM register to write.
 337                        registers are read-only.
 338   @param[in] Value     The value to write to the SMM register.
 339 **/
 340 VOID
 341 EFIAPI
 342 SmmCpuFeaturesSetSmmRegister (
 343   IN UINTN         CpuIndex,
 344   IN SMM_REG_NAME  RegName,
 345   IN UINT64        Value
 346   )
 347 {
 348 }
 349
 350 /**
 351   Read an SMM Save State register on the target processor.  If this function
 352   returns EFI_UNSUPPORTED, then the caller is responsible for reading the
 353   SMM Save Sate register.
 354
 355   @param[in]  CpuIndex  The index of the CPU to read the SMM Save State.  The
 356                         value must be between 0 and the NumberOfCpus field in
 357                         the System Management System Table (SMST).
 358   @param[in]  Register  The SMM Save State register to read.
 359   @param[in]  Width     The number of bytes to read from the CPU save state.
 360   @param[out] Buffer    Upon return, this holds the CPU register value read
 361                         from the save state.
 362
 363   @retval EFI_SUCCESS           The register was read from Save State.
 364   @retval EFI_INVALID_PARAMTER  Buffer is NULL.
 365   @retval EFI_UNSUPPORTED       This function does not support reading Register.
 366
 367 **/
 368 EFI_STATUS
 369 EFIAPI
 370 SmmCpuFeaturesReadSaveStateRegister (
 371   IN  UINTN                        CpuIndex,
 372   IN  EFI_SMM_SAVE_STATE_REGISTER  Register,
 373   IN  UINTN                        Width,
 374   OUT VOID                         *Buffer
 375   )
 376 {
 377   return EFI_UNSUPPORTED;
 378 }
 379
 380 /**
 381   Writes an SMM Save State register on the target processor.  If this function
 382   returns EFI_UNSUPPORTED, then the caller is responsible for writing the
 383   SMM Save Sate register.
 384
 385   @param[in] CpuIndex  The index of the CPU to write the SMM Save State.  The
 386                        value must be between 0 and the NumberOfCpus field in
 387                        the System Management System Table (SMST).
 388   @param[in] Register  The SMM Save State register to write.
 389   @param[in] Width     The number of bytes to write to the CPU save state.
 390   @param[in] Buffer    Upon entry, this holds the new CPU register value.
 391
 392   @retval EFI_SUCCESS           The register was written to Save State.
 393   @retval EFI_INVALID_PARAMTER  Buffer is NULL.
 394   @retval EFI_UNSUPPORTED       This function does not support writing Register.
 395 **/
 396 EFI_STATUS
 397 EFIAPI
 398 SmmCpuFeaturesWriteSaveStateRegister (
 399   IN UINTN                        CpuIndex,
 400   IN EFI_SMM_SAVE_STATE_REGISTER  Register,
 401   IN UINTN                        Width,
 402   IN CONST VOID                   *Buffer
 403   )
 404 {
 405   return EFI_UNSUPPORTED;
 406 }
 407
 408 /**
 409   This function is hook point called after the gEfiSmmReadyToLockProtocolGuid
 410   notification is completely processed.
 411 **/
 412 VOID
 413 EFIAPI
 414 SmmCpuFeaturesCompleteSmmReadyToLock (
 415   VOID
 416   )
 417 {
 418 }
 419
 420 /**
 421   This API provides a method for a CPU to allocate a specific region for storing page tables.
 422
 423   This API can be called more once to allocate memory for page tables.
 424
 425   Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
 426   allocated buffer.  The buffer returned is aligned on a 4KB boundary.  If Pages is 0, then NULL
 427   is returned.  If there is not enough memory remaining to satisfy the request, then NULL is
 428   returned.
 429
 430   This function can also return NULL if there is no preference on where the page tables are allocated in SMRAM.
 431
 432   @param  Pages                 The number of 4 KB pages to allocate.
 433
 434   @return A pointer to the allocated buffer for page tables.
 435   @retval NULL      Fail to allocate a specific region for storing page tables,
 436                     Or there is no preference on where the page tables are allocated in SMRAM.
 437
 438 **/
 439 VOID *
 440 EFIAPI
 441 SmmCpuFeaturesAllocatePageTableMemory (
 442   IN UINTN           Pages
 443   )
 444 {
 445   return NULL;
 446 }