QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/io.h

   1 /** @file
   2 Declaration of IO handling routines.
   3
   4 Copyright (c) 2013-2015 Intel Corporation.
   5
   6 SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9 #ifndef __IO_H
  10 #define __IO_H
  11
  12 #include "core_types.h"
  13
  14 #include "general_definitions.h"
  15 #include "gen5_iosf_sb_definitions.h"
  16
  17 // Instruction not present on Quark
  18 #define SFENCE()
  19
  20 #define DEAD_LOOP()   for(;;);
  21
  22 ////
  23 // Define each of the IOSF_SB ports used by MRC
  24 //
  25
  26 //
  27 // Has to be 0 because of emulation static data
  28 // initialisation:
  29 //   Space_t EmuSpace[ SPACE_COUNT] = {0};
  30 //
  31 #define FREE                0x000
  32
  33 // Pseudo side-band ports for access abstraction
  34 // See Wr32/Rd32 functions
  35 #define MEM                 0x101
  36 #define MMIO                0x102
  37 #define DCMD                0x0A0
  38
  39 // Real side-band ports
  40 // See Wr32/Rd32 functions
  41 #define MCU                 0x001
  42 #define HOST_BRIDGE               0x003
  43 #define MEMORY_MANAGER               0x005
  44 #define HTE                0x011
  45 #define DDRPHY              0x012
  46 #define FUSE                0x033
  47
  48 // End of IOSF_SB ports
  49 ////
  50
  51 // Pciexbar address
  52 #define EC_BASE          0xE0000000
  53
  54 #define PCIADDR(bus,dev,fn,reg) ( \
  55         (EC_BASE) + \
  56     ((bus) << 20) + \
  57     ((dev) << 15) + \
  58     ((fn)  << 12) + \
  59     (reg))
  60
  61 // Various offsets used in the building sideband commands.
  62 #define SB_OPCODE_OFFSET      24
  63 #define SB_PORT_OFFSET        16
  64 #define SB_REG_OFFEST          8
  65
  66 // Sideband opcodes
  67 #define SB_REG_READ_OPCODE        0x10
  68 #define SB_REG_WRITE_OPCODE       0x11
  69
  70 #define SB_FUSE_REG_READ_OPCODE    0x06
  71 #define SB_FUSE_REG_WRITE_OPCODE  0x07
  72
  73 #define SB_DDRIO_REG_READ_OPCODE  0x06
  74 #define SB_DDRIO_REG_WRITE_OPCODE 0x07
  75
  76 #define SB_DRAM_CMND_OPCODE       0x68
  77 #define SB_WAKE_CMND_OPCODE       0xCA
  78 #define SB_SUSPEND_CMND_OPCODE    0xCC
  79
  80 // Register addresses for sideband command and data.
  81 #define SB_PACKET_REG        0x00D0
  82 #define SB_DATA_REG          0x00D4
  83 #define SB_HADR_REG          0x00D8
  84
  85 // We always flag all 4 bytes in the register reads/writes as required.
  86 #define SB_ALL_BYTES_ENABLED  0xF0
  87
  88 #define SB_COMMAND(Opcode, Port, Reg)  \
  89  ((Opcode << SB_OPCODE_OFFSET) |  \
  90   (Port   << SB_PORT_OFFSET) |  \
  91   (Reg    << SB_REG_OFFEST) |  \
  92    SB_ALL_BYTES_ENABLED)
  93
  94 // iosf
  95 #define isbM32m   WrMask32
  96 #define isbW32m   Wr32
  97 #define isbR32m   Rd32
  98
  99 // pci
 100
 101 void pciwrite32(
 102     uint32_t bus,
 103     uint32_t dev,
 104     uint32_t fn,
 105     uint32_t reg,
 106     uint32_t data);
 107
 108 uint32_t pciread32(
 109     uint32_t bus,
 110     uint32_t dev,
 111     uint32_t fn,
 112     uint32_t reg);
 113
 114 // general
 115
 116 uint32_t Rd32(
 117     uint32_t unit,
 118     uint32_t addr);
 119
 120 void Wr32(
 121     uint32_t unit,
 122     uint32_t addr,
 123     uint32_t data);
 124
 125 void WrMask32(
 126     uint32_t unit,
 127     uint32_t addr,
 128     uint32_t data,
 129     uint32_t mask);
 130
 131
 132 #endif