QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/mrc.h

   1 /************************************************************************
   2  *
   3  * Copyright (c) 2013-2015 Intel Corporation.
   4  *
   5 * This program and the accompanying materials
   6 * are licensed and made available under the terms and conditions of the BSD License
   7 * which accompanies this distribution.  The full text of the license may be found at
   8 * http://opensource.org/licenses/bsd-license.php
   9 *
  10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12  *
  13  ************************************************************************/
  14 #ifndef _MRC_H_
  15 #define _MRC_H_
  16
  17 #include "core_types.h"
  18
  19 // define the MRC Version
  20 #define MRC_VERSION 0x0112
  21
  22
  23 // architectural definitions
  24 #define NUM_CHANNELS   1 // number of channels
  25 #define NUM_RANKS      2 // number of ranks per channel
  26 #define NUM_BYTE_LANES 4 // number of byte lanes per channel
  27
  28 // software limitations
  29 #define MAX_CHANNELS   1
  30 #define MAX_RANKS      2
  31 #define MAX_BYTE_LANES 4
  32
  33 // only to mock MrcWrapper
  34 #define MAX_SOCKETS    1
  35 #define MAX_SIDES      1
  36 #define MAX_ROWS       (MAX_SIDES * MAX_SOCKETS)
  37 // end
  38
  39
  40 // Specify DRAM of nenory channel width
  41 enum {
  42   x8,   // DRAM width
  43   x16,  // DRAM width & Channel Width
  44   x32   // Channel Width
  45 };
  46
  47 // Specify DRAM speed
  48 enum {
  49   DDRFREQ_800,
  50   DDRFREQ_1066
  51 };
  52
  53 // Specify DRAM type
  54 enum {
  55   DDR3,
  56   DDR3L
  57 };
  58
  59 // Delay configuration for individual signals
  60 // Vref setting
  61 // Scrambler seed
  62 typedef struct MrcTimings_s
  63 {
  64   uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
  65   uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
  66   uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
  67   uint32_t wdq [NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
  68   uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
  69   uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
  70   uint32_t wcmd[NUM_CHANNELS];
  71
  72   uint32_t scrambler_seed;
  73   uint8_t  ddr_speed;            // need to save for the case of frequency change
  74 } MrcTimings_t;
  75
  76
  77 // DENSITY: 0=512Mb, 1=Gb, 2=2Gb, 3=4Gb
  78 // tCL is DRAM CAS Latency in clocks.
  79 // All other timings are in picoseconds.
  80 // Refer to JEDEC spec (or DRAM datasheet) when changing these values.
  81 typedef struct DRAMParams_s {
  82   uint8_t  DENSITY;
  83   uint8_t  tCL;   // CAS latency in clocks
  84   uint32_t tRAS;  // ACT to PRE command period
  85   uint32_t tWTR;  // Delay from start of internal write transaction to internal read command
  86   uint32_t tRRD;  // ACT to ACT command period (JESD79 specific to page size 1K/2K)
  87   uint32_t tFAW;  // Four activate window (JESD79 specific to page size 1K/2K)
  88 } DRAMParams_t;
  89
  90
  91 // Boot mode defined as bit mask (1<<n)
  92 #define bmCold     1    // full training
  93 #define bmFast     2    // restore timing parameters
  94 #define bmS3       4    // resume from S3
  95 #define bmWarm     8
  96 #define bmUnknown  0
  97
  98
  99 // MRC execution status
 100 #define MRC_SUCCESS     0      // initialization ok
 101 #define MRC_E_MEMTEST   1      // memtest failed
 102
 103
 104 //
 105 // Input/output/context parameters for Memory Reference Code
 106 //
 107 typedef struct MRCParams_s
 108 {
 109   //
 110   // Global settings
 111   //
 112
 113   uint32_t boot_mode;           // bmCold, bmFast, bmWarm, bmS3
 114   uint32_t uart_mmio_base;      // pcie serial port base address (force 0 to disable debug)
 115
 116   uint8_t  dram_width;          // x8, x16
 117   uint8_t  ddr_speed;           // DDRFREQ_800, DDRFREQ_1066
 118   uint8_t  ddr_type;            // DDR3, DDR3L
 119   uint8_t  ecc_enables;         // 0, 1 (memory size reduced to 7/8)
 120   uint8_t  scrambling_enables;  // 0, 1
 121   uint32_t rank_enables;        // 1, 3 (1'st rank has to be populated if 2'nd rank present)
 122   uint32_t channel_enables;     // 1 only
 123   uint32_t channel_width;       // x16 only
 124   uint32_t address_mode;        // 0, 1, 2 (mode 2 forced if ecc enabled)
 125
 126   // memConfig_t begin
 127   uint8_t refresh_rate;         // REFRESH_RATE       : 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED
 128   uint8_t sr_temp_range;        // SR_TEMP_RANGE      : 0=normal, 1=extended, others=RESERVED
 129   uint8_t ron_value;            // RON_VALUE          : 0=34ohm, 1=40ohm, others=RESERVED (select MRS1.DIC driver impedance control)
 130   uint8_t rtt_nom_value;        // RTT_NOM_VALUE      : 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED
 131   uint8_t rd_odt_value;         // RD_ODT_VALUE       : 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED
 132   // memConfig_t end
 133
 134   DRAMParams_t params;
 135
 136   //
 137   // Internally used
 138   //
 139
 140   uint32_t board_id;            // internally used for board layout (use x8 or x16 memory)
 141   uint32_t hte_setup : 1;       // when set hte reconfiguration requested
 142   uint32_t menu_after_mrc : 1;
 143   uint32_t power_down_disable :1;
 144   uint32_t tune_rcvn :1;
 145
 146   uint32_t channel_size[NUM_CHANNELS];
 147   uint32_t column_bits[NUM_CHANNELS];
 148   uint32_t row_bits[NUM_CHANNELS];
 149
 150   uint32_t mrs1;                // register content saved during training
 151
 152   //
 153   // Output
 154   //
 155
 156   uint32_t status;              // initialization result (non zero specifies error code)
 157   uint32_t mem_size;            // total memory size in bytes (excludes ECC banks)
 158
 159   MrcTimings_t timings;         // training results (also used on input)
 160
 161 } MRCParams_t;
 162
 163 // Alternative type name for consistent naming convention
 164 #define MRC_PARAMS    MRCParams_t
 165
 166 #endif // _MRC_H_