QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/mrc.h

   1 /************************************************************************
   2  *
   3  * Copyright (c) 2013-2015 Intel Corporation.
   4  *
   5 * SPDX-License-Identifier: BSD-2-Clause-Patent
   6  *
   7  ************************************************************************/
   8 #ifndef _MRC_H_
   9 #define _MRC_H_
  10
  11 #include "core_types.h"
  12
  13 // define the MRC Version
  14 #define MRC_VERSION 0x0112
  15
  16
  17 // architectural definitions
  18 #define NUM_CHANNELS   1 // number of channels
  19 #define NUM_RANKS      2 // number of ranks per channel
  20 #define NUM_BYTE_LANES 4 // number of byte lanes per channel
  21
  22 // software limitations
  23 #define MAX_CHANNELS   1
  24 #define MAX_RANKS      2
  25 #define MAX_BYTE_LANES 4
  26
  27 // only to mock MrcWrapper
  28 #define MAX_SOCKETS    1
  29 #define MAX_SIDES      1
  30 #define MAX_ROWS       (MAX_SIDES * MAX_SOCKETS)
  31 // end
  32
  33
  34 // Specify DRAM of nenory channel width
  35 enum {
  36   x8,   // DRAM width
  37   x16,  // DRAM width & Channel Width
  38   x32   // Channel Width
  39 };
  40
  41 // Specify DRAM speed
  42 enum {
  43   DDRFREQ_800,
  44   DDRFREQ_1066
  45 };
  46
  47 // Specify DRAM type
  48 enum {
  49   DDR3,
  50   DDR3L
  51 };
  52
  53 // Delay configuration for individual signals
  54 // Vref setting
  55 // Scrambler seed
  56 typedef struct MrcTimings_s
  57 {
  58   uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
  59   uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
  60   uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
  61   uint32_t wdq [NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
  62   uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
  63   uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
  64   uint32_t wcmd[NUM_CHANNELS];
  65
  66   uint32_t scrambler_seed;
  67   uint8_t  ddr_speed;            // need to save for the case of frequency change
  68 } MrcTimings_t;
  69
  70
  71 // DENSITY: 0=512Mb, 1=Gb, 2=2Gb, 3=4Gb
  72 // tCL is DRAM CAS Latency in clocks.
  73 // All other timings are in picoseconds.
  74 // Refer to JEDEC spec (or DRAM datasheet) when changing these values.
  75 typedef struct DRAMParams_s {
  76   uint8_t  DENSITY;
  77   uint8_t  tCL;   // CAS latency in clocks
  78   uint32_t tRAS;  // ACT to PRE command period
  79   uint32_t tWTR;  // Delay from start of internal write transaction to internal read command
  80   uint32_t tRRD;  // ACT to ACT command period (JESD79 specific to page size 1K/2K)
  81   uint32_t tFAW;  // Four activate window (JESD79 specific to page size 1K/2K)
  82 } DRAMParams_t;
  83
  84
  85 // Boot mode defined as bit mask (1<<n)
  86 #define bmCold     1    // full training
  87 #define bmFast     2    // restore timing parameters
  88 #define bmS3       4    // resume from S3
  89 #define bmWarm     8
  90 #define bmUnknown  0
  91
  92
  93 // MRC execution status
  94 #define MRC_SUCCESS     0      // initialization ok
  95 #define MRC_E_MEMTEST   1      // memtest failed
  96
  97
  98 //
  99 // Input/output/context parameters for Memory Reference Code
 100 //
 101 typedef struct MRCParams_s
 102 {
 103   //
 104   // Global settings
 105   //
 106
 107   uint32_t boot_mode;           // bmCold, bmFast, bmWarm, bmS3
 108   uint32_t uart_mmio_base;      // pcie serial port base address (force 0 to disable debug)
 109
 110   uint8_t  dram_width;          // x8, x16
 111   uint8_t  ddr_speed;           // DDRFREQ_800, DDRFREQ_1066
 112   uint8_t  ddr_type;            // DDR3, DDR3L
 113   uint8_t  ecc_enables;         // 0, 1 (memory size reduced to 7/8)
 114   uint8_t  scrambling_enables;  // 0, 1
 115   uint32_t rank_enables;        // 1, 3 (1'st rank has to be populated if 2'nd rank present)
 116   uint32_t channel_enables;     // 1 only
 117   uint32_t channel_width;       // x16 only
 118   uint32_t address_mode;        // 0, 1, 2 (mode 2 forced if ecc enabled)
 119
 120   // memConfig_t begin
 121   uint8_t refresh_rate;         // REFRESH_RATE       : 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED
 122   uint8_t sr_temp_range;        // SR_TEMP_RANGE      : 0=normal, 1=extended, others=RESERVED
 123   uint8_t ron_value;            // RON_VALUE          : 0=34ohm, 1=40ohm, others=RESERVED (select MRS1.DIC driver impedance control)
 124   uint8_t rtt_nom_value;        // RTT_NOM_VALUE      : 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED
 125   uint8_t rd_odt_value;         // RD_ODT_VALUE       : 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED
 126   // memConfig_t end
 127
 128   DRAMParams_t params;
 129
 130   //
 131   // Internally used
 132   //
 133
 134   uint32_t board_id;            // internally used for board layout (use x8 or x16 memory)
 135   uint32_t hte_setup : 1;       // when set hte reconfiguration requested
 136   uint32_t menu_after_mrc : 1;
 137   uint32_t power_down_disable :1;
 138   uint32_t tune_rcvn :1;
 139
 140   uint32_t channel_size[NUM_CHANNELS];
 141   uint32_t column_bits[NUM_CHANNELS];
 142   uint32_t row_bits[NUM_CHANNELS];
 143
 144   uint32_t mrs1;                // register content saved during training
 145
 146   //
 147   // Output
 148   //
 149
 150   uint32_t status;              // initialization result (non zero specifies error code)
 151   uint32_t mem_size;            // total memory size in bytes (excludes ECC banks)
 152
 153   MrcTimings_t timings;         // training results (also used on input)
 154
 155 } MRCParams_t;
 156
 157 // Alternative type name for consistent naming convention
 158 #define MRC_PARAMS    MRCParams_t
 159
 160 #endif // _MRC_H_