QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/platform.c

   1 /** @file
   2 The interface layer for memory controller access.
   3 It is supporting both real hardware platform and simulation environment.
   4
   5 Copyright (c) 2013-2015 Intel Corporation.
   6
   7 SPDX-License-Identifier: BSD-2-Clause-Patent
   8
   9 **/
  10 #include "mrc.h"
  11 #include "memory_options.h"
  12 #include "meminit_utils.h"
  13 #include "io.h"
  14
  15 #ifdef SIM
  16
  17 void SimMmio32Write (
  18     uint32_t be,
  19     uint32_t address,
  20     uint32_t data );
  21
  22 void SimMmio32Read (
  23     uint32_t be,
  24     uint32_t address,
  25     uint32_t *data );
  26
  27 void SimDelayClk (
  28     uint32_t x2clk );
  29
  30 // This is a simple delay function.
  31 // It takes "nanoseconds" as a parameter.
  32 void delay_n(uint32_t nanoseconds)
  33 {
  34   SimDelayClk( 800*nanoseconds/1000);
  35 }
  36 #endif
  37
  38 /****
  39  *
  40  ***/
  41 uint32_t Rd32(
  42     uint32_t unit,
  43     uint32_t addr)
  44 {
  45   uint32_t data;
  46
  47   switch (unit)
  48   {
  49   case MEM:
  50     case MMIO:
  51 #ifdef SIM
  52     SimMmio32Read( 1, addr, &data);
  53 #else
  54     data = *PTR32(addr);
  55 #endif
  56     break;
  57
  58   case MCU:
  59     case HOST_BRIDGE:
  60     case MEMORY_MANAGER:
  61     case HTE:
  62     // Handle case addr bigger than 8bit
  63     pciwrite32(0, 0, 0, SB_HADR_REG, addr & 0xFFF00);
  64     addr &= 0x00FF;
  65
  66     pciwrite32(0, 0, 0, SB_PACKET_REG,
  67         SB_COMMAND(SB_REG_READ_OPCODE, unit, addr));
  68     data = pciread32(0, 0, 0, SB_DATA_REG);
  69     break;
  70
  71   case DDRPHY:
  72     // Handle case addr bigger than 8bit
  73     pciwrite32(0, 0, 0, SB_HADR_REG, addr & 0xFFF00);
  74     addr &= 0x00FF;
  75
  76     pciwrite32(0, 0, 0, SB_PACKET_REG,
  77         SB_COMMAND(SB_DDRIO_REG_READ_OPCODE, unit, addr));
  78     data = pciread32(0, 0, 0, SB_DATA_REG);
  79     break;
  80
  81   default:
  82     DEAD_LOOP()
  83     ;
  84   }
  85
  86   if (unit < MEM)
  87     DPF(D_REGRD, "RD32 %03X %08X %08X\n", unit, addr, data);
  88
  89   return data;
  90 }
  91
  92 /****
  93  *
  94  ***/
  95 void Wr32(
  96     uint32_t unit,
  97     uint32_t addr,
  98     uint32_t data)
  99 {
 100   if (unit < MEM)
 101     DPF(D_REGWR, "WR32 %03X %08X %08X\n", unit, addr, data);
 102
 103   switch (unit)
 104   {
 105   case MEM:
 106     case MMIO:
 107 #ifdef SIM
 108     SimMmio32Write( 1, addr, data);
 109 #else
 110     *PTR32(addr) = data;
 111 #endif
 112     break;
 113
 114   case MCU:
 115     case HOST_BRIDGE:
 116     case MEMORY_MANAGER:
 117     case HTE:
 118     // Handle case addr bigger than 8bit
 119     pciwrite32(0, 0, 0, SB_HADR_REG, addr & 0xFFF00);
 120     addr &= 0x00FF;
 121
 122     pciwrite32(0, 0, 0, SB_DATA_REG, data);
 123     pciwrite32(0, 0, 0, SB_PACKET_REG,
 124         SB_COMMAND(SB_REG_WRITE_OPCODE, unit, addr));
 125     break;
 126
 127   case DDRPHY:
 128     // Handle case addr bigger than 8bit
 129     pciwrite32(0, 0, 0, SB_HADR_REG, addr & 0xFFF00);
 130     addr &= 0x00FF;
 131
 132     pciwrite32(0, 0, 0, SB_DATA_REG, data);
 133     pciwrite32(0, 0, 0, SB_PACKET_REG,
 134         SB_COMMAND(SB_DDRIO_REG_WRITE_OPCODE, unit, addr));
 135     break;
 136
 137   case DCMD:
 138     pciwrite32(0, 0, 0, SB_HADR_REG, 0);
 139     pciwrite32(0, 0, 0, SB_DATA_REG, data);
 140     pciwrite32(0, 0, 0, SB_PACKET_REG,
 141         SB_COMMAND(SB_DRAM_CMND_OPCODE, MCU, 0));
 142     break;
 143
 144   default:
 145     DEAD_LOOP()
 146     ;
 147   }
 148 }
 149
 150 /****
 151  *
 152  ***/
 153 void WrMask32(
 154     uint32_t unit,
 155     uint32_t addr,
 156     uint32_t data,
 157     uint32_t mask)
 158 {
 159   Wr32(unit, addr, ((Rd32(unit, addr) & ~mask) | (data & mask)));
 160 }
 161
 162 /****
 163  *
 164  ***/
 165 void pciwrite32(
 166     uint32_t bus,
 167     uint32_t dev,
 168     uint32_t fn,
 169     uint32_t reg,
 170     uint32_t data)
 171 {
 172   Wr32(MMIO, PCIADDR(bus,dev,fn,reg), data);
 173 }
 174
 175 /****
 176  *
 177  ***/
 178 uint32_t pciread32(
 179     uint32_t bus,
 180     uint32_t dev,
 181     uint32_t fn,
 182     uint32_t reg)
 183 {
 184   return Rd32(MMIO, PCIADDR(bus,dev,fn,reg));
 185 }
 186