QuarkSocPkg/QuarkSouthCluster/Include/I2cRegs.h

   1 /** @file
   2 Include file for I2C DXE Driver register definitions (PCIe config. space and memory space).
   3
   4 Copyright (c) 2013-2015 Intel Corporation.
   5
   6 SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9
  10 #ifndef _I2C_REGS_H_
  11 #define _I2C_REGS_H_
  12
  13
  14 //----------------------------------------------------------------------------
  15 /// I2C Device Address
  16 //----------------------------------------------------------------------------
  17 typedef struct {
  18   ///
  19   /// The I2C hardware address to which the I2C device is preassigned or allocated.
  20   ///
  21   UINTN I2CDeviceAddress : 10;
  22 } EFI_I2C_DEVICE_ADDRESS;
  23
  24 //----------------------------------------------------------------------------
  25 /// I2C Addressing Mode (7-bit or 10 bit)
  26 //----------------------------------------------------------------------------
  27 typedef enum _EFI_I2C_ADDR_MODE {
  28   EfiI2CSevenBitAddrMode,
  29   EfiI2CTenBitAddrMode,
  30 } EFI_I2C_ADDR_MODE;
  31
  32
  33 //----------------------------------------------------------------------------
  34 // I2C Controller B:D:F
  35 //----------------------------------------------------------------------------
  36 #define I2C_Bus     0x00
  37 #define I2C_Device  0x15
  38 #define I2C_Func    0x02
  39
  40 //----------------------------------------------------------------------------
  41 // Memory Mapped Registers
  42 //----------------------------------------------------------------------------
  43 #define I2C_REG_CON                        0x00          // Control Register
  44 #define   B_I2C_REG_CON_SPEED                (BIT2+BIT1)   // standard mode (01) or fast mode (10)
  45 #define   B_I2C_REG_CON_10BITADD_MASTER      (BIT4)        // 7-bit addressing (0) or 10-bit addressing (1)
  46 #define I2C_REG_TAR                        0x04          // Master Target Address Register
  47 #define   B_I2C_REG_TAR                      (BIT9+BIT8+BIT7+BIT6+BIT5+BIT4+BIT3+BIT2+BIT1+BIT0) // Master Target Address bits
  48 #define I2C_REG_DATA_CMD                   0x10          // Data Buffer and Command Register
  49 #define   B_I2C_REG_DATA_CMD_RW              (BIT8)      // Data Buffer and Command Register Read/Write bit
  50 #define   B_I2C_REG_DATA_CMD_STOP            (BIT9)      // Data Buffer and Command Register STOP bit
  51 #define   B_I2C_REG_DATA_CMD_RESTART         (BIT10)     // Data Buffer and Command Register RESTART bit
  52 #define I2C_REG_SS_SCL_HCNT                0x14          // Standard Speed Clock SCL High Count Register
  53 #define I2C_REG_SS_SCL_LCNT                0x18          // Standard Speed Clock SCL Low Count Register
  54 #define I2C_REG_FS_SCL_HCNT                0x1C          // Fast Speed Clock SCL High Count Register
  55 #define I2C_REG_FS_SCL_LCNT                0x20          // Fast Speed Clock SCL Low Count Register
  56 #define I2C_REG_INTR_STAT                  0x2C          // Interrupt Status Register
  57 #define   B_I2C_REG_INTR_STAT_STOP_DET       (BIT9)        // Interrupt Status Register STOP_DET signal status
  58 #define I2C_REG_INTR_MASK                  0x30          // Interrupt Status Mask Register
  59 #define I2C_REG_RAW_INTR_STAT              0x34          // Raw Interrupt Status Register
  60 #define   I2C_REG_RAW_INTR_STAT_STOP_DET    (BIT9)         // Raw Interrupt Status Register STOP_DET signal status.
  61 #define   I2C_REG_RAW_INTR_STAT_TX_ABRT     (BIT6)         // Raw Interrupt Status Register TX Abort status.
  62 #define   I2C_REG_RAW_INTR_STAT_TX_OVER     (BIT3)         // Raw Interrupt Status Register TX Overflow signal status.
  63 #define   I2C_REG_RAW_INTR_STAT_RX_OVER     (BIT1)         // Raw Interrupt Status Register RX Overflow signal status.
  64 #define   I2C_REG_RAW_INTR_STAT_RX_UNDER    (BIT0)         // Raw Interrupt Status Register RX Underflow signal status.
  65 #define I2C_REG_RX_TL                      0x38          // Receive FIFO Threshold Level Register
  66 #define I2C_REG_TX_TL                      0x3C          // Transmit FIFO Threshold Level Register
  67 #define I2C_REG_CLR_INT                    0x40          // Clear Combined and Individual Interrupt Register
  68 #define I2C_REG_CLR_RX_UNDER               0x44          // Clear RX Under Interrupt Register
  69 #define I2C_REG_CLR_RX_OVER                0x48          // Clear RX Over Interrupt Register
  70 #define I2C_REG_CLR_TX_OVER                0x4C          // Clear TX Over Interrupt Register
  71 #define I2C_REG_CLR_RD_REQ                 0x50          // Clear RD REQ Interrupt Register
  72 #define I2C_REG_CLR_TX_ABRT                0x54          // Clear TX ABRT Interrupt Register
  73 #define I2C_REG_CLR_ACTIVITY               0x5C          // Clear Activity Interrupt Register
  74 #define I2C_REG_CLR_STOP_DET               0x60          // Clear STOP DET Interrupt Register
  75 #define   B_I2C_REG_CLR_STOP_DET             (BIT0)        // Clear STOP DET Interrupt Register
  76 #define I2C_REG_CLR_START_DET              0x64          // Clear START DET Interrupt Register
  77 #define   B_I2C_REG_CLR_START_DET          (BIT0)          // Clear START DET Interrupt Register
  78 #define I2C_REG_ENABLE                     0x6C          // Enable Register
  79 #define   B_I2C_REG_ENABLE                   (BIT0)        // Enable (1) or disable (0) I2C Controller
  80 #define I2C_REG_STATUS                     0x70          // Status Register
  81 #define I2C_REG_TXFLR                      0x74          // Transmit FIFO Level Register
  82 #define   B_I2C_REG_TXFLR                   (BIT3+BIT2+BIT1+BIT0)  // Transmit FIFO Level Register bits
  83 #define I2C_REG_RXFLR                      0x78          // Receive FIFO Level Register
  84 #define   B_I2C_REG_RXFLR                   (BIT3+BIT2+BIT1+BIT0)  // Receive FIFO Level Register bits
  85 #define I2C_REG_SDA_HOLD                   0x7C          // SDA HOLD Register
  86 #define I2C_REG_TX_ABRT_SOURCE             0x80          // Transmit Abort Source Register
  87 #define I2C_REG_ENABLE_STATUS              0x9C          // Enable Status Register
  88 #define I2C_REG_FS_SPKLEN                  0xA0          // SS and FS Spike Suppression Limit Register
  89
  90 //
  91 // Features.
  92 //
  93 #define I2C_FIFO_SIZE                      16
  94
  95 #endif