QuarkSocPkg/QuarkSouthCluster/Include/Ioh.h

   1 /** @file
   2 Header file for QuarkSCSocId Ioh.
   3 Copyright (c) 2013-2015 Intel Corporation.
   4
   5 SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7
   8 **/
   9 #ifndef _IOH_H_
  10 #define _IOH_H_
  11
  12 #ifndef BIT0
  13 #define BIT0    0x01
  14 #define BIT1    0x02
  15 #define BIT2    0x04
  16 #define BIT3    0x08
  17 #define BIT4    0x10
  18 #define BIT5    0x20
  19 #define BIT6    0x40
  20 #define BIT7    0x80
  21 #define BIT8    0x100
  22 #define BIT9    0x200
  23 #define BIT00   0x00000001
  24 #define BIT01   0x00000002
  25 #define BIT02   0x00000004
  26 #define BIT03   0x00000008
  27 #define BIT04   0x00000010
  28 #define BIT05   0x00000020
  29 #define BIT06   0x00000040
  30 #define BIT07   0x00000080
  31 #define BIT08   0x00000100
  32 #define BIT09   0x00000200
  33 #define BIT10   0x00000400
  34 #define BIT11   0x00000800
  35 #define BIT12   0x00001000
  36 #define BIT13   0x00002000
  37 #define BIT14   0x00004000
  38 #define BIT15   0x00008000
  39 #define BIT16   0x00010000
  40 #define BIT17   0x00020000
  41 #define BIT18   0x00040000
  42 #define BIT19   0x00080000
  43 #define BIT20   0x00100000
  44 #define BIT21   0x00200000
  45 #define BIT22   0x00400000
  46 #define BIT23   0x00800000
  47 #define BIT24   0x01000000
  48 #define BIT25   0x02000000
  49 #define BIT26   0x04000000
  50 #define BIT27   0x08000000
  51 #define BIT28   0x10000000
  52 #define BIT29   0x20000000
  53 #define BIT30   0x40000000
  54 #define BIT31   0x80000000
  55 #endif
  56
  57 #define IOH_PCI_CFG_ADDRESS(bus,dev,func,reg) \
  58     ((UINT32) ( (((UINTN)bus) << 24) + (((UINTN)dev) << 16) + \
  59     (((UINTN)func) << 8) + ((UINTN)reg) ))& 0x00000000ffffffff
  60
  61 //----------------------------------------------------------------------------
  62
  63 #define INTEL_VENDOR_ID         0x8086  // Intel Vendor ID
  64
  65 //----------------------------------------------------------------------------
  66 // Pci Configuration Map Register Offsets
  67 //----------------------------------------------------------------------------
  68 #define PCI_REG_VID             0x00    // Vendor ID Register
  69 #define PCI_REG_DID             0x02    // Device ID Register
  70 #define PCI_REG_PCICMD          0x04    // PCI Command Register
  71 #define PCI_REG_PCISTS          0x06    // PCI Status Register
  72 #define PCI_REG_RID             0x08    // PCI Revision ID Register
  73 #define PCI_REG_PI              0x09    // Programming Interface
  74 #define PCI_REG_SCC             0x0a    // Sub Class Code Register
  75 #define PCI_REG_BCC             0x0b    // Base Class Code Register
  76 #define PCI_REG_PMLT            0x0d    // Primary Master Latnecy Timer
  77 #define PCI_REG_HDR             0x0e    // Header Type Register
  78 #define PCI_REG_PBUS            0x18    // Primary Bus Number Register
  79 #define PCI_REG_SBUS            0x19    // Secondary Bus Number Register
  80 #define PCI_REG_SUBUS           0x1a    // Subordinate Bus Number Register
  81 #define PCI_REG_SMLT            0x1b    // Secondary Master Latnecy Timer
  82 #define PCI_REG_IOBASE          0x1c    // I/O base Register
  83 #define PCI_REG_IOLIMIT         0x1d    // I/O Limit Register
  84 #define PCI_REG_SECSTATUS       0x1e    // Secondary Status Register
  85 #define PCI_REG_MEMBASE         0x20    // Memory Base Register
  86 #define PCI_REG_MEMLIMIT        0x22    // Memory Limit Register
  87 #define PCI_REG_PRE_MEMBASE     0x24    // Prefretchable memory Base register
  88 #define PCI_REG_PRE_MEMLIMIT    0x26    // Prefretchable memory Limit register
  89 #define PCI_REG_SVID0           0x2c    // Subsystem Vendor ID low byte
  90 #define PCI_REG_SVID1           0x2d    // Subsystem Vendor ID high byte
  91 #define PCI_REG_SID0            0x2e    // Subsystem ID low byte
  92 #define PCI_REG_SID1            0x2f    // Subsystem ID high byte
  93 #define PCI_REG_IOBASE_U        0x30    // I/O base Upper Register
  94 #define PCI_REG_IOLIMIT_U       0x32    // I/O Limit Upper Register
  95 #define PCI_REG_INTLINE         0x3c    // Interrupt Line Register
  96 #define PCI_REG_BRIDGE_CNTL     0x3e    // Bridge Control Register
  97
  98 //---------------------------------------------------------------------------
  99 // QuarkSCSocId Packet Hub definitions
 100 //---------------------------------------------------------------------------
 101
 102 #define PCIE_BRIDGE_VID_DID     0x88008086
 103
 104 //---------------------------------------------------------------------------
 105 // Quark South Cluster definitions.
 106 //---------------------------------------------------------------------------
 107
 108 #define IOH_BUS                           0
 109 #define IOH_PCI_IOSF2AHB_0_DEV_NUM        0x14
 110 #define IOH_PCI_IOSF2AHB_0_MAX_FUNCS      7
 111 #define IOH_PCI_IOSF2AHB_1_DEV_NUM        0x15
 112 #define IOH_PCI_IOSF2AHB_1_MAX_FUNCS      3
 113
 114 //---------------------------------------------------------------------------
 115 // Quark South Cluster USB definitions.
 116 //---------------------------------------------------------------------------
 117
 118 #define IOH_USB_BUS_NUMBER                IOH_BUS
 119 #define IOH_USB_CONTROLLER_MMIO_RANGE     0x1000
 120 #define IOH_MAX_OHCI_USB_CONTROLLERS      1
 121 #define IOH_MAX_EHCI_USB_CONTROLLERS      1
 122 #define IOH_MAX_USBDEVICE_USB_CONTROLLERS 1
 123
 124 #define R_IOH_USB_VENDOR_ID               0x00
 125 #define   V_IOH_USB_VENDOR_ID               INTEL_VENDOR_ID
 126 #define R_IOH_USB_DEVICE_ID               0x02
 127 #define R_IOH_USB_COMMAND                 0x04
 128 #define   B_IOH_USB_COMMAND_BME             BIT2
 129 #define   B_IOH_USB_COMMAND_MSE             BIT1
 130 #define   B_IOH_USB_COMMAND_ISE             BIT0
 131 #define R_IOH_USB_MEMBAR                  0x10
 132 #define   B_IOH_USB_MEMBAR_ADDRESS_MASK     0xFFFFF000  // [31:12].
 133 #define R_IOH_USB_OHCI_HCCABAR            0x18
 134
 135 //---------------------------------------------------------------------------
 136 // Quark South Cluster OHCI definitions
 137 //---------------------------------------------------------------------------
 138 #define IOH_USB_OHCI_DEVICE_NUMBER        IOH_PCI_IOSF2AHB_0_DEV_NUM
 139 #define IOH_OHCI_FUNCTION_NUMBER          0x04
 140
 141 //---------------------------------------------------------------------------
 142 // Quark South Cluster EHCI definitions
 143 //---------------------------------------------------------------------------
 144 #define IOH_USB_EHCI_DEVICE_NUMBER        IOH_PCI_IOSF2AHB_0_DEV_NUM
 145 #define IOH_EHCI_FUNCTION_NUMBER          0x03
 146
 147 //
 148 // EHCI memory mapped registers offset from memory BAR0.
 149 //
 150 #define R_IOH_EHCI_CAPLENGTH              0x00
 151 #define R_IOH_EHCI_INSNREG01              0x94
 152 #define   B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP    (16)
 153 #define   B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_MASK  (0xff << B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP)
 154 #define   B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP     (0)
 155 #define   B_IOH_EHCI_INSNREG01_IN_THRESHOLD_MASK   (0xff << B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP)
 156
 157 //
 158 // EHCI memory mapped registers offset from memory BAR0 + Cap length value.
 159 //
 160 #define R_IOH_EHCI_CONFIGFLAGS            0x40
 161
 162 //---------------------------------------------------------------------------
 163 // Quark South Cluster USB Device definitions
 164 //---------------------------------------------------------------------------
 165 #define IOH_USBDEVICE_DEVICE_NUMBER       IOH_PCI_IOSF2AHB_0_DEV_NUM
 166 #define IOH_USBDEVICE_FUNCTION_NUMBER     0x02
 167
 168 //
 169 // USB Device memory mapped registers offset from memory BAR0.
 170 //
 171 #define R_IOH_USBDEVICE_D_INTR_UDC_REG                      0x40c
 172 #define R_IOH_USBDEVICE_D_INTR_MSK_UDC_REG                  0x410
 173 #define   B_IOH_USBDEVICE_D_INTR_MSK_UDC_REG_MASK1_MASK       0xff
 174 #define R_IOH_USBDEVICE_EP_INTR_UDC_REG                     0x414
 175 #define R_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG                 0x418
 176 #define   B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_OUT_EP_MASK     0x000f0000
 177 #define   B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_IN_EP_MASK      0x0000000f
 178
 179 //---------------------------------------------------------------------------
 180 // Quark South Cluster 10/100 Mbps Ethernet Device definitions.
 181 //---------------------------------------------------------------------------
 182 #define IOH_MAC0_BUS_NUMBER                                 IOH_BUS
 183 #define IOH_MAC0_DEVICE_NUMBER                              IOH_PCI_IOSF2AHB_0_DEV_NUM
 184 #define IOH_MAC0_FUNCTION_NUMBER                            0x06
 185 #define IOH_MAC1_BUS_NUMBER                                 IOH_BUS
 186 #define IOH_MAC1_DEVICE_NUMBER                              IOH_PCI_IOSF2AHB_0_DEV_NUM
 187 #define IOH_MAC1_FUNCTION_NUMBER                            0x07
 188
 189 //
 190 // MAC Device PCI config registers.
 191 //
 192 #define R_IOH_MAC_DEVICE_ID                                 0x02
 193 #define   V_IOH_MAC_VENDOR_ID                                 INTEL_VENDOR_ID
 194 #define R_IOH_MAC_DEVICE_ID                                 0x02
 195 #define   V_IOH_MAC_DEVICE_ID                                 0x0937
 196 #define R_IOH_MAC_COMMAND                                   0x04
 197 #define   B_IOH_MAC_COMMAND_BME                               BIT2
 198 #define   B_IOH_MAC_COMMAND_MSE                               BIT1
 199 #define   B_IOH_MAC_COMMAND_ISE                               BIT0
 200 #define R_IOH_MAC_MEMBAR                                    0x10
 201 #define   B_IOH_MAC_MEMBAR_ADDRESS_MASK                       0xFFFFF000
 202
 203 //
 204 // LAN Device memory mapped registers offset from memory BAR0.
 205 //
 206 #define R_IOH_MAC_GMAC_REG_8                                0x20
 207 #define   B_IOH_MAC_USERVER_MASK                              0x0000FF00
 208 #define   B_IOH_MAC_SNPSVER_MASK                              0x000000FF
 209 #define R_IOH_MAC_GMAC_REG_16                               0x40
 210 #define   B_IOH_MAC_ADDRHI_MASK                               0x0000FFFF
 211 #define   B_IOH_MAC_AE                                        BIT31
 212 #define R_IOH_MAC_GMAC_REG_17                               0x44
 213 #define   B_IOH_MAC_ADDRLO_MASK                               0xFFFFFFFF
 214
 215 //---------------------------------------------------------------------------
 216 // Quark I2C / GPIO definitions
 217 //---------------------------------------------------------------------------
 218
 219 #define   V_IOH_I2C_GPIO_VENDOR_ID          INTEL_VENDOR_ID
 220 #define   V_IOH_I2C_GPIO_DEVICE_ID          0x0934
 221
 222 #define R_IOH_I2C_MEMBAR                  0x10
 223 #define   B_IOH_I2C_GPIO_MEMBAR_ADDR_MASK   0xFFFFF000  // [31:12].
 224
 225 #define GPIO_SWPORTA_DR                   0x00
 226 #define GPIO_SWPORTA_DDR                  0x04
 227 #define GPIO_INTEN                        0x30
 228 #define GPIO_INTMASK                      0x34
 229 #define GPIO_INTTYPE_LEVEL                0x38
 230 #define GPIO_INT_POLARITY                 0x3C
 231 #define GPIO_INTSTATUS                    0x40
 232 #define GPIO_RAW_INTSTATUS                0x44
 233 #define GPIO_DEBOUNCE                     0x48
 234 #define GPIO_PORTA_EOI                    0x4C
 235 #define GPIO_EXT_PORTA                    0x50
 236 #define GPIO_EXT_PORTB                    0x54
 237 #define GPIO_LS_SYNC                      0x60
 238 #define GPIO_CONFIG_REG2                  0x70
 239 #define GPIO_CONFIG_REG1                  0x74
 240
 241 //---------------------------------------------------------------------------
 242 // Quark South Cluster UART definitions.
 243 //---------------------------------------------------------------------------
 244
 245 #define R_IOH_UART_MEMBAR                 0x10
 246 #define   B_IOH_UART_MEMBAR_ADDRESS_MASK    0xFFFFF000  // [31:12].
 247
 248 #endif