QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/OhciReg.h

   1 /** @file
   2 This file contains the definination for host controller
   3 register operation routines.
   4
   5 Copyright (c) 2013-2015 Intel Corporation.
   6
   7 This program and the accompanying materials
   8 are licensed and made available under the terms and conditions of the BSD License
   9 which accompanies this distribution.  The full text of the license may be found at
  10 http://opensource.org/licenses/bsd-license.php
  11
  12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15 **/
  16
  17
  18
  19 #ifndef   _OHCI_REG_H
  20 #define   _OHCI_REG_H
  21
  22 #define   HC_STATE_RESET         0x0
  23 #define   HC_STATE_RESUME        0x1
  24 #define   HC_STATE_OPERATIONAL   0x2
  25 #define   HC_STATE_SUSPEND       0x3
  26
  27 #define   PERIODIC_ENABLE               0x01
  28 #define   ISOCHRONOUS_ENABLE            0x02
  29 #define   CONTROL_ENABLE                0x04
  30 #define   BULK_ENABLE                   0x08
  31 #define   CONTROL_BULK_RATIO            0x10
  32
  33 #define   HC_FUNCTIONAL_STATE    0x20
  34 #define   INTERRUPT_ROUTING      0x40
  35
  36 #define   HC_RESET               0x01
  37 #define   CONTROL_LIST_FILLED    0x02
  38 #define   BULK_LIST_FILLED       0x04
  39 #define   CHANGE_OWNER_REQUEST   0x08
  40
  41 #define   SCHEDULE_OVERRUN_COUNT 0x10
  42
  43 #define   SCHEDULE_OVERRUN       0x00001
  44 #define   WRITEBACK_DONE_HEAD    0x00002
  45 #define   START_OF_FRAME         0x00004
  46 #define   RESUME_DETECT          0x00008
  47 #define   UNRECOVERABLE_ERROR    0x00010
  48 #define   FRAME_NUMBER_OVERFLOW  0x00020
  49 #define   ROOTHUB_STATUS_CHANGE  0x00040
  50 #define   OWNERSHIP_CHANGE       0x00080
  51
  52 #define   MASTER_INTERRUPT       0x00400
  53
  54 #define   CONTROL_HEAD           0x001
  55 #define   BULK_HEAD              0x002
  56 #define   DONE_HEAD              0x004
  57
  58 #define   Hc_HCCA                0x001
  59 #define   Hc_PERIODIC_CURRENT    0x002
  60 #define   Hc_CONTOL_HEAD         0x004
  61 #define   Hc_CONTROL_CURRENT_PTR 0x008
  62 #define   Hc_BULK_HEAD           0x010
  63 #define   Hc_BULK_CURRENT_PTR    0x020
  64 #define   Hc_DONE_HEAD           0x040
  65
  66 #define   FRAME_INTERVAL         0x008
  67 #define   FS_LARGEST_DATA_PACKET 0x010
  68 #define   FRMINT_TOGGLE          0x020
  69 #define   FRAME_REMAINING        0x040
  70 #define   FRAME_REMAIN_TOGGLE    0x080
  71
  72 #define   RH_DESC_A              0x00001
  73 #define   RH_DESC_B              0x00002
  74 #define   RH_NUM_DS_PORTS        0x00004
  75 #define   RH_NO_PSWITCH          0x00008
  76 #define   RH_PSWITCH_MODE        0x00010
  77 #define   RH_DEVICE_TYPE         0x00020
  78 #define   RH_OC_PROT_MODE        0x00040
  79 #define   RH_NOC_PROT            0x00080
  80 #define   RH_POTPGT              0x00100
  81 #define   RH_NO_POTPGT           0x00200
  82 #define   RH_DEV_REMOVABLE       0x00400
  83 #define   RH_PORT_PWR_CTRL_MASK  0x00800
  84
  85 #define   RH_LOCAL_PSTAT         0x00001
  86 #define   RH_OC_ID               0x00002
  87 #define   RH_REMOTE_WK_ENABLE    0x00004
  88 #define   RH_LOCAL_PSTAT_CHANGE  0x00008
  89 #define   RH_OC_ID_CHANGE        0x00010
  90 #define   RH_CLR_RMT_WK_ENABLE   0x00020
  91
  92 #define   RH_CLEAR_PORT_ENABLE        0x0001
  93 #define   RH_SET_PORT_ENABLE          0x0002
  94 #define   RH_SET_PORT_SUSPEND         0x0004
  95 #define   RH_CLEAR_SUSPEND_STATUS     0x0008
  96 #define   RH_SET_PORT_RESET           0x0010
  97 #define   RH_SET_PORT_POWER           0x0020
  98 #define   RH_CLEAR_PORT_POWER         0x0040
  99 #define   RH_CONNECT_STATUS_CHANGE    0x10000
 100 #define   RH_PORT_ENABLE_STAT_CHANGE  0x20000
 101 #define   RH_PORT_SUSPEND_STAT_CHANGE 0x40000
 102 #define   RH_OC_INDICATOR_CHANGE      0x80000
 103 #define   RH_PORT_RESET_STAT_CHANGE   0x100000
 104
 105 #define   RH_CURR_CONNECT_STAT        0x0001
 106 #define   RH_PORT_ENABLE_STAT         0x0002
 107 #define   RH_PORT_SUSPEND_STAT        0x0004
 108 #define   RH_PORT_OC_INDICATOR        0x0008
 109 #define   RH_PORT_RESET_STAT          0x0010
 110 #define   RH_PORT_POWER_STAT          0x0020
 111 #define   RH_LSDEVICE_ATTACHED        0x0040
 112
 113 #define   RESET_SYSTEM_BUS            (1 << 0)
 114 #define   RESET_HOST_CONTROLLER       (1 << 1)
 115 #define   RESET_CLOCK_GENERATION      (1 << 2)
 116 #define   RESET_SSE_GLOBAL            (1 << 5)
 117 #define   RESET_PSPL                  (1 << 6)
 118 #define   RESET_PCPL                  (1 << 7)
 119 #define   RESET_SSEP1                 (1 << 9)
 120 #define   RESET_SSEP2                 (1 << 10)
 121 #define   RESET_SSEP3                 (1 << 11)
 122
 123 #define ONE_SECOND                      1000000
 124 #define ONE_MILLI_SEC                   1000
 125 #define MAX_BYTES_PER_TD                0x1000
 126 #define MAX_RETRY_TIMES                 100
 127 #define PORT_NUMBER_ON_MAINSTONE2       1
 128
 129
 130 //
 131 // Operational Register Offsets
 132 //
 133
 134 //
 135 // Command & Status Registers Offsets
 136 //
 137 #define HC_REVISION             0x00
 138 #define HC_CONTROL              0x04
 139 #define HC_COMMAND_STATUS       0x08
 140 #define HC_INTERRUPT_STATUS     0x0C
 141 #define HC_INTERRUPT_ENABLE     0x10
 142 #define HC_INTERRUPT_DISABLE    0x14
 143
 144 //
 145 // Memory Pointer Offsets
 146 //
 147 #define HC_HCCA                 0x18
 148 #define HC_PERIODIC_CURRENT     0x1C
 149 #define HC_CONTROL_HEAD         0x20
 150 #define HC_CONTROL_CURRENT_PTR  0x24
 151 #define HC_BULK_HEAD            0x28
 152 #define HC_BULK_CURRENT_PTR     0x2C
 153 #define HC_DONE_HEAD            0x30
 154
 155 //
 156 // Frame Register Offsets
 157 //
 158 #define HC_FRM_INTERVAL         0x34
 159 #define HC_FRM_REMAINING        0x38
 160 #define HC_FRM_NUMBER           0x3C
 161 #define HC_PERIODIC_START       0x40
 162 #define HC_LS_THREASHOLD        0x44
 163
 164 //
 165 // Root Hub Register Offsets
 166 //
 167 #define HC_RH_DESC_A            0x48
 168 #define HC_RH_DESC_B            0x4C
 169 #define HC_RH_STATUS            0x50
 170 #define HC_RH_PORT_STATUS       0x54
 171
 172 #define USBHOST_OFFSET_UHCHR         0x64         // Usb Host reset register
 173
 174 #define OHC_BAR_INDEX               0
 175
 176 //
 177 // Usb Host controller register offset
 178 //
 179 #define USBHOST_OFFSET_UHCREV        0x0          // Usb Host revision register
 180 #define USBHOST_OFFSET_UHCHCON       0x4          // Usb Host control register
 181 #define USBHOST_OFFSET_UHCCOMS       0x8          // Usb Host Command Status register
 182 #define USBHOST_OFFSET_UHCINTS       0xC          // Usb Host Interrupt Status register
 183 #define USBHOST_OFFSET_UHCINTE       0x10         // Usb Host Interrupt Enable register
 184 #define USBHOST_OFFSET_UHCINTD       0x14         // Usb Host Interrupt Disable register
 185 #define USBHOST_OFFSET_UHCHCCA       0x18         // Usb Host Controller Communication Area
 186 #define USBHOST_OFFSET_UHCPCED       0x1C         // Usb Host Period Current Endpoint Descriptor
 187 #define USBHOST_OFFSET_UHCCHED       0x20         // Usb Host Control Head Endpoint Descriptor
 188 #define USBHOST_OFFSET_UHCCCED       0x24         // Usb Host Control Current Endpoint Descriptor
 189 #define USBHOST_OFFSET_UHCBHED       0x28         // Usb Host Bulk Head Endpoint Descriptor
 190 #define USBHOST_OFFSET_UHCBCED       0x2C         // Usb Host Bulk Current Endpoint Descriptor
 191 #define USBHOST_OFFSET_UHCDHEAD      0x30         // Usb Host Done Head register
 192 #define USBHOST_OFFSET_UHCFMI        0x34         // Usb Host Frame Interval register
 193 #define USBHOST_OFFSET_UHCFMR        0x38         // Usb Host Frame Remaining register
 194 #define USBHOST_OFFSET_UHCFMN        0x3C         // Usb Host Frame Number register
 195 #define USBHOST_OFFSET_UHCPERS       0x40         // Usb Host Periodic Start register
 196 #define USBHOST_OFFSET_UHCLST        0x44         // Usb Host Low-Speed Threshold register
 197 #define USBHOST_OFFSET_UHCRHDA       0x48         // Usb Host Root Hub Descriptor A register
 198 #define USBHOST_OFFSET_UHCRHDB       0x4C         // Usb Host Root Hub Descriptor B register
 199 #define USBHOST_OFFSET_UHCRHS        0x50         // Usb Host Root Hub Status register
 200 #define USBHOST_OFFSET_UHCRHPS1      0x54         // Usb Host Root Hub Port Status 1 register
 201
 202 //
 203 // Usb Host controller register bit fields
 204 //
 205 #pragma pack(1)
 206
 207 typedef struct {
 208   UINT8                   ProgInterface;
 209   UINT8                   SubClassCode;
 210   UINT8                   BaseCode;
 211 } USB_CLASSC;
 212
 213 typedef struct {
 214     UINT32 Revision:8;
 215     UINT32 Rsvd:24;
 216 } HcREVISION;
 217
 218 typedef struct {
 219     UINT32 ControlBulkRatio:2;
 220     UINT32 PeriodicEnable:1;
 221     UINT32 IsochronousEnable:1;
 222     UINT32 ControlEnable:1;
 223     UINT32 BulkEnable:1;
 224     UINT32 FunctionalState:2;
 225     UINT32 InterruptRouting:1;
 226     UINT32 RemoteWakeup:1;
 227     UINT32 RemoteWakeupEnable:1;
 228     UINT32 Reserved:21;
 229 } HcCONTROL;
 230
 231 typedef struct {
 232     UINT32 HcReset:1;
 233     UINT32 ControlListFilled:1;
 234     UINT32 BulkListFilled:1;
 235     UINT32 ChangeOwnerRequest:1;
 236     UINT32 Reserved1:12;
 237     UINT32 ScheduleOverrunCount:2;
 238     UINT32 Reserved:14;
 239 } HcCOMMAND_STATUS;
 240
 241 typedef struct {
 242     UINT32 SchedulingOverrun:1;
 243     UINT32 WriteBackDone:1;
 244     UINT32 Sof:1;
 245     UINT32 ResumeDetected:1;
 246     UINT32 UnrecoverableError:1;
 247     UINT32 FrameNumOverflow:1;
 248     UINT32 RHStatusChange:1;
 249     UINT32 Reserved1:23;
 250     UINT32 OwnerChange:1;
 251     UINT32 Reserved2:1;
 252 } HcINTERRUPT_STATUS;
 253
 254 typedef struct {
 255     UINT32 SchedulingOverrunInt:1;
 256     UINT32 WriteBackDoneInt:1;
 257     UINT32 SofInt:1;
 258     UINT32 ResumeDetectedInt:1;
 259     UINT32 UnrecoverableErrorInt:1;
 260     UINT32 FrameNumOverflowInt:1;
 261     UINT32 RHStatusChangeInt:1;
 262     UINT32 Reserved:23;
 263     UINT32 OwnerChangedInt:1;
 264     UINT32 MasterInterruptEnable:1;
 265 } HcINTERRUPT_CONTROL;
 266
 267 typedef struct {
 268     UINT32 Rerserved:8;
 269     UINT32 Hcca:24;
 270 } HcHCCA;
 271
 272 typedef struct {
 273     UINT32 Reserved:4;
 274     UINT32 MemoryPtr:28;
 275 } HcMEMORY_PTR;
 276
 277 typedef struct {
 278     UINT32 FrameInterval:14;
 279     UINT32 Reserved:2;
 280     UINT32 FSMaxDataPacket:15;
 281     UINT32 FrmIntervalToggle:1;
 282 } HcFRM_INTERVAL;
 283
 284 typedef struct {
 285     UINT32 FrameRemaining:14;
 286     UINT32 Reserved:17;
 287     UINT32 FrameRemainingToggle:1;
 288 } HcFRAME_REMAINING;
 289
 290 typedef struct {
 291     UINT32 FrameNumber:16;
 292     UINT32 Reserved:16;
 293 } HcFRAME_NUMBER;
 294
 295 typedef struct {
 296     UINT32 PeriodicStart:14;
 297     UINT32 Reserved:18;
 298 } HcPERIODIC_START;
 299
 300 typedef struct {
 301     UINT32 LsThreshold:12;
 302     UINT32 Reserved:20;
 303 } HcLS_THRESHOLD;
 304
 305 typedef struct {
 306     UINT32 NumDownStrmPorts:8;
 307     UINT32 PowerSwitchMode:1;
 308     UINT32 NoPowerSwitch:1;
 309     UINT32 DeviceType:1;
 310     UINT32 OverCurrentProtMode:1;
 311     UINT32 NoOverCurrentProtMode:1;
 312     UINT32 Reserved:11;
 313     UINT32 PowerOnToPowerGoodTime:8;
 314 } HcRH_DESC_A;
 315
 316 typedef struct {
 317     UINT32 DeviceRemovable:16;
 318     UINT32 PortPowerControlMask:16;
 319 } HcRH_DESC_B;
 320
 321 typedef struct {
 322     UINT32 LocalPowerStat:1;
 323     UINT32 OverCurrentIndicator:1;
 324     UINT32 Reserved1:13;
 325     UINT32 DevRemoteWakeupEnable:1;
 326     UINT32 LocalPowerStatChange:1;
 327     UINT32 OverCurrentIndicatorChange:1;
 328     UINT32 Reserved2:13;
 329     UINT32 ClearRemoteWakeupEnable:1;
 330 } HcRH_STATUS;
 331
 332 typedef struct {
 333     UINT32 CurrentConnectStat:1;
 334     UINT32 EnableStat:1;
 335     UINT32 SuspendStat:1;
 336     UINT32 OCIndicator:1;
 337     UINT32 ResetStat:1;
 338     UINT32 Reserved1:3;
 339     UINT32 PowerStat:1;
 340     UINT32 LsDeviceAttached:1;
 341     UINT32 Reserved2:6;
 342     UINT32 ConnectStatChange:1;
 343     UINT32 EnableStatChange:1;
 344     UINT32 SuspendStatChange:1;
 345     UINT32 OCIndicatorChange:1;
 346     UINT32 ResetStatChange:1;
 347     UINT32 Reserved3:11;
 348 } HcRHPORT_STATUS;
 349
 350 typedef struct {
 351     UINT32 FSBIR:1;
 352     UINT32 FHR:1;
 353     UINT32 CGR:1;
 354     UINT32 SSDC:1;
 355     UINT32 UIT:1;
 356     UINT32 SSE:1;
 357     UINT32 PSPL:1;
 358     UINT32 PCPL:1;
 359     UINT32 Reserved0:1;
 360     UINT32 SSEP1:1;
 361     UINT32 SSEP2:1;
 362     UINT32 SSEP3:1;
 363     UINT32 Reserved1:20;
 364 } HcRESET;
 365
 366
 367 #pragma pack()
 368
 369 //
 370 // Func List
 371 //
 372
 373
 374 /**
 375
 376   Get OHCI operational reg value
 377
 378   @param  PciIo                 PciIo protocol instance
 379   @param  Offset                Offset of the operational reg
 380
 381   @retval                       Value of the register
 382
 383 **/
 384 UINT32
 385 OhciGetOperationalReg (
 386   IN EFI_PCI_IO_PROTOCOL  *PciIo,
 387   IN UINT32               Offset
 388   );
 389
 390 /**
 391
 392   Set OHCI operational reg value
 393
 394   @param  PciIo                  PCI Bus Io protocol instance
 395   @param  Offset                 Offset of the operational reg
 396   @param  Value                  Value to set
 397
 398   @retval EFI_SUCCESS            Value set to the reg
 399
 400 **/
 401
 402
 403 EFI_STATUS
 404 OhciSetOperationalReg (
 405   IN EFI_PCI_IO_PROTOCOL  *PciIo,
 406   IN UINT32               Offset,
 407   IN VOID                 *Value
 408   );
 409
 410
 411 /**
 412
 413   Get HcRevision reg value
 414
 415   @param  PciIo                 PCI Bus Io protocol instance
 416
 417   @retval                       Value of the register
 418
 419 **/
 420
 421
 422 UINT32
 423 OhciGetHcRevision (
 424   IN EFI_PCI_IO_PROTOCOL  *PciIo
 425   );
 426
 427 /**
 428
 429   Set HcReset reg value
 430
 431   @param  Ohc                   UHC private data
 432   @param  Field                 Field to set
 433   @param  Value                 Value to set
 434
 435   @retval EFI_SUCCESS           Value set
 436
 437 **/
 438
 439 EFI_STATUS
 440 OhciSetHcReset (
 441   IN USB_OHCI_HC_DEV            *Ohc,
 442   IN UINT32                     Field,
 443   IN UINT32                     Value
 444   );
 445 /**
 446
 447   Get specific field of HcReset reg value
 448
 449   @param  Ohc                   UHC private data
 450   @param  Field                 Field to get
 451
 452   @retval                       Value of the field
 453
 454 **/
 455
 456 UINT32
 457 OhciGetHcReset (
 458   IN USB_OHCI_HC_DEV      *Ohc,
 459   IN UINT32               Field
 460   );
 461 /**
 462
 463   Set HcControl reg value
 464
 465   @param  Ohc                   UHC private data
 466   @param  Field                 Field to set
 467   @param  Value                 Value to set
 468
 469   @retval  EFI_SUCCESS          Value set
 470
 471 **/
 472
 473 EFI_STATUS
 474 OhciSetHcControl (
 475   IN USB_OHCI_HC_DEV      *Ohc,
 476   IN UINTN                Field,
 477   IN UINT32               Value
 478   );
 479
 480
 481 /**
 482
 483   Get specific field of HcControl reg value
 484
 485   @param  Ohc                   UHC private data
 486   @param  Field                 Field to get
 487
 488   @retval                       Value of the field
 489
 490 **/
 491
 492
 493 UINT32
 494 OhciGetHcControl (
 495   IN USB_OHCI_HC_DEV   *Ohc,
 496   IN UINTN             Field
 497   );
 498
 499
 500 /**
 501
 502   Set HcCommand reg value
 503
 504   @param  Ohc                   UHC private data
 505   @param  Field                 Field to set
 506   @param  Value                 Value to set
 507
 508   @retval EFI_SUCCESS           Value set
 509
 510 **/
 511
 512 EFI_STATUS
 513 OhciSetHcCommandStatus (
 514   IN USB_OHCI_HC_DEV      *Ohc,
 515   IN UINTN                Field,
 516   IN UINT32               Value
 517   );
 518
 519 /**
 520
 521   Get specific field of HcCommand reg value
 522
 523   @param  Ohc                   UHC private data
 524   @param  Field                 Field to get
 525
 526   @retval                       Value of the field
 527
 528 **/
 529
 530 UINT32
 531 OhciGetHcCommandStatus (
 532   IN USB_OHCI_HC_DEV      *Ohc,
 533   IN UINTN                Field
 534   );
 535
 536 /**
 537
 538   Clear specific fields of Interrupt Status
 539
 540   @param  Ohc                   UHC private data
 541   @param  Field                 Field to clear
 542
 543   @retval EFI_SUCCESS           Fields cleared
 544
 545 **/
 546
 547 EFI_STATUS
 548 OhciClearInterruptStatus (
 549   IN USB_OHCI_HC_DEV      *Ohc,
 550   IN UINTN                Field
 551   );
 552
 553 /**
 554
 555   Get fields of HcInterrupt reg value
 556
 557   @param  Ohc                   UHC private data
 558   @param  Field                 Field to get
 559
 560   @retval                       Value of the field
 561
 562 **/
 563
 564 UINT32
 565 OhciGetHcInterruptStatus (
 566   IN USB_OHCI_HC_DEV      *Ohc,
 567   IN UINTN                Field
 568   );
 569
 570 /**
 571
 572   Set Interrupt Control reg value
 573
 574   @param  Ohc                   UHC private data
 575   @param  StatEnable            Enable or Disable
 576   @param  Field                 Field to set
 577   @param  Value                 Value to set
 578
 579   @retval EFI_SUCCESS           Value set
 580
 581 **/
 582
 583 EFI_STATUS
 584 OhciSetInterruptControl (
 585   IN USB_OHCI_HC_DEV      *Ohc,
 586   IN BOOLEAN              StatEnable,
 587   IN UINTN                Field,
 588   IN UINT32               Value
 589   );
 590
 591 /**
 592
 593   Get field of HcInterruptControl reg value
 594
 595   @param  Ohc                   UHC private data
 596   @param  Field                 Field to get
 597
 598   @retval                       Value of the field
 599
 600 **/
 601
 602 UINT32
 603 OhciGetHcInterruptControl (
 604   IN USB_OHCI_HC_DEV      *Ohc,
 605   IN UINTN                Field
 606   );
 607
 608
 609 /**
 610
 611   Set memory pointer of specific type
 612
 613   @param  Ohc                   UHC private data
 614   @param  PointerType           Type of the pointer to set
 615   @param  Value                 Value to set
 616
 617   @retval EFI_SUCCESS           Memory pointer set
 618
 619 **/
 620
 621 EFI_STATUS
 622 OhciSetMemoryPointer(
 623   IN USB_OHCI_HC_DEV      *Ohc,
 624   IN UINT32               PointerType,
 625   IN VOID                 *Value
 626   );
 627
 628 /**
 629
 630   Get memory pointer of specific type
 631
 632   @param  Ohc                   UHC private data
 633   @param  PointerType           Type of pointer
 634
 635   @retval                       Memory pointer of the specific type
 636
 637 **/
 638
 639 VOID *
 640 OhciGetMemoryPointer (
 641   IN USB_OHCI_HC_DEV      *Ohc,
 642   IN UINT32               PointerType
 643   );
 644
 645 /**
 646
 647   Set Frame Interval value
 648
 649   @param  Ohc                   UHC private data
 650   @param  Field                 Field to set
 651   @param  Value                 Value to set
 652
 653   @retval  EFI_SUCCESS          Value set
 654
 655 **/
 656
 657 EFI_STATUS
 658 OhciSetFrameInterval (
 659   IN USB_OHCI_HC_DEV      *Ohc,
 660   IN UINTN                Field,
 661   IN UINT32               Value
 662   );
 663
 664
 665 /**
 666
 667   Get field of frame interval reg value
 668
 669   @param  Ohc                   UHC private data
 670   @param  Field                 Field to get
 671
 672   @retval                       Value of the field
 673
 674 **/
 675
 676 UINT32
 677 OhciGetFrameInterval (
 678   IN USB_OHCI_HC_DEV      *Ohc,
 679   IN UINTN                Field
 680   );
 681
 682
 683 /**
 684
 685   Set Frame Remaining reg value
 686
 687   @param  Ohc                   UHC private data
 688   @param  Value                 Value to set
 689
 690   @retval  EFI_SUCCESS          Value set
 691
 692 **/
 693
 694 EFI_STATUS
 695 OhciSetFrameRemaining (
 696   IN USB_OHCI_HC_DEV      *Ohc,
 697   IN UINT32               Value
 698   );
 699
 700 /**
 701
 702   Get value of frame remaining reg
 703
 704   @param  Ohc                   UHC private data
 705   @param  Field                 Field to get
 706
 707   @retval                       Value of frame remaining reg
 708
 709 **/
 710 UINT32
 711 OhciGetFrameRemaining (
 712   IN USB_OHCI_HC_DEV      *Ohc,
 713   IN UINTN                Field
 714   );
 715
 716 /**
 717
 718   Set frame number reg value
 719
 720   @param  Ohc                   UHC private data
 721   @param  Value                 Value to set
 722
 723   @retval  EFI_SUCCESS          Value set
 724
 725 **/
 726
 727 EFI_STATUS
 728 OhciSetFrameNumber(
 729   IN USB_OHCI_HC_DEV      *Ohc,
 730   IN UINT32               Value
 731   );
 732
 733 /**
 734
 735   Get frame number reg value
 736
 737   @param  Ohc                   UHC private data
 738
 739   @retval                       Value of frame number reg
 740
 741 **/
 742
 743 UINT32
 744 OhciGetFrameNumber (
 745   IN USB_OHCI_HC_DEV      *Ohc
 746   );
 747
 748
 749 /**
 750
 751   Set period start reg value
 752
 753   @param  Ohc                   UHC private data
 754   @param  Value                 Value to set
 755
 756   @retval EFI_SUCCESS           Value set
 757
 758 **/
 759
 760 EFI_STATUS
 761 OhciSetPeriodicStart (
 762   IN USB_OHCI_HC_DEV      *Ohc,
 763   IN UINT32               Value
 764   );
 765
 766
 767 /**
 768
 769   Get periodic start reg value
 770
 771   @param  Ohc                   UHC private data
 772
 773   @param                        Value of periodic start reg
 774
 775 **/
 776
 777 UINT32
 778 OhciGetPeriodicStart (
 779   IN USB_OHCI_HC_DEV      *Ohc
 780   );
 781
 782
 783 /**
 784
 785   Set Ls Threshold reg value
 786
 787   @param  Ohc                   UHC private data
 788   @param  Value                 Value to set
 789
 790   @retval  EFI_SUCCESS          Value set
 791
 792 **/
 793
 794 EFI_STATUS
 795 OhciSetLsThreshold (
 796   IN USB_OHCI_HC_DEV      *Ohc,
 797   IN UINT32               Value
 798   );
 799
 800 /**
 801
 802   Get Ls Threshold reg value
 803
 804   @param  Ohc                   UHC private data
 805
 806   @retval                       Value of Ls Threshold reg
 807
 808 **/
 809
 810 UINT32
 811 OhciGetLsThreshold (
 812   IN USB_OHCI_HC_DEV      *Ohc
 813   );
 814
 815 /**
 816
 817   Set Root Hub Descriptor reg value
 818
 819   @param  Ohc                   UHC private data
 820   @param  Field                 Field to set
 821   @param  Value                 Value to set
 822
 823   @retval  EFI_SUCCESS          Value set
 824
 825 **/
 826 EFI_STATUS
 827 OhciSetRootHubDescriptor (
 828   IN USB_OHCI_HC_DEV      *Ohc,
 829   IN UINTN                Field,
 830   IN UINT32               Value
 831   );
 832
 833
 834 /**
 835
 836   Get Root Hub Descriptor reg value
 837
 838   @param  Ohc                   UHC private data
 839   @param  Field                 Field to get
 840
 841   @retval                       Value of the field
 842
 843 **/
 844
 845 UINT32
 846 OhciGetRootHubDescriptor (
 847   IN USB_OHCI_HC_DEV     *Ohc,
 848   IN UINTN               Field
 849   );
 850
 851 /**
 852
 853   Set Root Hub Status reg value
 854
 855   @param  Ohc                   UHC private data
 856   @param  Field                 Field to set
 857
 858   @retval  EFI_SUCCESS          Value set
 859
 860 **/
 861
 862 EFI_STATUS
 863 OhciSetRootHubStatus (
 864   IN USB_OHCI_HC_DEV      *Ohc,
 865   IN UINTN                Field
 866   );
 867
 868
 869 /**
 870
 871   Get Root Hub Status reg value
 872
 873   @param  Ohc                   UHC private data
 874   @param  Field                 Field to get
 875
 876   @retval                       Value of the field
 877
 878 **/
 879
 880 UINT32
 881 OhciGetRootHubStatus (
 882   IN USB_OHCI_HC_DEV      *Ohc,
 883   IN UINTN                Field
 884   );
 885
 886
 887 /**
 888
 889   Set Root Hub Port Status reg value
 890
 891   @param  Ohc                   UHC private data
 892   @param  Index                 Index of the port
 893   @param  Field                 Field to set
 894
 895   @retval  EFI_SUCCESS          Value set
 896
 897 **/
 898
 899 EFI_STATUS
 900 OhciSetRootHubPortStatus (
 901   IN USB_OHCI_HC_DEV      *Ohc,
 902   IN UINT32               Index,
 903   IN UINTN                Field
 904   );
 905
 906
 907 /**
 908
 909   Get Root Hub Port Status reg value
 910
 911   @param  Ohc                   UHC private data
 912   @param  Index                 Index of the port
 913   @param  Field                 Field to get
 914
 915   @retval                       Value of the field and index
 916
 917 **/
 918
 919 UINT32
 920 OhciReadRootHubPortStatus (
 921   IN USB_OHCI_HC_DEV      *Ohc,
 922   IN UINT32               Index,
 923   IN UINTN                Field
 924   );
 925
 926 #endif