QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/OhciReg.h

   1 /** @file
   2 This file contains the definination for host controller
   3 register operation routines.
   4
   5 Copyright (c) 2013-2015 Intel Corporation.
   6
   7 SPDX-License-Identifier: BSD-2-Clause-Patent
   8
   9 **/
  10
  11
  12
  13 #ifndef   _OHCI_REG_H
  14 #define   _OHCI_REG_H
  15
  16 #define   HC_STATE_RESET         0x0
  17 #define   HC_STATE_RESUME        0x1
  18 #define   HC_STATE_OPERATIONAL   0x2
  19 #define   HC_STATE_SUSPEND       0x3
  20
  21 #define   PERIODIC_ENABLE               0x01
  22 #define   ISOCHRONOUS_ENABLE            0x02
  23 #define   CONTROL_ENABLE                0x04
  24 #define   BULK_ENABLE                   0x08
  25 #define   CONTROL_BULK_RATIO            0x10
  26
  27 #define   HC_FUNCTIONAL_STATE    0x20
  28 #define   INTERRUPT_ROUTING      0x40
  29
  30 #define   HC_RESET               0x01
  31 #define   CONTROL_LIST_FILLED    0x02
  32 #define   BULK_LIST_FILLED       0x04
  33 #define   CHANGE_OWNER_REQUEST   0x08
  34
  35 #define   SCHEDULE_OVERRUN_COUNT 0x10
  36
  37 #define   SCHEDULE_OVERRUN       0x00001
  38 #define   WRITEBACK_DONE_HEAD    0x00002
  39 #define   START_OF_FRAME         0x00004
  40 #define   RESUME_DETECT          0x00008
  41 #define   UNRECOVERABLE_ERROR    0x00010
  42 #define   FRAME_NUMBER_OVERFLOW  0x00020
  43 #define   ROOTHUB_STATUS_CHANGE  0x00040
  44 #define   OWNERSHIP_CHANGE       0x00080
  45
  46 #define   MASTER_INTERRUPT       0x00400
  47
  48 #define   CONTROL_HEAD           0x001
  49 #define   BULK_HEAD              0x002
  50 #define   DONE_HEAD              0x004
  51
  52 #define   Hc_HCCA                0x001
  53 #define   Hc_PERIODIC_CURRENT    0x002
  54 #define   Hc_CONTOL_HEAD         0x004
  55 #define   Hc_CONTROL_CURRENT_PTR 0x008
  56 #define   Hc_BULK_HEAD           0x010
  57 #define   Hc_BULK_CURRENT_PTR    0x020
  58 #define   Hc_DONE_HEAD           0x040
  59
  60 #define   FRAME_INTERVAL         0x008
  61 #define   FS_LARGEST_DATA_PACKET 0x010
  62 #define   FRMINT_TOGGLE          0x020
  63 #define   FRAME_REMAINING        0x040
  64 #define   FRAME_REMAIN_TOGGLE    0x080
  65
  66 #define   RH_DESC_A              0x00001
  67 #define   RH_DESC_B              0x00002
  68 #define   RH_NUM_DS_PORTS        0x00004
  69 #define   RH_NO_PSWITCH          0x00008
  70 #define   RH_PSWITCH_MODE        0x00010
  71 #define   RH_DEVICE_TYPE         0x00020
  72 #define   RH_OC_PROT_MODE        0x00040
  73 #define   RH_NOC_PROT            0x00080
  74 #define   RH_POTPGT              0x00100
  75 #define   RH_NO_POTPGT           0x00200
  76 #define   RH_DEV_REMOVABLE       0x00400
  77 #define   RH_PORT_PWR_CTRL_MASK  0x00800
  78
  79 #define   RH_LOCAL_PSTAT         0x00001
  80 #define   RH_OC_ID               0x00002
  81 #define   RH_REMOTE_WK_ENABLE    0x00004
  82 #define   RH_LOCAL_PSTAT_CHANGE  0x00008
  83 #define   RH_OC_ID_CHANGE        0x00010
  84 #define   RH_CLR_RMT_WK_ENABLE   0x00020
  85
  86 #define   RH_CLEAR_PORT_ENABLE        0x0001
  87 #define   RH_SET_PORT_ENABLE          0x0002
  88 #define   RH_SET_PORT_SUSPEND         0x0004
  89 #define   RH_CLEAR_SUSPEND_STATUS     0x0008
  90 #define   RH_SET_PORT_RESET           0x0010
  91 #define   RH_SET_PORT_POWER           0x0020
  92 #define   RH_CLEAR_PORT_POWER         0x0040
  93 #define   RH_CONNECT_STATUS_CHANGE    0x10000
  94 #define   RH_PORT_ENABLE_STAT_CHANGE  0x20000
  95 #define   RH_PORT_SUSPEND_STAT_CHANGE 0x40000
  96 #define   RH_OC_INDICATOR_CHANGE      0x80000
  97 #define   RH_PORT_RESET_STAT_CHANGE   0x100000
  98
  99 #define   RH_CURR_CONNECT_STAT        0x0001
 100 #define   RH_PORT_ENABLE_STAT         0x0002
 101 #define   RH_PORT_SUSPEND_STAT        0x0004
 102 #define   RH_PORT_OC_INDICATOR        0x0008
 103 #define   RH_PORT_RESET_STAT          0x0010
 104 #define   RH_PORT_POWER_STAT          0x0020
 105 #define   RH_LSDEVICE_ATTACHED        0x0040
 106
 107 #define   RESET_SYSTEM_BUS            (1 << 0)
 108 #define   RESET_HOST_CONTROLLER       (1 << 1)
 109 #define   RESET_CLOCK_GENERATION      (1 << 2)
 110 #define   RESET_SSE_GLOBAL            (1 << 5)
 111 #define   RESET_PSPL                  (1 << 6)
 112 #define   RESET_PCPL                  (1 << 7)
 113 #define   RESET_SSEP1                 (1 << 9)
 114 #define   RESET_SSEP2                 (1 << 10)
 115 #define   RESET_SSEP3                 (1 << 11)
 116
 117 #define ONE_SECOND                      1000000
 118 #define ONE_MILLI_SEC                   1000
 119 #define MAX_BYTES_PER_TD                0x1000
 120 #define MAX_RETRY_TIMES                 100
 121 #define PORT_NUMBER_ON_MAINSTONE2       1
 122
 123
 124 //
 125 // Operational Register Offsets
 126 //
 127
 128 //
 129 // Command & Status Registers Offsets
 130 //
 131 #define HC_REVISION             0x00
 132 #define HC_CONTROL              0x04
 133 #define HC_COMMAND_STATUS       0x08
 134 #define HC_INTERRUPT_STATUS     0x0C
 135 #define HC_INTERRUPT_ENABLE     0x10
 136 #define HC_INTERRUPT_DISABLE    0x14
 137
 138 //
 139 // Memory Pointer Offsets
 140 //
 141 #define HC_HCCA                 0x18
 142 #define HC_PERIODIC_CURRENT     0x1C
 143 #define HC_CONTROL_HEAD         0x20
 144 #define HC_CONTROL_CURRENT_PTR  0x24
 145 #define HC_BULK_HEAD            0x28
 146 #define HC_BULK_CURRENT_PTR     0x2C
 147 #define HC_DONE_HEAD            0x30
 148
 149 //
 150 // Frame Register Offsets
 151 //
 152 #define HC_FRM_INTERVAL         0x34
 153 #define HC_FRM_REMAINING        0x38
 154 #define HC_FRM_NUMBER           0x3C
 155 #define HC_PERIODIC_START       0x40
 156 #define HC_LS_THREASHOLD        0x44
 157
 158 //
 159 // Root Hub Register Offsets
 160 //
 161 #define HC_RH_DESC_A            0x48
 162 #define HC_RH_DESC_B            0x4C
 163 #define HC_RH_STATUS            0x50
 164 #define HC_RH_PORT_STATUS       0x54
 165
 166 #define USBHOST_OFFSET_UHCHR         0x64         // Usb Host reset register
 167
 168 #define OHC_BAR_INDEX               0
 169
 170 //
 171 // Usb Host controller register offset
 172 //
 173 #define USBHOST_OFFSET_UHCREV        0x0          // Usb Host revision register
 174 #define USBHOST_OFFSET_UHCHCON       0x4          // Usb Host control register
 175 #define USBHOST_OFFSET_UHCCOMS       0x8          // Usb Host Command Status register
 176 #define USBHOST_OFFSET_UHCINTS       0xC          // Usb Host Interrupt Status register
 177 #define USBHOST_OFFSET_UHCINTE       0x10         // Usb Host Interrupt Enable register
 178 #define USBHOST_OFFSET_UHCINTD       0x14         // Usb Host Interrupt Disable register
 179 #define USBHOST_OFFSET_UHCHCCA       0x18         // Usb Host Controller Communication Area
 180 #define USBHOST_OFFSET_UHCPCED       0x1C         // Usb Host Period Current Endpoint Descriptor
 181 #define USBHOST_OFFSET_UHCCHED       0x20         // Usb Host Control Head Endpoint Descriptor
 182 #define USBHOST_OFFSET_UHCCCED       0x24         // Usb Host Control Current Endpoint Descriptor
 183 #define USBHOST_OFFSET_UHCBHED       0x28         // Usb Host Bulk Head Endpoint Descriptor
 184 #define USBHOST_OFFSET_UHCBCED       0x2C         // Usb Host Bulk Current Endpoint Descriptor
 185 #define USBHOST_OFFSET_UHCDHEAD      0x30         // Usb Host Done Head register
 186 #define USBHOST_OFFSET_UHCFMI        0x34         // Usb Host Frame Interval register
 187 #define USBHOST_OFFSET_UHCFMR        0x38         // Usb Host Frame Remaining register
 188 #define USBHOST_OFFSET_UHCFMN        0x3C         // Usb Host Frame Number register
 189 #define USBHOST_OFFSET_UHCPERS       0x40         // Usb Host Periodic Start register
 190 #define USBHOST_OFFSET_UHCLST        0x44         // Usb Host Low-Speed Threshold register
 191 #define USBHOST_OFFSET_UHCRHDA       0x48         // Usb Host Root Hub Descriptor A register
 192 #define USBHOST_OFFSET_UHCRHDB       0x4C         // Usb Host Root Hub Descriptor B register
 193 #define USBHOST_OFFSET_UHCRHS        0x50         // Usb Host Root Hub Status register
 194 #define USBHOST_OFFSET_UHCRHPS1      0x54         // Usb Host Root Hub Port Status 1 register
 195
 196 //
 197 // Usb Host controller register bit fields
 198 //
 199 #pragma pack(1)
 200
 201 typedef struct {
 202   UINT8                   ProgInterface;
 203   UINT8                   SubClassCode;
 204   UINT8                   BaseCode;
 205 } USB_CLASSC;
 206
 207 typedef struct {
 208     UINT32 Revision:8;
 209     UINT32 Rsvd:24;
 210 } HcREVISION;
 211
 212 typedef struct {
 213     UINT32 ControlBulkRatio:2;
 214     UINT32 PeriodicEnable:1;
 215     UINT32 IsochronousEnable:1;
 216     UINT32 ControlEnable:1;
 217     UINT32 BulkEnable:1;
 218     UINT32 FunctionalState:2;
 219     UINT32 InterruptRouting:1;
 220     UINT32 RemoteWakeup:1;
 221     UINT32 RemoteWakeupEnable:1;
 222     UINT32 Reserved:21;
 223 } HcCONTROL;
 224
 225 typedef struct {
 226     UINT32 HcReset:1;
 227     UINT32 ControlListFilled:1;
 228     UINT32 BulkListFilled:1;
 229     UINT32 ChangeOwnerRequest:1;
 230     UINT32 Reserved1:12;
 231     UINT32 ScheduleOverrunCount:2;
 232     UINT32 Reserved:14;
 233 } HcCOMMAND_STATUS;
 234
 235 typedef struct {
 236     UINT32 SchedulingOverrun:1;
 237     UINT32 WriteBackDone:1;
 238     UINT32 Sof:1;
 239     UINT32 ResumeDetected:1;
 240     UINT32 UnrecoverableError:1;
 241     UINT32 FrameNumOverflow:1;
 242     UINT32 RHStatusChange:1;
 243     UINT32 Reserved1:23;
 244     UINT32 OwnerChange:1;
 245     UINT32 Reserved2:1;
 246 } HcINTERRUPT_STATUS;
 247
 248 typedef struct {
 249     UINT32 SchedulingOverrunInt:1;
 250     UINT32 WriteBackDoneInt:1;
 251     UINT32 SofInt:1;
 252     UINT32 ResumeDetectedInt:1;
 253     UINT32 UnrecoverableErrorInt:1;
 254     UINT32 FrameNumOverflowInt:1;
 255     UINT32 RHStatusChangeInt:1;
 256     UINT32 Reserved:23;
 257     UINT32 OwnerChangedInt:1;
 258     UINT32 MasterInterruptEnable:1;
 259 } HcINTERRUPT_CONTROL;
 260
 261 typedef struct {
 262     UINT32 Rerserved:8;
 263     UINT32 Hcca:24;
 264 } HcHCCA;
 265
 266 typedef struct {
 267     UINT32 Reserved:4;
 268     UINT32 MemoryPtr:28;
 269 } HcMEMORY_PTR;
 270
 271 typedef struct {
 272     UINT32 FrameInterval:14;
 273     UINT32 Reserved:2;
 274     UINT32 FSMaxDataPacket:15;
 275     UINT32 FrmIntervalToggle:1;
 276 } HcFRM_INTERVAL;
 277
 278 typedef struct {
 279     UINT32 FrameRemaining:14;
 280     UINT32 Reserved:17;
 281     UINT32 FrameRemainingToggle:1;
 282 } HcFRAME_REMAINING;
 283
 284 typedef struct {
 285     UINT32 FrameNumber:16;
 286     UINT32 Reserved:16;
 287 } HcFRAME_NUMBER;
 288
 289 typedef struct {
 290     UINT32 PeriodicStart:14;
 291     UINT32 Reserved:18;
 292 } HcPERIODIC_START;
 293
 294 typedef struct {
 295     UINT32 LsThreshold:12;
 296     UINT32 Reserved:20;
 297 } HcLS_THRESHOLD;
 298
 299 typedef struct {
 300     UINT32 NumDownStrmPorts:8;
 301     UINT32 PowerSwitchMode:1;
 302     UINT32 NoPowerSwitch:1;
 303     UINT32 DeviceType:1;
 304     UINT32 OverCurrentProtMode:1;
 305     UINT32 NoOverCurrentProtMode:1;
 306     UINT32 Reserved:11;
 307     UINT32 PowerOnToPowerGoodTime:8;
 308 } HcRH_DESC_A;
 309
 310 typedef struct {
 311     UINT32 DeviceRemovable:16;
 312     UINT32 PortPowerControlMask:16;
 313 } HcRH_DESC_B;
 314
 315 typedef struct {
 316     UINT32 LocalPowerStat:1;
 317     UINT32 OverCurrentIndicator:1;
 318     UINT32 Reserved1:13;
 319     UINT32 DevRemoteWakeupEnable:1;
 320     UINT32 LocalPowerStatChange:1;
 321     UINT32 OverCurrentIndicatorChange:1;
 322     UINT32 Reserved2:13;
 323     UINT32 ClearRemoteWakeupEnable:1;
 324 } HcRH_STATUS;
 325
 326 typedef struct {
 327     UINT32 CurrentConnectStat:1;
 328     UINT32 EnableStat:1;
 329     UINT32 SuspendStat:1;
 330     UINT32 OCIndicator:1;
 331     UINT32 ResetStat:1;
 332     UINT32 Reserved1:3;
 333     UINT32 PowerStat:1;
 334     UINT32 LsDeviceAttached:1;
 335     UINT32 Reserved2:6;
 336     UINT32 ConnectStatChange:1;
 337     UINT32 EnableStatChange:1;
 338     UINT32 SuspendStatChange:1;
 339     UINT32 OCIndicatorChange:1;
 340     UINT32 ResetStatChange:1;
 341     UINT32 Reserved3:11;
 342 } HcRHPORT_STATUS;
 343
 344 typedef struct {
 345     UINT32 FSBIR:1;
 346     UINT32 FHR:1;
 347     UINT32 CGR:1;
 348     UINT32 SSDC:1;
 349     UINT32 UIT:1;
 350     UINT32 SSE:1;
 351     UINT32 PSPL:1;
 352     UINT32 PCPL:1;
 353     UINT32 Reserved0:1;
 354     UINT32 SSEP1:1;
 355     UINT32 SSEP2:1;
 356     UINT32 SSEP3:1;
 357     UINT32 Reserved1:20;
 358 } HcRESET;
 359
 360
 361 #pragma pack()
 362
 363 //
 364 // Func List
 365 //
 366
 367
 368 /**
 369
 370   Get OHCI operational reg value
 371
 372   @param  PciIo                 PciIo protocol instance
 373   @param  Offset                Offset of the operational reg
 374
 375   @retval                       Value of the register
 376
 377 **/
 378 UINT32
 379 OhciGetOperationalReg (
 380   IN EFI_PCI_IO_PROTOCOL  *PciIo,
 381   IN UINT32               Offset
 382   );
 383
 384 /**
 385
 386   Set OHCI operational reg value
 387
 388   @param  PciIo                  PCI Bus Io protocol instance
 389   @param  Offset                 Offset of the operational reg
 390   @param  Value                  Value to set
 391
 392   @retval EFI_SUCCESS            Value set to the reg
 393
 394 **/
 395
 396
 397 EFI_STATUS
 398 OhciSetOperationalReg (
 399   IN EFI_PCI_IO_PROTOCOL  *PciIo,
 400   IN UINT32               Offset,
 401   IN VOID                 *Value
 402   );
 403
 404
 405 /**
 406
 407   Get HcRevision reg value
 408
 409   @param  PciIo                 PCI Bus Io protocol instance
 410
 411   @retval                       Value of the register
 412
 413 **/
 414
 415
 416 UINT32
 417 OhciGetHcRevision (
 418   IN EFI_PCI_IO_PROTOCOL  *PciIo
 419   );
 420
 421 /**
 422
 423   Set HcReset reg value
 424
 425   @param  Ohc                   UHC private data
 426   @param  Field                 Field to set
 427   @param  Value                 Value to set
 428
 429   @retval EFI_SUCCESS           Value set
 430
 431 **/
 432
 433 EFI_STATUS
 434 OhciSetHcReset (
 435   IN USB_OHCI_HC_DEV            *Ohc,
 436   IN UINT32                     Field,
 437   IN UINT32                     Value
 438   );
 439 /**
 440
 441   Get specific field of HcReset reg value
 442
 443   @param  Ohc                   UHC private data
 444   @param  Field                 Field to get
 445
 446   @retval                       Value of the field
 447
 448 **/
 449
 450 UINT32
 451 OhciGetHcReset (
 452   IN USB_OHCI_HC_DEV      *Ohc,
 453   IN UINT32               Field
 454   );
 455 /**
 456
 457   Set HcControl reg value
 458
 459   @param  Ohc                   UHC private data
 460   @param  Field                 Field to set
 461   @param  Value                 Value to set
 462
 463   @retval  EFI_SUCCESS          Value set
 464
 465 **/
 466
 467 EFI_STATUS
 468 OhciSetHcControl (
 469   IN USB_OHCI_HC_DEV      *Ohc,
 470   IN UINTN                Field,
 471   IN UINT32               Value
 472   );
 473
 474
 475 /**
 476
 477   Get specific field of HcControl reg value
 478
 479   @param  Ohc                   UHC private data
 480   @param  Field                 Field to get
 481
 482   @retval                       Value of the field
 483
 484 **/
 485
 486
 487 UINT32
 488 OhciGetHcControl (
 489   IN USB_OHCI_HC_DEV   *Ohc,
 490   IN UINTN             Field
 491   );
 492
 493
 494 /**
 495
 496   Set HcCommand reg value
 497
 498   @param  Ohc                   UHC private data
 499   @param  Field                 Field to set
 500   @param  Value                 Value to set
 501
 502   @retval EFI_SUCCESS           Value set
 503
 504 **/
 505
 506 EFI_STATUS
 507 OhciSetHcCommandStatus (
 508   IN USB_OHCI_HC_DEV      *Ohc,
 509   IN UINTN                Field,
 510   IN UINT32               Value
 511   );
 512
 513 /**
 514
 515   Get specific field of HcCommand reg value
 516
 517   @param  Ohc                   UHC private data
 518   @param  Field                 Field to get
 519
 520   @retval                       Value of the field
 521
 522 **/
 523
 524 UINT32
 525 OhciGetHcCommandStatus (
 526   IN USB_OHCI_HC_DEV      *Ohc,
 527   IN UINTN                Field
 528   );
 529
 530 /**
 531
 532   Clear specific fields of Interrupt Status
 533
 534   @param  Ohc                   UHC private data
 535   @param  Field                 Field to clear
 536
 537   @retval EFI_SUCCESS           Fields cleared
 538
 539 **/
 540
 541 EFI_STATUS
 542 OhciClearInterruptStatus (
 543   IN USB_OHCI_HC_DEV      *Ohc,
 544   IN UINTN                Field
 545   );
 546
 547 /**
 548
 549   Get fields of HcInterrupt reg value
 550
 551   @param  Ohc                   UHC private data
 552   @param  Field                 Field to get
 553
 554   @retval                       Value of the field
 555
 556 **/
 557
 558 UINT32
 559 OhciGetHcInterruptStatus (
 560   IN USB_OHCI_HC_DEV      *Ohc,
 561   IN UINTN                Field
 562   );
 563
 564 /**
 565
 566   Set Interrupt Control reg value
 567
 568   @param  Ohc                   UHC private data
 569   @param  StatEnable            Enable or Disable
 570   @param  Field                 Field to set
 571   @param  Value                 Value to set
 572
 573   @retval EFI_SUCCESS           Value set
 574
 575 **/
 576
 577 EFI_STATUS
 578 OhciSetInterruptControl (
 579   IN USB_OHCI_HC_DEV      *Ohc,
 580   IN BOOLEAN              StatEnable,
 581   IN UINTN                Field,
 582   IN UINT32               Value
 583   );
 584
 585 /**
 586
 587   Get field of HcInterruptControl reg value
 588
 589   @param  Ohc                   UHC private data
 590   @param  Field                 Field to get
 591
 592   @retval                       Value of the field
 593
 594 **/
 595
 596 UINT32
 597 OhciGetHcInterruptControl (
 598   IN USB_OHCI_HC_DEV      *Ohc,
 599   IN UINTN                Field
 600   );
 601
 602
 603 /**
 604
 605   Set memory pointer of specific type
 606
 607   @param  Ohc                   UHC private data
 608   @param  PointerType           Type of the pointer to set
 609   @param  Value                 Value to set
 610
 611   @retval EFI_SUCCESS           Memory pointer set
 612
 613 **/
 614
 615 EFI_STATUS
 616 OhciSetMemoryPointer(
 617   IN USB_OHCI_HC_DEV      *Ohc,
 618   IN UINT32               PointerType,
 619   IN VOID                 *Value
 620   );
 621
 622 /**
 623
 624   Get memory pointer of specific type
 625
 626   @param  Ohc                   UHC private data
 627   @param  PointerType           Type of pointer
 628
 629   @retval                       Memory pointer of the specific type
 630
 631 **/
 632
 633 VOID *
 634 OhciGetMemoryPointer (
 635   IN USB_OHCI_HC_DEV      *Ohc,
 636   IN UINT32               PointerType
 637   );
 638
 639 /**
 640
 641   Set Frame Interval value
 642
 643   @param  Ohc                   UHC private data
 644   @param  Field                 Field to set
 645   @param  Value                 Value to set
 646
 647   @retval  EFI_SUCCESS          Value set
 648
 649 **/
 650
 651 EFI_STATUS
 652 OhciSetFrameInterval (
 653   IN USB_OHCI_HC_DEV      *Ohc,
 654   IN UINTN                Field,
 655   IN UINT32               Value
 656   );
 657
 658
 659 /**
 660
 661   Get field of frame interval reg value
 662
 663   @param  Ohc                   UHC private data
 664   @param  Field                 Field to get
 665
 666   @retval                       Value of the field
 667
 668 **/
 669
 670 UINT32
 671 OhciGetFrameInterval (
 672   IN USB_OHCI_HC_DEV      *Ohc,
 673   IN UINTN                Field
 674   );
 675
 676
 677 /**
 678
 679   Set Frame Remaining reg value
 680
 681   @param  Ohc                   UHC private data
 682   @param  Value                 Value to set
 683
 684   @retval  EFI_SUCCESS          Value set
 685
 686 **/
 687
 688 EFI_STATUS
 689 OhciSetFrameRemaining (
 690   IN USB_OHCI_HC_DEV      *Ohc,
 691   IN UINT32               Value
 692   );
 693
 694 /**
 695
 696   Get value of frame remaining reg
 697
 698   @param  Ohc                   UHC private data
 699   @param  Field                 Field to get
 700
 701   @retval                       Value of frame remaining reg
 702
 703 **/
 704 UINT32
 705 OhciGetFrameRemaining (
 706   IN USB_OHCI_HC_DEV      *Ohc,
 707   IN UINTN                Field
 708   );
 709
 710 /**
 711
 712   Set frame number reg value
 713
 714   @param  Ohc                   UHC private data
 715   @param  Value                 Value to set
 716
 717   @retval  EFI_SUCCESS          Value set
 718
 719 **/
 720
 721 EFI_STATUS
 722 OhciSetFrameNumber(
 723   IN USB_OHCI_HC_DEV      *Ohc,
 724   IN UINT32               Value
 725   );
 726
 727 /**
 728
 729   Get frame number reg value
 730
 731   @param  Ohc                   UHC private data
 732
 733   @retval                       Value of frame number reg
 734
 735 **/
 736
 737 UINT32
 738 OhciGetFrameNumber (
 739   IN USB_OHCI_HC_DEV      *Ohc
 740   );
 741
 742
 743 /**
 744
 745   Set period start reg value
 746
 747   @param  Ohc                   UHC private data
 748   @param  Value                 Value to set
 749
 750   @retval EFI_SUCCESS           Value set
 751
 752 **/
 753
 754 EFI_STATUS
 755 OhciSetPeriodicStart (
 756   IN USB_OHCI_HC_DEV      *Ohc,
 757   IN UINT32               Value
 758   );
 759
 760
 761 /**
 762
 763   Get periodic start reg value
 764
 765   @param  Ohc                   UHC private data
 766
 767   @param                        Value of periodic start reg
 768
 769 **/
 770
 771 UINT32
 772 OhciGetPeriodicStart (
 773   IN USB_OHCI_HC_DEV      *Ohc
 774   );
 775
 776
 777 /**
 778
 779   Set Ls Threshold reg value
 780
 781   @param  Ohc                   UHC private data
 782   @param  Value                 Value to set
 783
 784   @retval  EFI_SUCCESS          Value set
 785
 786 **/
 787
 788 EFI_STATUS
 789 OhciSetLsThreshold (
 790   IN USB_OHCI_HC_DEV      *Ohc,
 791   IN UINT32               Value
 792   );
 793
 794 /**
 795
 796   Get Ls Threshold reg value
 797
 798   @param  Ohc                   UHC private data
 799
 800   @retval                       Value of Ls Threshold reg
 801
 802 **/
 803
 804 UINT32
 805 OhciGetLsThreshold (
 806   IN USB_OHCI_HC_DEV      *Ohc
 807   );
 808
 809 /**
 810
 811   Set Root Hub Descriptor reg value
 812
 813   @param  Ohc                   UHC private data
 814   @param  Field                 Field to set
 815   @param  Value                 Value to set
 816
 817   @retval  EFI_SUCCESS          Value set
 818
 819 **/
 820 EFI_STATUS
 821 OhciSetRootHubDescriptor (
 822   IN USB_OHCI_HC_DEV      *Ohc,
 823   IN UINTN                Field,
 824   IN UINT32               Value
 825   );
 826
 827
 828 /**
 829
 830   Get Root Hub Descriptor reg value
 831
 832   @param  Ohc                   UHC private data
 833   @param  Field                 Field to get
 834
 835   @retval                       Value of the field
 836
 837 **/
 838
 839 UINT32
 840 OhciGetRootHubDescriptor (
 841   IN USB_OHCI_HC_DEV     *Ohc,
 842   IN UINTN               Field
 843   );
 844
 845 /**
 846
 847   Set Root Hub Status reg value
 848
 849   @param  Ohc                   UHC private data
 850   @param  Field                 Field to set
 851
 852   @retval  EFI_SUCCESS          Value set
 853
 854 **/
 855
 856 EFI_STATUS
 857 OhciSetRootHubStatus (
 858   IN USB_OHCI_HC_DEV      *Ohc,
 859   IN UINTN                Field
 860   );
 861
 862
 863 /**
 864
 865   Get Root Hub Status reg value
 866
 867   @param  Ohc                   UHC private data
 868   @param  Field                 Field to get
 869
 870   @retval                       Value of the field
 871
 872 **/
 873
 874 UINT32
 875 OhciGetRootHubStatus (
 876   IN USB_OHCI_HC_DEV      *Ohc,
 877   IN UINTN                Field
 878   );
 879
 880
 881 /**
 882
 883   Set Root Hub Port Status reg value
 884
 885   @param  Ohc                   UHC private data
 886   @param  Index                 Index of the port
 887   @param  Field                 Field to set
 888
 889   @retval  EFI_SUCCESS          Value set
 890
 891 **/
 892
 893 EFI_STATUS
 894 OhciSetRootHubPortStatus (
 895   IN USB_OHCI_HC_DEV      *Ohc,
 896   IN UINT32               Index,
 897   IN UINTN                Field
 898   );
 899
 900
 901 /**
 902
 903   Get Root Hub Port Status reg value
 904
 905   @param  Ohc                   UHC private data
 906   @param  Index                 Index of the port
 907   @param  Field                 Field to get
 908
 909   @retval                       Value of the field and index
 910
 911 **/
 912
 913 UINT32
 914 OhciReadRootHubPortStatus (
 915   IN USB_OHCI_HC_DEV      *Ohc,
 916   IN UINT32               Index,
 917   IN UINTN                Field
 918   );
 919
 920 #endif