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[mirror_edk2.git] / SecurityPkg / Library / Tpm12DeviceLibDTpm / Tpm12Tis.c
1 /** @file
2 TIS (TPM Interface Specification) functions used by TPM1.2.
3
4 Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>
5 (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 **/
15
16 #include <Uefi.h>
17 #include <IndustryStandard/Tpm12.h>
18 #include <Library/BaseLib.h>
19 #include <Library/BaseMemoryLib.h>
20 #include <Library/IoLib.h>
21 #include <Library/TimerLib.h>
22 #include <Library/DebugLib.h>
23 #include <Library/Tpm12CommandLib.h>
24 #include <Library/PcdLib.h>
25
26 #include <IndustryStandard/TpmPtp.h>
27 #include <IndustryStandard/TpmTis.h>
28
29 typedef enum {
30 PtpInterfaceTis,
31 PtpInterfaceFifo,
32 PtpInterfaceCrb,
33 PtpInterfaceMax,
34 } PTP_INTERFACE_TYPE;
35
36 //
37 // Max TPM command/reponse length
38 //
39 #define TPMCMDBUFLENGTH 1024
40
41 /**
42 Check whether TPM chip exist.
43
44 @param[in] TisReg Pointer to TIS register.
45
46 @retval TRUE TPM chip exists.
47 @retval FALSE TPM chip is not found.
48 **/
49 BOOLEAN
50 Tpm12TisPcPresenceCheck (
51 IN TIS_PC_REGISTERS_PTR TisReg
52 )
53 {
54 UINT8 RegRead;
55
56 RegRead = MmioRead8 ((UINTN)&TisReg->Access);
57 return (BOOLEAN)(RegRead != (UINT8)-1);
58 }
59
60 /**
61 Return PTP interface type.
62
63 @param[in] Register Pointer to PTP register.
64
65 @return PTP interface type.
66 **/
67 PTP_INTERFACE_TYPE
68 Tpm12GetPtpInterface (
69 IN VOID *Register
70 )
71 {
72 PTP_CRB_INTERFACE_IDENTIFIER InterfaceId;
73 PTP_FIFO_INTERFACE_CAPABILITY InterfaceCapability;
74
75 if (!Tpm12TisPcPresenceCheck (Register)) {
76 return PtpInterfaceMax;
77 }
78 //
79 // Check interface id
80 //
81 InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
82 InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);
83
84 if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB) &&
85 (InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB) &&
86 (InterfaceId.Bits.CapCRB != 0)) {
87 return PtpInterfaceCrb;
88 }
89 if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO) &&
90 (InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO) &&
91 (InterfaceId.Bits.CapFIFO != 0) &&
92 (InterfaceCapability.Bits.InterfaceVersion == INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP)) {
93 return PtpInterfaceFifo;
94 }
95 return PtpInterfaceTis;
96 }
97
98 /**
99 Check whether the value of a TPM chip register satisfies the input BIT setting.
100
101 @param[in] Register Address port of register to be checked.
102 @param[in] BitSet Check these data bits are set.
103 @param[in] BitClear Check these data bits are clear.
104 @param[in] TimeOut The max wait time (unit MicroSecond) when checking register.
105
106 @retval EFI_SUCCESS The register satisfies the check bit.
107 @retval EFI_TIMEOUT The register can't run into the expected status in time.
108 **/
109 EFI_STATUS
110 Tpm12TisPcWaitRegisterBits (
111 IN UINT8 *Register,
112 IN UINT8 BitSet,
113 IN UINT8 BitClear,
114 IN UINT32 TimeOut
115 )
116 {
117 UINT8 RegRead;
118 UINT32 WaitTime;
119
120 for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){
121 RegRead = MmioRead8 ((UINTN)Register);
122 if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0)
123 return EFI_SUCCESS;
124 MicroSecondDelay (30);
125 }
126 return EFI_TIMEOUT;
127 }
128
129 /**
130 Get BurstCount by reading the burstCount field of a TIS regiger
131 in the time of default TIS_TIMEOUT_D.
132
133 @param[in] TisReg Pointer to TIS register.
134 @param[out] BurstCount Pointer to a buffer to store the got BurstConut.
135
136 @retval EFI_SUCCESS Get BurstCount.
137 @retval EFI_INVALID_PARAMETER TisReg is NULL or BurstCount is NULL.
138 @retval EFI_TIMEOUT BurstCount can't be got in time.
139 **/
140 EFI_STATUS
141 Tpm12TisPcReadBurstCount (
142 IN TIS_PC_REGISTERS_PTR TisReg,
143 OUT UINT16 *BurstCount
144 )
145 {
146 UINT32 WaitTime;
147 UINT8 DataByte0;
148 UINT8 DataByte1;
149
150 if (BurstCount == NULL || TisReg == NULL) {
151 return EFI_INVALID_PARAMETER;
152 }
153
154 WaitTime = 0;
155 do {
156 //
157 // TIS_PC_REGISTERS_PTR->burstCount is UINT16, but it is not 2bytes aligned,
158 // so it needs to use MmioRead8 to read two times
159 //
160 DataByte0 = MmioRead8 ((UINTN)&TisReg->BurstCount);
161 DataByte1 = MmioRead8 ((UINTN)&TisReg->BurstCount + 1);
162 *BurstCount = (UINT16)((DataByte1 << 8) + DataByte0);
163 if (*BurstCount != 0) {
164 return EFI_SUCCESS;
165 }
166 MicroSecondDelay (30);
167 WaitTime += 30;
168 } while (WaitTime < TIS_TIMEOUT_D);
169
170 return EFI_TIMEOUT;
171 }
172
173 /**
174 Set TPM chip to ready state by sending ready command TIS_PC_STS_READY
175 to Status Register in time.
176
177 @param[in] TisReg Pointer to TIS register.
178
179 @retval EFI_SUCCESS TPM chip enters into ready state.
180 @retval EFI_INVALID_PARAMETER TisReg is NULL.
181 @retval EFI_TIMEOUT TPM chip can't be set to ready state in time.
182 **/
183 EFI_STATUS
184 Tpm12TisPcPrepareCommand (
185 IN TIS_PC_REGISTERS_PTR TisReg
186 )
187 {
188 EFI_STATUS Status;
189
190 if (TisReg == NULL) {
191 return EFI_INVALID_PARAMETER;
192 }
193
194 MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);
195 Status = Tpm12TisPcWaitRegisterBits (
196 &TisReg->Status,
197 TIS_PC_STS_READY,
198 0,
199 TIS_TIMEOUT_B
200 );
201 return Status;
202 }
203
204 /**
205 Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE
206 to ACCESS Register in the time of default TIS_TIMEOUT_A.
207
208 @param[in] TisReg Pointer to TIS register.
209
210 @retval EFI_SUCCESS Get the control of TPM chip.
211 @retval EFI_INVALID_PARAMETER TisReg is NULL.
212 @retval EFI_NOT_FOUND TPM chip doesn't exit.
213 @retval EFI_TIMEOUT Can't get the TPM control in time.
214 **/
215 EFI_STATUS
216 Tpm12TisPcRequestUseTpm (
217 IN TIS_PC_REGISTERS_PTR TisReg
218 )
219 {
220 EFI_STATUS Status;
221
222 if (TisReg == NULL) {
223 return EFI_INVALID_PARAMETER;
224 }
225
226 if (!Tpm12TisPcPresenceCheck (TisReg)) {
227 return EFI_NOT_FOUND;
228 }
229
230 MmioWrite8((UINTN)&TisReg->Access, TIS_PC_ACC_RQUUSE);
231 Status = Tpm12TisPcWaitRegisterBits (
232 &TisReg->Access,
233 (UINT8)(TIS_PC_ACC_ACTIVE |TIS_PC_VALID),
234 0,
235 TIS_TIMEOUT_A
236 );
237 return Status;
238 }
239
240 /**
241 Send a command to TPM for execution and return response data.
242
243 @param[in] TisReg TPM register space base address.
244 @param[in] BufferIn Buffer for command data.
245 @param[in] SizeIn Size of command data.
246 @param[in, out] BufferOut Buffer for response data.
247 @param[in, out] SizeOut Size of response data.
248
249 @retval EFI_SUCCESS Operation completed successfully.
250 @retval EFI_BUFFER_TOO_SMALL Response data buffer is too small.
251 @retval EFI_DEVICE_ERROR Unexpected device behavior.
252 @retval EFI_UNSUPPORTED Unsupported TPM version
253
254 **/
255 EFI_STATUS
256 Tpm12TisTpmCommand (
257 IN TIS_PC_REGISTERS_PTR TisReg,
258 IN UINT8 *BufferIn,
259 IN UINT32 SizeIn,
260 IN OUT UINT8 *BufferOut,
261 IN OUT UINT32 *SizeOut
262 )
263 {
264 EFI_STATUS Status;
265 UINT16 BurstCount;
266 UINT32 Index;
267 UINT32 TpmOutSize;
268 UINT16 Data16;
269 UINT32 Data32;
270
271 DEBUG_CODE (
272 UINTN DebugSize;
273
274 DEBUG ((EFI_D_VERBOSE, "Tpm12TisTpmCommand Send - "));
275 if (SizeIn > 0x100) {
276 DebugSize = 0x40;
277 } else {
278 DebugSize = SizeIn;
279 }
280 for (Index = 0; Index < DebugSize; Index++) {
281 DEBUG ((EFI_D_VERBOSE, "%02x ", BufferIn[Index]));
282 }
283 if (DebugSize != SizeIn) {
284 DEBUG ((EFI_D_VERBOSE, "...... "));
285 for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {
286 DEBUG ((EFI_D_VERBOSE, "%02x ", BufferIn[Index]));
287 }
288 }
289 DEBUG ((EFI_D_VERBOSE, "\n"));
290 );
291 TpmOutSize = 0;
292
293 Status = Tpm12TisPcPrepareCommand (TisReg);
294 if (EFI_ERROR (Status)){
295 DEBUG ((DEBUG_ERROR, "Tpm12 is not ready for command!\n"));
296 return EFI_DEVICE_ERROR;
297 }
298 //
299 // Send the command data to Tpm
300 //
301 Index = 0;
302 while (Index < SizeIn) {
303 Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);
304 if (EFI_ERROR (Status)) {
305 Status = EFI_DEVICE_ERROR;
306 goto Exit;
307 }
308 for (; BurstCount > 0 && Index < SizeIn; BurstCount--) {
309 MmioWrite8((UINTN)&TisReg->DataFifo, *(BufferIn + Index));
310 Index++;
311 }
312 }
313 //
314 // Check the Tpm status STS_EXPECT change from 1 to 0
315 //
316 Status = Tpm12TisPcWaitRegisterBits (
317 &TisReg->Status,
318 (UINT8) TIS_PC_VALID,
319 TIS_PC_STS_EXPECT,
320 TIS_TIMEOUT_C
321 );
322 if (EFI_ERROR (Status)) {
323 DEBUG ((DEBUG_ERROR, "Tpm12 The send buffer too small!\n"));
324 Status = EFI_BUFFER_TOO_SMALL;
325 goto Exit;
326 }
327 //
328 // Executed the TPM command and waiting for the response data ready
329 //
330 MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_GO);
331 Status = Tpm12TisPcWaitRegisterBits (
332 &TisReg->Status,
333 (UINT8) (TIS_PC_VALID | TIS_PC_STS_DATA),
334 0,
335 TIS_TIMEOUT_B
336 );
337 if (EFI_ERROR (Status)) {
338 DEBUG ((DEBUG_ERROR, "Wait for Tpm12 response data time out!!\n"));
339 Status = EFI_DEVICE_ERROR;
340 goto Exit;
341 }
342 //
343 // Get response data header
344 //
345 Index = 0;
346 BurstCount = 0;
347 while (Index < sizeof (TPM_RSP_COMMAND_HDR)) {
348 Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);
349 if (EFI_ERROR (Status)) {
350 Status = EFI_DEVICE_ERROR;
351 goto Exit;
352 }
353 for (; BurstCount > 0; BurstCount--) {
354 *(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);
355 Index++;
356 if (Index == sizeof (TPM_RSP_COMMAND_HDR)) break;
357 }
358 }
359 DEBUG_CODE (
360 DEBUG ((EFI_D_VERBOSE, "Tpm12TisTpmCommand ReceiveHeader - "));
361 for (Index = 0; Index < sizeof (TPM_RSP_COMMAND_HDR); Index++) {
362 DEBUG ((EFI_D_VERBOSE, "%02x ", BufferOut[Index]));
363 }
364 DEBUG ((EFI_D_VERBOSE, "\n"));
365 );
366 //
367 // Check the reponse data header (tag,parasize and returncode )
368 //
369 CopyMem (&Data16, BufferOut, sizeof (UINT16));
370 if (SwapBytes16 (Data16) != TPM_TAG_RSP_COMMAND) {
371 DEBUG ((EFI_D_ERROR, "TPM12: TPM_ST_RSP error - %x\n", TPM_TAG_RSP_COMMAND));
372 Status = EFI_UNSUPPORTED;
373 goto Exit;
374 }
375
376 CopyMem (&Data32, (BufferOut + 2), sizeof (UINT32));
377 TpmOutSize = SwapBytes32 (Data32);
378 if (*SizeOut < TpmOutSize) {
379 Status = EFI_BUFFER_TOO_SMALL;
380 goto Exit;
381 }
382 *SizeOut = TpmOutSize;
383 //
384 // Continue reading the remaining data
385 //
386 while ( Index < TpmOutSize ) {
387 for (; BurstCount > 0; BurstCount--) {
388 *(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);
389 Index++;
390 if (Index == TpmOutSize) {
391 Status = EFI_SUCCESS;
392 goto Exit;
393 }
394 }
395 Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);
396 if (EFI_ERROR (Status)) {
397 Status = EFI_DEVICE_ERROR;
398 goto Exit;
399 }
400 }
401 Exit:
402 DEBUG_CODE (
403 DEBUG ((EFI_D_VERBOSE, "Tpm12TisTpmCommand Receive - "));
404 for (Index = 0; Index < TpmOutSize; Index++) {
405 DEBUG ((EFI_D_VERBOSE, "%02x ", BufferOut[Index]));
406 }
407 DEBUG ((EFI_D_VERBOSE, "\n"));
408 );
409 MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);
410 return Status;
411 }
412
413 /**
414 This service enables the sending of commands to the TPM12.
415
416 @param[in] InputParameterBlockSize Size of the TPM12 input parameter block.
417 @param[in] InputParameterBlock Pointer to the TPM12 input parameter block.
418 @param[in,out] OutputParameterBlockSize Size of the TPM12 output parameter block.
419 @param[in] OutputParameterBlock Pointer to the TPM12 output parameter block.
420
421 @retval EFI_SUCCESS The command byte stream was successfully sent to the device and a response was successfully received.
422 @retval EFI_DEVICE_ERROR The command was not successfully sent to the device or a response was not successfully received from the device.
423 @retval EFI_BUFFER_TOO_SMALL The output parameter block is too small.
424 **/
425 EFI_STATUS
426 EFIAPI
427 Tpm12SubmitCommand (
428 IN UINT32 InputParameterBlockSize,
429 IN UINT8 *InputParameterBlock,
430 IN OUT UINT32 *OutputParameterBlockSize,
431 IN UINT8 *OutputParameterBlock
432 )
433 {
434 PTP_INTERFACE_TYPE PtpInterface;
435
436 //
437 // Special handle for TPM1.2 to check PTP too, because PTP/TIS share same register address.
438 //
439 PtpInterface = Tpm12GetPtpInterface ((VOID *) (UINTN) PcdGet64 (PcdTpmBaseAddress));
440 switch (PtpInterface) {
441 case PtpInterfaceFifo:
442 case PtpInterfaceTis:
443 return Tpm12TisTpmCommand (
444 (TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),
445 InputParameterBlock,
446 InputParameterBlockSize,
447 OutputParameterBlock,
448 OutputParameterBlockSize
449 );
450 case PtpInterfaceCrb:
451 //
452 // No need to support CRB because it is only accept TPM2 command.
453 //
454 default:
455 return EFI_DEVICE_ERROR;
456 }
457
458 }
459
460 /**
461 Check whether the value of a TPM chip register satisfies the input BIT setting.
462
463 @param[in] Register Address port of register to be checked.
464 @param[in] BitSet Check these data bits are set.
465 @param[in] BitClear Check these data bits are clear.
466 @param[in] TimeOut The max wait time (unit MicroSecond) when checking register.
467
468 @retval EFI_SUCCESS The register satisfies the check bit.
469 @retval EFI_TIMEOUT The register can't run into the expected status in time.
470 **/
471 EFI_STATUS
472 Tpm12PtpCrbWaitRegisterBits (
473 IN UINT32 *Register,
474 IN UINT32 BitSet,
475 IN UINT32 BitClear,
476 IN UINT32 TimeOut
477 )
478 {
479 UINT32 RegRead;
480 UINT32 WaitTime;
481
482 for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){
483 RegRead = MmioRead32 ((UINTN)Register);
484 if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0) {
485 return EFI_SUCCESS;
486 }
487 MicroSecondDelay (30);
488 }
489 return EFI_TIMEOUT;
490 }
491
492 /**
493 Get the control of TPM chip.
494
495 @param[in] CrbReg Pointer to CRB register.
496
497 @retval EFI_SUCCESS Get the control of TPM chip.
498 @retval EFI_INVALID_PARAMETER CrbReg is NULL.
499 @retval EFI_NOT_FOUND TPM chip doesn't exit.
500 @retval EFI_TIMEOUT Can't get the TPM control in time.
501 **/
502 EFI_STATUS
503 Tpm12PtpCrbRequestUseTpm (
504 IN PTP_CRB_REGISTERS_PTR CrbReg
505 )
506 {
507 EFI_STATUS Status;
508
509 MmioWrite32((UINTN)&CrbReg->LocalityControl, PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS);
510 Status = Tpm12PtpCrbWaitRegisterBits (
511 &CrbReg->LocalityStatus,
512 PTP_CRB_LOCALITY_STATUS_GRANTED,
513 0,
514 PTP_TIMEOUT_A
515 );
516 return Status;
517 }
518
519 /**
520 This service requests use TPM12.
521
522 @retval EFI_SUCCESS Get the control of TPM12 chip.
523 @retval EFI_NOT_FOUND TPM12 not found.
524 @retval EFI_DEVICE_ERROR Unexpected device behavior.
525 **/
526 EFI_STATUS
527 EFIAPI
528 Tpm12RequestUseTpm (
529 VOID
530 )
531 {
532 PTP_INTERFACE_TYPE PtpInterface;
533
534 //
535 // Special handle for TPM1.2 to check PTP too, because PTP/TIS share same register address.
536 // Some other program might leverage this function to check the existence of TPM chip.
537 //
538 PtpInterface = Tpm12GetPtpInterface ((VOID *) (UINTN) PcdGet64 (PcdTpmBaseAddress));
539 switch (PtpInterface) {
540 case PtpInterfaceCrb:
541 return Tpm12PtpCrbRequestUseTpm ((PTP_CRB_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));
542 case PtpInterfaceFifo:
543 case PtpInterfaceTis:
544 return Tpm12TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));
545 default:
546 return EFI_NOT_FOUND;
547 }
548 }
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