SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Ptp.c

   1 /** @file
   2   PTP (Platform TPM Profile) CRB (Command Response Buffer) interface used by dTPM2.0 library.
   3
   4 Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
   5 Copyright (c), Microsoft Corporation.
   6 SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9
  10 #include <IndustryStandard/Tpm20.h>
  11
  12 #include <Library/BaseLib.h>
  13 #include <Library/BaseMemoryLib.h>
  14 #include <Library/IoLib.h>
  15 #include <Library/TimerLib.h>
  16 #include <Library/DebugLib.h>
  17 #include <Library/Tpm2DeviceLib.h>
  18 #include <Library/PcdLib.h>
  19
  20 #include <IndustryStandard/TpmPtp.h>
  21 #include <IndustryStandard/TpmTis.h>
  22
  23 #include "Tpm2DeviceLibDTpm.h"
  24
  25 //
  26 // Execution of the command may take from several seconds to minutes for certain
  27 // commands, such as key generation.
  28 //
  29 #define PTP_TIMEOUT_MAX  (90000 * 1000)             // 90s
  30
  31 //
  32 // Max TPM command/response length
  33 //
  34 #define TPMCMDBUFLENGTH  0x500
  35
  36 /**
  37   Check whether TPM PTP register exist.
  38
  39   @param[in] Reg  Pointer to PTP register.
  40
  41   @retval    TRUE    TPM PTP exists.
  42   @retval    FALSE   TPM PTP is not found.
  43 **/
  44 BOOLEAN
  45 Tpm2IsPtpPresence (
  46   IN VOID  *Reg
  47   )
  48 {
  49   UINT8  RegRead;
  50
  51   RegRead = MmioRead8 ((UINTN)Reg);
  52   if (RegRead == 0xFF) {
  53     //
  54     // No TPM chip
  55     //
  56     return FALSE;
  57   }
  58
  59   return TRUE;
  60 }
  61
  62 /**
  63   Check whether the value of a TPM chip register satisfies the input BIT setting.
  64
  65   @param[in]  Register     Address port of register to be checked.
  66   @param[in]  BitSet       Check these data bits are set.
  67   @param[in]  BitClear     Check these data bits are clear.
  68   @param[in]  TimeOut      The max wait time (unit MicroSecond) when checking register.
  69
  70   @retval     EFI_SUCCESS  The register satisfies the check bit.
  71   @retval     EFI_TIMEOUT  The register can't run into the expected status in time.
  72 **/
  73 EFI_STATUS
  74 PtpCrbWaitRegisterBits (
  75   IN      UINT32  *Register,
  76   IN      UINT32  BitSet,
  77   IN      UINT32  BitClear,
  78   IN      UINT32  TimeOut
  79   )
  80 {
  81   UINT32  RegRead;
  82   UINT32  WaitTime;
  83
  84   for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30) {
  85     RegRead = MmioRead32 ((UINTN)Register);
  86     if (((RegRead & BitSet) == BitSet) && ((RegRead & BitClear) == 0)) {
  87       return EFI_SUCCESS;
  88     }
  89
  90     MicroSecondDelay (30);
  91   }
  92
  93   return EFI_TIMEOUT;
  94 }
  95
  96 /**
  97   Get the control of TPM chip.
  98
  99   @param[in] CrbReg                Pointer to CRB register.
 100
 101   @retval    EFI_SUCCESS           Get the control of TPM chip.
 102   @retval    EFI_INVALID_PARAMETER CrbReg is NULL.
 103   @retval    EFI_NOT_FOUND         TPM chip doesn't exit.
 104   @retval    EFI_TIMEOUT           Can't get the TPM control in time.
 105 **/
 106 EFI_STATUS
 107 PtpCrbRequestUseTpm (
 108   IN      PTP_CRB_REGISTERS_PTR  CrbReg
 109   )
 110 {
 111   EFI_STATUS  Status;
 112
 113   if (!Tpm2IsPtpPresence (CrbReg)) {
 114     return EFI_NOT_FOUND;
 115   }
 116
 117   MmioWrite32 ((UINTN)&CrbReg->LocalityControl, PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS);
 118   Status = PtpCrbWaitRegisterBits (
 119              &CrbReg->LocalityStatus,
 120              PTP_CRB_LOCALITY_STATUS_GRANTED,
 121              0,
 122              PTP_TIMEOUT_A
 123              );
 124   return Status;
 125 }
 126
 127 /**
 128   Send a command to TPM for execution and return response data.
 129
 130   @param[in]      CrbReg        TPM register space base address.
 131   @param[in]      BufferIn      Buffer for command data.
 132   @param[in]      SizeIn        Size of command data.
 133   @param[in, out] BufferOut     Buffer for response data.
 134   @param[in, out] SizeOut       Size of response data.
 135
 136   @retval EFI_SUCCESS           Operation completed successfully.
 137   @retval EFI_BUFFER_TOO_SMALL  Response data buffer is too small.
 138   @retval EFI_DEVICE_ERROR      Unexpected device behavior.
 139   @retval EFI_UNSUPPORTED       Unsupported TPM version
 140
 141 **/
 142 EFI_STATUS
 143 PtpCrbTpmCommand (
 144   IN     PTP_CRB_REGISTERS_PTR  CrbReg,
 145   IN     UINT8                  *BufferIn,
 146   IN     UINT32                 SizeIn,
 147   IN OUT UINT8                  *BufferOut,
 148   IN OUT UINT32                 *SizeOut
 149   )
 150 {
 151   EFI_STATUS  Status;
 152   UINT32      Index;
 153   UINT32      TpmOutSize;
 154   UINT16      Data16;
 155   UINT32      Data32;
 156
 157   DEBUG_CODE_BEGIN ();
 158   UINTN  DebugSize;
 159
 160   DEBUG ((DEBUG_VERBOSE, "PtpCrbTpmCommand Send - "));
 161   if (SizeIn > 0x100) {
 162     DebugSize = 0x40;
 163   } else {
 164     DebugSize = SizeIn;
 165   }
 166
 167   for (Index = 0; Index < DebugSize; Index++) {
 168     DEBUG ((DEBUG_VERBOSE, "%02x ", BufferIn[Index]));
 169   }
 170
 171   if (DebugSize != SizeIn) {
 172     DEBUG ((DEBUG_VERBOSE, "...... "));
 173     for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {
 174       DEBUG ((DEBUG_VERBOSE, "%02x ", BufferIn[Index]));
 175     }
 176   }
 177
 178   DEBUG ((DEBUG_VERBOSE, "\n"));
 179   DEBUG_CODE_END ();
 180   TpmOutSize = 0;
 181
 182   //
 183   // STEP 0:
 184   // if CapCRbIdelByPass == 0, enforce Idle state before sending command
 185   //
 186   if ((GetCachedIdleByPass () == 0) && ((MmioRead32 ((UINTN)&CrbReg->CrbControlStatus) & PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE) == 0)) {
 187     Status = PtpCrbWaitRegisterBits (
 188                &CrbReg->CrbControlStatus,
 189                PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE,
 190                0,
 191                PTP_TIMEOUT_C
 192                );
 193     if (EFI_ERROR (Status)) {
 194       //
 195       // Try to goIdle to recover TPM
 196       //
 197       Status = EFI_DEVICE_ERROR;
 198       goto GoIdle_Exit;
 199     }
 200   }
 201
 202   //
 203   // STEP 1:
 204   // Ready is any time the TPM is ready to receive a command, following a write
 205   // of 1 by software to Request.cmdReady, as indicated by the Status field
 206   // being cleared to 0.
 207   //
 208   MmioWrite32 ((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY);
 209   Status = PtpCrbWaitRegisterBits (
 210              &CrbReg->CrbControlRequest,
 211              0,
 212              PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY,
 213              PTP_TIMEOUT_C
 214              );
 215   if (EFI_ERROR (Status)) {
 216     Status = EFI_DEVICE_ERROR;
 217     goto GoIdle_Exit;
 218   }
 219
 220   Status = PtpCrbWaitRegisterBits (
 221              &CrbReg->CrbControlStatus,
 222              0,
 223              PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE,
 224              PTP_TIMEOUT_C
 225              );
 226   if (EFI_ERROR (Status)) {
 227     Status = EFI_DEVICE_ERROR;
 228     goto GoIdle_Exit;
 229   }
 230
 231   //
 232   // STEP 2:
 233   // Command Reception occurs following a Ready state between the write of the
 234   // first byte of a command to the Command Buffer and the receipt of a write
 235   // of 1 to Start.
 236   //
 237   for (Index = 0; Index < SizeIn; Index++) {
 238     MmioWrite8 ((UINTN)&CrbReg->CrbDataBuffer[Index], BufferIn[Index]);
 239   }
 240
 241   MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandAddressHigh, (UINT32)RShiftU64 ((UINTN)CrbReg->CrbDataBuffer, 32));
 242   MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandAddressLow, (UINT32)(UINTN)CrbReg->CrbDataBuffer);
 243   MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandSize, sizeof (CrbReg->CrbDataBuffer));
 244
 245   MmioWrite64 ((UINTN)&CrbReg->CrbControlResponseAddrss, (UINT32)(UINTN)CrbReg->CrbDataBuffer);
 246   MmioWrite32 ((UINTN)&CrbReg->CrbControlResponseSize, sizeof (CrbReg->CrbDataBuffer));
 247
 248   //
 249   // STEP 3:
 250   // Command Execution occurs after receipt of a 1 to Start and the TPM
 251   // clearing Start to 0.
 252   //
 253   MmioWrite32 ((UINTN)&CrbReg->CrbControlStart, PTP_CRB_CONTROL_START);
 254   Status = PtpCrbWaitRegisterBits (
 255              &CrbReg->CrbControlStart,
 256              0,
 257              PTP_CRB_CONTROL_START,
 258              PTP_TIMEOUT_MAX
 259              );
 260   if (EFI_ERROR (Status)) {
 261     //
 262     // Command Completion check timeout. Cancel the currently executing command by writing TPM_CRB_CTRL_CANCEL,
 263     // Expect TPM_RC_CANCELLED or successfully completed response.
 264     //
 265     MmioWrite32 ((UINTN)&CrbReg->CrbControlCancel, PTP_CRB_CONTROL_CANCEL);
 266     Status = PtpCrbWaitRegisterBits (
 267                &CrbReg->CrbControlStart,
 268                0,
 269                PTP_CRB_CONTROL_START,
 270                PTP_TIMEOUT_B
 271                );
 272     MmioWrite32 ((UINTN)&CrbReg->CrbControlCancel, 0);
 273
 274     if (EFI_ERROR (Status)) {
 275       //
 276       // Still in Command Execution state. Try to goIdle, the behavior is agnostic.
 277       //
 278       Status = EFI_DEVICE_ERROR;
 279       goto GoIdle_Exit;
 280     }
 281   }
 282
 283   //
 284   // STEP 4:
 285   // Command Completion occurs after completion of a command (indicated by the
 286   // TPM clearing TPM_CRB_CTRL_Start_x to 0) and before a write of a 1 by the
 287   // software to Request.goIdle.
 288   //
 289
 290   //
 291   // Get response data header
 292   //
 293   for (Index = 0; Index < sizeof (TPM2_RESPONSE_HEADER); Index++) {
 294     BufferOut[Index] = MmioRead8 ((UINTN)&CrbReg->CrbDataBuffer[Index]);
 295   }
 296
 297   DEBUG_CODE_BEGIN ();
 298   DEBUG ((DEBUG_VERBOSE, "PtpCrbTpmCommand ReceiveHeader - "));
 299   for (Index = 0; Index < sizeof (TPM2_RESPONSE_HEADER); Index++) {
 300     DEBUG ((DEBUG_VERBOSE, "%02x ", BufferOut[Index]));
 301   }
 302
 303   DEBUG ((DEBUG_VERBOSE, "\n"));
 304   DEBUG_CODE_END ();
 305   //
 306   // Check the response data header (tag, parasize and returncode)
 307   //
 308   CopyMem (&Data16, BufferOut, sizeof (UINT16));
 309   // TPM2 should not use this RSP_COMMAND
 310   if (SwapBytes16 (Data16) == TPM_ST_RSP_COMMAND) {
 311     DEBUG ((DEBUG_ERROR, "TPM2: TPM_ST_RSP error - %x\n", TPM_ST_RSP_COMMAND));
 312     Status = EFI_UNSUPPORTED;
 313     goto GoIdle_Exit;
 314   }
 315
 316   CopyMem (&Data32, (BufferOut + 2), sizeof (UINT32));
 317   TpmOutSize = SwapBytes32 (Data32);
 318   if (*SizeOut < TpmOutSize) {
 319     //
 320     // Command completed, but buffer is not enough
 321     //
 322     Status = EFI_BUFFER_TOO_SMALL;
 323     goto GoReady_Exit;
 324   }
 325
 326   *SizeOut = TpmOutSize;
 327   //
 328   // Continue reading the remaining data
 329   //
 330   for (Index = sizeof (TPM2_RESPONSE_HEADER); Index < TpmOutSize; Index++) {
 331     BufferOut[Index] = MmioRead8 ((UINTN)&CrbReg->CrbDataBuffer[Index]);
 332   }
 333
 334   DEBUG_CODE_BEGIN ();
 335   DEBUG ((DEBUG_VERBOSE, "PtpCrbTpmCommand Receive - "));
 336   for (Index = 0; Index < TpmOutSize; Index++) {
 337     DEBUG ((DEBUG_VERBOSE, "%02x ", BufferOut[Index]));
 338   }
 339
 340   DEBUG ((DEBUG_VERBOSE, "\n"));
 341   DEBUG_CODE_END ();
 342
 343 GoReady_Exit:
 344   //
 345   // Goto Ready State if command is completed successfully and TPM support IdleBypass
 346   // If not supported. flow down to GoIdle
 347   //
 348   if (GetCachedIdleByPass () == 1) {
 349     MmioWrite32 ((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY);
 350     return Status;
 351   }
 352
 353   //
 354   // Do not wait for state transition for TIMEOUT_C
 355   // This function will try to wait 2 TIMEOUT_C at the beginning in next call.
 356   //
 357 GoIdle_Exit:
 358
 359   //
 360   //  Return to Idle state by setting TPM_CRB_CTRL_STS_x.Status.goIdle to 1.
 361   //
 362   MmioWrite32 ((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE);
 363
 364   //
 365   // Only enforce Idle state transition if execution fails when CRBIdleBypass==1
 366   // Leave regular Idle delay at the beginning of next command execution
 367   //
 368   if (GetCachedIdleByPass () == 1) {
 369     Status = PtpCrbWaitRegisterBits (
 370                &CrbReg->CrbControlStatus,
 371                PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE,
 372                0,
 373                PTP_TIMEOUT_C
 374                );
 375   }
 376
 377   return Status;
 378 }
 379
 380 /**
 381   Send a command to TPM for execution and return response data.
 382
 383   @param[in]      TisReg        TPM register space base address.
 384   @param[in]      BufferIn      Buffer for command data.
 385   @param[in]      SizeIn        Size of command data.
 386   @param[in, out] BufferOut     Buffer for response data.
 387   @param[in, out] SizeOut       Size of response data.
 388
 389   @retval EFI_SUCCESS           Operation completed successfully.
 390   @retval EFI_BUFFER_TOO_SMALL  Response data buffer is too small.
 391   @retval EFI_DEVICE_ERROR      Unexpected device behavior.
 392   @retval EFI_UNSUPPORTED       Unsupported TPM version
 393
 394 **/
 395 EFI_STATUS
 396 Tpm2TisTpmCommand (
 397   IN     TIS_PC_REGISTERS_PTR  TisReg,
 398   IN     UINT8                 *BufferIn,
 399   IN     UINT32                SizeIn,
 400   IN OUT UINT8                 *BufferOut,
 401   IN OUT UINT32                *SizeOut
 402   );
 403
 404 /**
 405   Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE
 406   to ACCESS Register in the time of default TIS_TIMEOUT_A.
 407
 408   @param[in] TisReg                Pointer to TIS register.
 409
 410   @retval    EFI_SUCCESS           Get the control of TPM chip.
 411   @retval    EFI_INVALID_PARAMETER TisReg is NULL.
 412   @retval    EFI_NOT_FOUND         TPM chip doesn't exit.
 413   @retval    EFI_TIMEOUT           Can't get the TPM control in time.
 414 **/
 415 EFI_STATUS
 416 TisPcRequestUseTpm (
 417   IN     TIS_PC_REGISTERS_PTR  TisReg
 418   );
 419
 420 /**
 421   Return PTP interface type.
 422
 423   @param[in] Register                Pointer to PTP register.
 424
 425   @return PTP interface type.
 426 **/
 427 TPM2_PTP_INTERFACE_TYPE
 428 Tpm2GetPtpInterface (
 429   IN VOID  *Register
 430   )
 431 {
 432   PTP_CRB_INTERFACE_IDENTIFIER   InterfaceId;
 433   PTP_FIFO_INTERFACE_CAPABILITY  InterfaceCapability;
 434
 435   if (!Tpm2IsPtpPresence (Register)) {
 436     return Tpm2PtpInterfaceMax;
 437   }
 438
 439   //
 440   // Check interface id
 441   //
 442   InterfaceId.Uint32         = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
 443   InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);
 444
 445   if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB) &&
 446       (InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB) &&
 447       (InterfaceId.Bits.CapCRB != 0))
 448   {
 449     return Tpm2PtpInterfaceCrb;
 450   }
 451
 452   if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO) &&
 453       (InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO) &&
 454       (InterfaceId.Bits.CapFIFO != 0) &&
 455       (InterfaceCapability.Bits.InterfaceVersion == INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP))
 456   {
 457     return Tpm2PtpInterfaceFifo;
 458   }
 459
 460   return Tpm2PtpInterfaceTis;
 461 }
 462
 463 /**
 464   Return PTP CRB interface IdleByPass state.
 465
 466   @param[in] Register                Pointer to PTP register.
 467
 468   @return PTP CRB interface IdleByPass state.
 469 **/
 470 UINT8
 471 Tpm2GetIdleByPass (
 472   IN VOID  *Register
 473   )
 474 {
 475   PTP_CRB_INTERFACE_IDENTIFIER  InterfaceId;
 476
 477   //
 478   // Check interface id
 479   //
 480   InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
 481
 482   return (UINT8)(InterfaceId.Bits.CapCRBIdleBypass);
 483 }
 484
 485 /**
 486   Dump PTP register information.
 487
 488   @param[in] Register                Pointer to PTP register.
 489 **/
 490 VOID
 491 DumpPtpInfo (
 492   IN VOID  *Register
 493   )
 494 {
 495   PTP_CRB_INTERFACE_IDENTIFIER   InterfaceId;
 496   PTP_FIFO_INTERFACE_CAPABILITY  InterfaceCapability;
 497   UINT8                          StatusEx;
 498   UINT16                         Vid;
 499   UINT16                         Did;
 500   UINT8                          Rid;
 501   TPM2_PTP_INTERFACE_TYPE        PtpInterface;
 502
 503   if (!Tpm2IsPtpPresence (Register)) {
 504     return;
 505   }
 506
 507   InterfaceId.Uint32         = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
 508   InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);
 509   StatusEx                   = MmioRead8 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->StatusEx);
 510
 511   //
 512   // Dump InterfaceId Register for PTP
 513   //
 514   DEBUG ((DEBUG_INFO, "InterfaceId - 0x%08x\n", InterfaceId.Uint32));
 515   DEBUG ((DEBUG_INFO, "  InterfaceType    - 0x%02x\n", InterfaceId.Bits.InterfaceType));
 516   if (InterfaceId.Bits.InterfaceType != PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS) {
 517     DEBUG ((DEBUG_INFO, "  InterfaceVersion - 0x%02x\n", InterfaceId.Bits.InterfaceVersion));
 518     DEBUG ((DEBUG_INFO, "  CapFIFO          - 0x%x\n", InterfaceId.Bits.CapFIFO));
 519     DEBUG ((DEBUG_INFO, "  CapCRB           - 0x%x\n", InterfaceId.Bits.CapCRB));
 520   }
 521
 522   //
 523   // Dump Capability Register for TIS and FIFO
 524   //
 525   DEBUG ((DEBUG_INFO, "InterfaceCapability - 0x%08x\n", InterfaceCapability.Uint32));
 526   if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS) ||
 527       (InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO))
 528   {
 529     DEBUG ((DEBUG_INFO, "  InterfaceVersion - 0x%x\n", InterfaceCapability.Bits.InterfaceVersion));
 530   }
 531
 532   //
 533   // Dump StatusEx Register for PTP FIFO
 534   //
 535   DEBUG ((DEBUG_INFO, "StatusEx - 0x%02x\n", StatusEx));
 536   if (InterfaceCapability.Bits.InterfaceVersion == INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP) {
 537     DEBUG ((DEBUG_INFO, "  TpmFamily - 0x%x\n", (StatusEx & PTP_FIFO_STS_EX_TPM_FAMILY) >> PTP_FIFO_STS_EX_TPM_FAMILY_OFFSET));
 538   }
 539
 540   Vid          = 0xFFFF;
 541   Did          = 0xFFFF;
 542   Rid          = 0xFF;
 543   PtpInterface = GetCachedPtpInterface ();
 544   DEBUG ((DEBUG_INFO, "PtpInterface - %x\n", PtpInterface));
 545   switch (PtpInterface) {
 546     case Tpm2PtpInterfaceCrb:
 547       Vid = MmioRead16 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->Vid);
 548       Did = MmioRead16 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->Did);
 549       Rid = (UINT8)InterfaceId.Bits.Rid;
 550       break;
 551     case Tpm2PtpInterfaceFifo:
 552     case Tpm2PtpInterfaceTis:
 553       Vid = MmioRead16 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Vid);
 554       Did = MmioRead16 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Did);
 555       Rid = MmioRead8 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Rid);
 556       break;
 557     default:
 558       break;
 559   }
 560
 561   DEBUG ((DEBUG_INFO, "VID - 0x%04x\n", Vid));
 562   DEBUG ((DEBUG_INFO, "DID - 0x%04x\n", Did));
 563   DEBUG ((DEBUG_INFO, "RID - 0x%02x\n", Rid));
 564 }
 565
 566 /**
 567   This service enables the sending of commands to the TPM2.
 568
 569   @param[in]      InputParameterBlockSize  Size of the TPM2 input parameter block.
 570   @param[in]      InputParameterBlock      Pointer to the TPM2 input parameter block.
 571   @param[in,out]  OutputParameterBlockSize Size of the TPM2 output parameter block.
 572   @param[in]      OutputParameterBlock     Pointer to the TPM2 output parameter block.
 573
 574   @retval EFI_SUCCESS            The command byte stream was successfully sent to the device and a response was successfully received.
 575   @retval EFI_DEVICE_ERROR       The command was not successfully sent to the device or a response was not successfully received from the device.
 576   @retval EFI_BUFFER_TOO_SMALL   The output parameter block is too small.
 577 **/
 578 EFI_STATUS
 579 EFIAPI
 580 DTpm2SubmitCommand (
 581   IN UINT32      InputParameterBlockSize,
 582   IN UINT8       *InputParameterBlock,
 583   IN OUT UINT32  *OutputParameterBlockSize,
 584   IN UINT8       *OutputParameterBlock
 585   )
 586 {
 587   TPM2_PTP_INTERFACE_TYPE  PtpInterface;
 588
 589   PtpInterface = GetCachedPtpInterface ();
 590   switch (PtpInterface) {
 591     case Tpm2PtpInterfaceCrb:
 592       return PtpCrbTpmCommand (
 593                (PTP_CRB_REGISTERS_PTR)(UINTN)PcdGet64 (PcdTpmBaseAddress),
 594                InputParameterBlock,
 595                InputParameterBlockSize,
 596                OutputParameterBlock,
 597                OutputParameterBlockSize
 598                );
 599     case Tpm2PtpInterfaceFifo:
 600     case Tpm2PtpInterfaceTis:
 601       return Tpm2TisTpmCommand (
 602                (TIS_PC_REGISTERS_PTR)(UINTN)PcdGet64 (PcdTpmBaseAddress),
 603                InputParameterBlock,
 604                InputParameterBlockSize,
 605                OutputParameterBlock,
 606                OutputParameterBlockSize
 607                );
 608     default:
 609       return EFI_NOT_FOUND;
 610   }
 611 }
 612
 613 /**
 614   This service requests use TPM2.
 615
 616   @retval EFI_SUCCESS      Get the control of TPM2 chip.
 617   @retval EFI_NOT_FOUND    TPM2 not found.
 618   @retval EFI_DEVICE_ERROR Unexpected device behavior.
 619 **/
 620 EFI_STATUS
 621 EFIAPI
 622 DTpm2RequestUseTpm (
 623   VOID
 624   )
 625 {
 626   TPM2_PTP_INTERFACE_TYPE  PtpInterface;
 627
 628   PtpInterface = GetCachedPtpInterface ();
 629   switch (PtpInterface) {
 630     case Tpm2PtpInterfaceCrb:
 631       return PtpCrbRequestUseTpm ((PTP_CRB_REGISTERS_PTR)(UINTN)PcdGet64 (PcdTpmBaseAddress));
 632     case Tpm2PtpInterfaceFifo:
 633     case Tpm2PtpInterfaceTis:
 634       return TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR)(UINTN)PcdGet64 (PcdTpmBaseAddress));
 635     default:
 636       return EFI_NOT_FOUND;
 637   }
 638 }