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1 /** @file
2 Header file for Registers and Structure definitions
3
4 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14 #ifndef __OPAL_PASSWORD_NVME_REG_H__
15 #define __OPAL_PASSWORD_NVME_REG_H__
16
17 //
18 // PCI Header for PCIe root port configuration
19 //
20 #define NVME_PCIE_PCICMD 0x04
21 #define NVME_PCIE_BNUM 0x18
22 #define NVME_PCIE_SEC_BNUM 0x19
23 #define NVME_PCIE_IOBL 0x1C
24 #define NVME_PCIE_MBL 0x20
25 #define NVME_PCIE_PMBL 0x24
26 #define NVME_PCIE_PMBU32 0x28
27 #define NVME_PCIE_PMLU32 0x2C
28 #define NVME_PCIE_INTR 0x3C
29
30 //
31 // NVMe related definitions
32 //
33 #define PCI_CLASS_MASS_STORAGE_NVM 0x08 // mass storage sub-class non-volatile memory.
34 #define PCI_IF_NVMHCI 0x02 // mass storage programming interface NVMHCI.
35
36 #define NVME_ASQ_SIZE 1 // Number of admin submission queue entries, which is 0-based
37 #define NVME_ACQ_SIZE 1 // Number of admin completion queue entries, which is 0-based
38
39 #define NVME_CSQ_SIZE 63 // Number of I/O submission queue entries, which is 0-based
40 #define NVME_CCQ_SIZE 63 // Number of I/O completion queue entries, which is 0-based
41
42 #define NVME_MAX_IO_QUEUES 2 // Number of I/O queues supported by the driver, 1 for AQ, 1 for CQ
43
44 #define NVME_CSQ_DEPTH (NVME_CSQ_SIZE+1)
45 #define NVME_CCQ_DEPTH (NVME_CCQ_SIZE+1)
46 #define NVME_PRP_SIZE (4) // Pages of PRP list
47
48 #define NVME_CONTROLLER_ID 0
49
50 //
51 // Time out Value for Nvme transaction execution
52 //
53 #define NVME_GENERIC_TIMEOUT 5000000 ///< us
54 #define NVME_CMD_WAIT 100 ///< us
55 #define NVME_CMD_TIMEOUT 20000000 ///< us
56
57
58
59 #define NVME_MEM_MAX_SIZE \
60 (( \
61 1 /* Controller Data */ + \
62 1 /* Identify Data */ + \
63 1 /* ASQ */ + \
64 1 /* ACQ */ + \
65 1 /* SQs */ + \
66 1 /* CQs */ + \
67 NVME_PRP_SIZE * NVME_CSQ_DEPTH /* PRPs */ + \
68 1 /* SECURITY */ \
69 ) * EFI_PAGE_SIZE)
70
71
72 //
73 // controller register offsets
74 //
75 #define NVME_CAP_OFFSET 0x0000 // Controller Capabilities
76 #define NVME_VER_OFFSET 0x0008 // Version
77 #define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set
78 #define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear
79 #define NVME_CC_OFFSET 0x0014 // Controller Configuration
80 #define NVME_CSTS_OFFSET 0x001c // Controller Status
81 #define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes
82 #define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address
83 #define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address
84 #define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tail Doorbell
85 #define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Head Doorbell
86
87 //
88 // These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))
89 // Get the doorbell stride bit shift Value from the controller capabilities.
90 //
91 #define NVME_SQTDBL_OFFSET(QID, DSTRD) 0x1000 + ((2 * (QID)) * (4 << (DSTRD))) // Submission Queue y (NVM) Tail Doorbell
92 #define NVME_CQHDBL_OFFSET(QID, DSTRD) 0x1000 + (((2 * (QID)) + 1) * (4 << (DSTRD))) // Completion Queue y (NVM) Head Doorbell
93
94
95 #pragma pack(1)
96
97 //
98 // 3.1.1 Offset 00h: CAP - Controller Capabilities
99 //
100 typedef struct {
101 UINT16 Mqes; // Maximum Queue Entries Supported
102 UINT8 Cqr:1; // Contiguous Queues Required
103 UINT8 Ams:2; // Arbitration Mechanism Supported
104 UINT8 Rsvd1:5;
105 UINT8 To; // Timeout
106 UINT16 Dstrd:4;
107 UINT16 Rsvd2:1;
108 UINT16 Css:4; // Command Sets Supported
109 UINT16 Rsvd3:7;
110 UINT8 Mpsmin:4;
111 UINT8 Mpsmax:4;
112 UINT8 Rsvd4;
113 } NVME_CAP;
114
115 //
116 // 3.1.2 Offset 08h: VS - Version
117 //
118 typedef struct {
119 UINT16 Mnr; // Minor version number
120 UINT16 Mjr; // Major version number
121 } NVME_VER;
122
123 //
124 // 3.1.5 Offset 14h: CC - Controller Configuration
125 //
126 typedef struct {
127 UINT16 En:1; // Enable
128 UINT16 Rsvd1:3;
129 UINT16 Css:3; // Command Set Selected
130 UINT16 Mps:4; // Memory Page Size
131 UINT16 Ams:3; // Arbitration Mechanism Selected
132 UINT16 Shn:2; // Shutdown Notification
133 UINT8 Iosqes:4; // I/O Submission Queue Entry Size
134 UINT8 Iocqes:4; // I/O Completion Queue Entry Size
135 UINT8 Rsvd2;
136 } NVME_CC;
137
138 //
139 // 3.1.6 Offset 1Ch: CSTS - Controller Status
140 //
141 typedef struct {
142 UINT32 Rdy:1; // Ready
143 UINT32 Cfs:1; // Controller Fatal Status
144 UINT32 Shst:2; // Shutdown Status
145 UINT32 Nssro:1; // NVM Subsystem Reset Occurred
146 UINT32 Rsvd1:27;
147 } NVME_CSTS;
148
149 //
150 // 3.1.8 Offset 24h: AQA - Admin Queue Attributes
151 //
152 typedef struct {
153 UINT16 Asqs:12; // Submission Queue Size
154 UINT16 Rsvd1:4;
155 UINT16 Acqs:12; // Completion Queue Size
156 UINT16 Rsvd2:4;
157 } NVME_AQA;
158
159 //
160 // 3.1.9 Offset 28h: ASQ - Admin Submission Queue Base Address
161 //
162 #define NVME_ASQ UINT64
163
164 //
165 // 3.1.10 Offset 30h: ACQ - Admin Completion Queue Base Address
166 //
167 #define NVME_ACQ UINT64
168
169 //
170 // 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell
171 //
172 typedef struct {
173 UINT16 Sqt;
174 UINT16 Rsvd1;
175 } NVME_SQTDBL;
176
177 //
178 // 3.1.12 Offset (1000h + ((2y + 1) * (4 << CAP.DSTRD))): CQyHDBL - Completion Queue y Head Doorbell
179 //
180 typedef struct {
181 UINT16 Cqh;
182 UINT16 Rsvd1;
183 } NVME_CQHDBL;
184
185 //
186 // NVM command set structures
187 //
188 // Read Command
189 //
190 typedef struct {
191 //
192 // CDW 10, 11
193 //
194 UINT64 Slba; /* Starting Sector Address */
195 //
196 // CDW 12
197 //
198 UINT16 Nlb; /* Number of Sectors */
199 UINT16 Rsvd1:10;
200 UINT16 Prinfo:4; /* Protection Info Check */
201 UINT16 Fua:1; /* Force Unit Access */
202 UINT16 Lr:1; /* Limited Retry */
203 //
204 // CDW 13
205 //
206 UINT32 Af:4; /* Access Frequency */
207 UINT32 Al:2; /* Access Latency */
208 UINT32 Sr:1; /* Sequential Request */
209 UINT32 In:1; /* Incompressible */
210 UINT32 Rsvd2:24;
211 //
212 // CDW 14
213 //
214 UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */
215 //
216 // CDW 15
217 //
218 UINT16 Elbat; /* Expected Logical Block Application Tag */
219 UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */
220 } NVME_READ;
221
222 //
223 // Write Command
224 //
225 typedef struct {
226 //
227 // CDW 10, 11
228 //
229 UINT64 Slba; /* Starting Sector Address */
230 //
231 // CDW 12
232 //
233 UINT16 Nlb; /* Number of Sectors */
234 UINT16 Rsvd1:10;
235 UINT16 Prinfo:4; /* Protection Info Check */
236 UINT16 Fua:1; /* Force Unit Access */
237 UINT16 Lr:1; /* Limited Retry */
238 //
239 // CDW 13
240 //
241 UINT32 Af:4; /* Access Frequency */
242 UINT32 Al:2; /* Access Latency */
243 UINT32 Sr:1; /* Sequential Request */
244 UINT32 In:1; /* Incompressible */
245 UINT32 Rsvd2:24;
246 //
247 // CDW 14
248 //
249 UINT32 Ilbrt; /* Initial Logical Block Reference Tag */
250 //
251 // CDW 15
252 //
253 UINT16 Lbat; /* Logical Block Application Tag */
254 UINT16 Lbatm; /* Logical Block Application Tag Mask */
255 } NVME_WRITE;
256
257 //
258 // Flush
259 //
260 typedef struct {
261 //
262 // CDW 10
263 //
264 UINT32 Flush; /* Flush */
265 } NVME_FLUSH;
266
267 //
268 // Write Uncorrectable command
269 //
270 typedef struct {
271 //
272 // CDW 10, 11
273 //
274 UINT64 Slba; /* Starting LBA */
275 //
276 // CDW 12
277 //
278 UINT32 Nlb:16; /* Number of Logical Blocks */
279 UINT32 Rsvd1:16;
280 } NVME_WRITE_UNCORRECTABLE;
281
282 //
283 // Write Zeroes command
284 //
285 typedef struct {
286 //
287 // CDW 10, 11
288 //
289 UINT64 Slba; /* Starting LBA */
290 //
291 // CDW 12
292 //
293 UINT16 Nlb; /* Number of Logical Blocks */
294 UINT16 Rsvd1:10;
295 UINT16 Prinfo:4; /* Protection Info Check */
296 UINT16 Fua:1; /* Force Unit Access */
297 UINT16 Lr:1; /* Limited Retry */
298 //
299 // CDW 13
300 //
301 UINT32 Rsvd2;
302 //
303 // CDW 14
304 //
305 UINT32 Ilbrt; /* Initial Logical Block Reference Tag */
306 //
307 // CDW 15
308 //
309 UINT16 Lbat; /* Logical Block Application Tag */
310 UINT16 Lbatm; /* Logical Block Application Tag Mask */
311 } NVME_WRITE_ZEROES;
312
313 //
314 // Compare command
315 //
316 typedef struct {
317 //
318 // CDW 10, 11
319 //
320 UINT64 Slba; /* Starting LBA */
321 //
322 // CDW 12
323 //
324 UINT16 Nlb; /* Number of Logical Blocks */
325 UINT16 Rsvd1:10;
326 UINT16 Prinfo:4; /* Protection Info Check */
327 UINT16 Fua:1; /* Force Unit Access */
328 UINT16 Lr:1; /* Limited Retry */
329 //
330 // CDW 13
331 //
332 UINT32 Rsvd2;
333 //
334 // CDW 14
335 //
336 UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */
337 //
338 // CDW 15
339 //
340 UINT16 Elbat; /* Expected Logical Block Application Tag */
341 UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */
342 } NVME_COMPARE;
343
344 typedef union {
345 NVME_READ Read;
346 NVME_WRITE Write;
347 NVME_FLUSH Flush;
348 NVME_WRITE_UNCORRECTABLE WriteUncorrectable;
349 NVME_WRITE_ZEROES WriteZeros;
350 NVME_COMPARE Compare;
351 } NVME_CMD;
352
353 typedef struct {
354 UINT16 Mp; /* Maximum Power */
355 UINT8 Rsvd1; /* Reserved as of Nvm Express 1.1 Spec */
356 UINT8 Mps:1; /* Max Power Scale */
357 UINT8 Nops:1; /* Non-Operational State */
358 UINT8 Rsvd2:6; /* Reserved as of Nvm Express 1.1 Spec */
359 UINT32 Enlat; /* Entry Latency */
360 UINT32 Exlat; /* Exit Latency */
361 UINT8 Rrt:5; /* Relative Read Throughput */
362 UINT8 Rsvd3:3; /* Reserved as of Nvm Express 1.1 Spec */
363 UINT8 Rrl:5; /* Relative Read Leatency */
364 UINT8 Rsvd4:3; /* Reserved as of Nvm Express 1.1 Spec */
365 UINT8 Rwt:5; /* Relative Write Throughput */
366 UINT8 Rsvd5:3; /* Reserved as of Nvm Express 1.1 Spec */
367 UINT8 Rwl:5; /* Relative Write Leatency */
368 UINT8 Rsvd6:3; /* Reserved as of Nvm Express 1.1 Spec */
369 UINT8 Rsvd7[16]; /* Reserved as of Nvm Express 1.1 Spec */
370 } NVME_PSDESCRIPTOR;
371
372 //
373 // Identify Controller Data
374 //
375 typedef struct {
376 //
377 // Controller Capabilities and Features 0-255
378 //
379 UINT16 Vid; /* PCI Vendor ID */
380 UINT16 Ssvid; /* PCI sub-system vendor ID */
381 UINT8 Sn[20]; /* Produce serial number */
382
383 UINT8 Mn[40]; /* Proeduct model number */
384 UINT8 Fr[8]; /* Firmware Revision */
385 UINT8 Rab; /* Recommended Arbitration Burst */
386 UINT8 Ieee_oiu[3]; /* Organization Unique Identifier */
387 UINT8 Cmic; /* Multi-interface Capabilities */
388 UINT8 Mdts; /* Maximum Data Transfer Size */
389 UINT8 Cntlid[2]; /* Controller ID */
390 UINT8 Rsvd1[176]; /* Reserved as of Nvm Express 1.1 Spec */
391 //
392 // Admin Command Set Attributes
393 //
394 UINT16 Oacs; /* Optional Admin Command Support */
395 UINT8 Acl; /* Abort Command Limit */
396 UINT8 Aerl; /* Async Event Request Limit */
397 UINT8 Frmw; /* Firmware updates */
398 UINT8 Lpa; /* Log Page Attributes */
399 UINT8 Elpe; /* Error Log Page Entries */
400 UINT8 Npss; /* Number of Power States Support */
401 UINT8 Avscc; /* Admin Vendor Specific Command Configuration */
402 UINT8 Apsta; /* Autonomous Power State Transition Attributes */
403 UINT8 Rsvd2[246]; /* Reserved as of Nvm Express 1.1 Spec */
404 //
405 // NVM Command Set Attributes
406 //
407 UINT8 Sqes; /* Submission Queue Entry Size */
408 UINT8 Cqes; /* Completion Queue Entry Size */
409 UINT16 Rsvd3; /* Reserved as of Nvm Express 1.1 Spec */
410 UINT32 Nn; /* Number of Namespaces */
411 UINT16 Oncs; /* Optional NVM Command Support */
412 UINT16 Fuses; /* Fused Operation Support */
413 UINT8 Fna; /* Format NVM Attributes */
414 UINT8 Vwc; /* Volatile Write Cache */
415 UINT16 Awun; /* Atomic Write Unit Normal */
416 UINT16 Awupf; /* Atomic Write Unit Power Fail */
417 UINT8 Nvscc; /* NVM Vendor Specific Command Configuration */
418 UINT8 Rsvd4; /* Reserved as of Nvm Express 1.1 Spec */
419 UINT16 Acwu; /* Atomic Compare & Write Unit */
420 UINT16 Rsvd5; /* Reserved as of Nvm Express 1.1 Spec */
421 UINT32 Sgls; /* SGL Support */
422 UINT8 Rsvd6[164]; /* Reserved as of Nvm Express 1.1 Spec */
423 //
424 // I/O Command set Attributes
425 //
426 UINT8 Rsvd7[1344]; /* Reserved as of Nvm Express 1.1 Spec */
427 //
428 // Power State Descriptors
429 //
430 NVME_PSDESCRIPTOR PsDescriptor[32];
431
432 UINT8 VendorData[1024]; /* Vendor specific Data */
433 } NVME_ADMIN_CONTROLLER_DATA;
434
435 typedef struct {
436 UINT16 Security : 1; /* supports security send/receive commands */
437 UINT16 Format : 1; /* supports format nvm command */
438 UINT16 Firmware : 1; /* supports firmware activate/download commands */
439 UINT16 Oacs_rsvd : 13;
440 } OACS; // optional admin command support: NVME_ADMIN_CONTROLLER_DATA.Oacs
441
442 typedef struct {
443 UINT16 Ms; /* Metadata Size */
444 UINT8 Lbads; /* LBA Data Size */
445 UINT8 Rp:2; /* Relative Performance */
446 #define LBAF_RP_BEST 00b
447 #define LBAF_RP_BETTER 01b
448 #define LBAF_RP_GOOD 10b
449 #define LBAF_RP_DEGRADED 11b
450 UINT8 Rsvd1:6; /* Reserved as of Nvm Express 1.1 Spec */
451 } NVME_LBAFORMAT;
452
453 //
454 // Identify Namespace Data
455 //
456 typedef struct {
457 //
458 // NVM Command Set Specific
459 //
460 UINT64 Nsze; /* Namespace Size (total number of blocks in formatted namespace) */
461 UINT64 Ncap; /* Namespace Capacity (max number of logical blocks) */
462 UINT64 Nuse; /* Namespace Utilization */
463 UINT8 Nsfeat; /* Namespace Features */
464 UINT8 Nlbaf; /* Number of LBA Formats */
465 UINT8 Flbas; /* Formatted LBA Size */
466 UINT8 Mc; /* Metadata Capabilities */
467 UINT8 Dpc; /* End-to-end Data Protection capabilities */
468 UINT8 Dps; /* End-to-end Data Protection Type Settings */
469 UINT8 Nmic; /* Namespace Multi-path I/O and Namespace Sharing Capabilities */
470 UINT8 Rescap; /* Reservation Capabilities */
471 UINT8 Rsvd1[88]; /* Reserved as of Nvm Express 1.1 Spec */
472 UINT64 Eui64; /* IEEE Extended Unique Identifier */
473 //
474 // LBA Format
475 //
476 NVME_LBAFORMAT LbaFormat[16];
477
478 UINT8 Rsvd2[192]; /* Reserved as of Nvm Express 1.1 Spec */
479 UINT8 VendorData[3712]; /* Vendor specific Data */
480 } NVME_ADMIN_NAMESPACE_DATA;
481
482 //
483 // NvmExpress Admin Identify Cmd
484 //
485 typedef struct {
486 //
487 // CDW 10
488 //
489 UINT32 Cns:2;
490 UINT32 Rsvd1:30;
491 } NVME_ADMIN_IDENTIFY;
492
493 //
494 // NvmExpress Admin Create I/O Completion Queue
495 //
496 typedef struct {
497 //
498 // CDW 10
499 //
500 UINT32 Qid:16; /* Queue Identifier */
501 UINT32 Qsize:16; /* Queue Size */
502
503 //
504 // CDW 11
505 //
506 UINT32 Pc:1; /* Physically Contiguous */
507 UINT32 Ien:1; /* Interrupts Enabled */
508 UINT32 Rsvd1:14; /* reserved as of Nvm Express 1.1 Spec */
509 UINT32 Iv:16; /* Interrupt Vector */
510 } NVME_ADMIN_CRIOCQ;
511
512 //
513 // NvmExpress Admin Create I/O Submission Queue
514 //
515 typedef struct {
516 //
517 // CDW 10
518 //
519 UINT32 Qid:16; /* Queue Identifier */
520 UINT32 Qsize:16; /* Queue Size */
521
522 //
523 // CDW 11
524 //
525 UINT32 Pc:1; /* Physically Contiguous */
526 UINT32 Qprio:2; /* Queue Priority */
527 UINT32 Rsvd1:13; /* Reserved as of Nvm Express 1.1 Spec */
528 UINT32 Cqid:16; /* Completion Queue ID */
529 } NVME_ADMIN_CRIOSQ;
530
531 //
532 // NvmExpress Admin Delete I/O Completion Queue
533 //
534 typedef struct {
535 //
536 // CDW 10
537 //
538 UINT16 Qid;
539 UINT16 Rsvd1;
540 } NVME_ADMIN_DEIOCQ;
541
542 //
543 // NvmExpress Admin Delete I/O Submission Queue
544 //
545 typedef struct {
546 //
547 // CDW 10
548 //
549 UINT16 Qid;
550 UINT16 Rsvd1;
551 } NVME_ADMIN_DEIOSQ;
552
553 //
554 // NvmExpress Admin Security Send
555 //
556 typedef struct {
557 //
558 // CDW 10
559 //
560 UINT32 Resv:8; /* Reserve */
561 UINT32 Spsp:16; /* SP Specific */
562 UINT32 Secp:8; /* Security Protocol */
563
564 //
565 // CDW 11
566 //
567 UINT32 Tl; /* Transfer Length */
568 } NVME_ADMIN_SECSEND;
569
570 //
571 // NvmExpress Admin Abort Command
572 //
573 typedef struct {
574 //
575 // CDW 10
576 //
577 UINT32 Sqid:16; /* Submission Queue identifier */
578 UINT32 Cid:16; /* Command Identifier */
579 } NVME_ADMIN_ABORT;
580
581 //
582 // NvmExpress Admin Firmware Activate Command
583 //
584 typedef struct {
585 //
586 // CDW 10
587 //
588 UINT32 Fs:3; /* Submission Queue identifier */
589 UINT32 Aa:2; /* Command Identifier */
590 UINT32 Rsvd1:27;
591 } NVME_ADMIN_FIRMWARE_ACTIVATE;
592
593 //
594 // NvmExpress Admin Firmware Image Download Command
595 //
596 typedef struct {
597 //
598 // CDW 10
599 //
600 UINT32 Numd; /* Number of Dwords */
601 //
602 // CDW 11
603 //
604 UINT32 Ofst; /* Offset */
605 } NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD;
606
607 //
608 // NvmExpress Admin Get Features Command
609 //
610 typedef struct {
611 //
612 // CDW 10
613 //
614 UINT32 Fid:8; /* Feature Identifier */
615 UINT32 Sel:3; /* Select */
616 UINT32 Rsvd1:21;
617 } NVME_ADMIN_GET_FEATURES;
618
619 //
620 // NvmExpress Admin Get Log Page Command
621 //
622 typedef struct {
623 //
624 // CDW 10
625 //
626 UINT32 Lid:8; /* Log Page Identifier */
627 #define LID_ERROR_INFO
628 #define LID_SMART_INFO
629 #define LID_FW_SLOT_INFO
630 UINT32 Rsvd1:8;
631 UINT32 Numd:12; /* Number of Dwords */
632 UINT32 Rsvd2:4; /* Reserved as of Nvm Express 1.1 Spec */
633 } NVME_ADMIN_GET_LOG_PAGE;
634
635 //
636 // NvmExpress Admin Set Features Command
637 //
638 typedef struct {
639 //
640 // CDW 10
641 //
642 UINT32 Fid:8; /* Feature Identifier */
643 UINT32 Rsvd1:23;
644 UINT32 Sv:1; /* Save */
645 } NVME_ADMIN_SET_FEATURES;
646
647 //
648 // NvmExpress Admin Format NVM Command
649 //
650 typedef struct {
651 //
652 // CDW 10
653 //
654 UINT32 Lbaf:4; /* LBA Format */
655 UINT32 Ms:1; /* Metadata Settings */
656 UINT32 Pi:3; /* Protection Information */
657 UINT32 Pil:1; /* Protection Information Location */
658 UINT32 Ses:3; /* Secure Erase Settings */
659 UINT32 Rsvd1:20;
660 } NVME_ADMIN_FORMAT_NVM;
661
662 //
663 // NvmExpress Admin Security Receive Command
664 //
665 typedef struct {
666 //
667 // CDW 10
668 //
669 UINT32 Rsvd1:8;
670 UINT32 Spsp:16; /* SP Specific */
671 UINT32 Secp:8; /* Security Protocol */
672 //
673 // CDW 11
674 //
675 UINT32 Al; /* Allocation Length */
676 } NVME_ADMIN_SECURITY_RECEIVE;
677
678 //
679 // NvmExpress Admin Security Send Command
680 //
681 typedef struct {
682 //
683 // CDW 10
684 //
685 UINT32 Rsvd1:8;
686 UINT32 Spsp:16; /* SP Specific */
687 UINT32 Secp:8; /* Security Protocol */
688 //
689 // CDW 11
690 //
691 UINT32 Tl; /* Transfer Length */
692 } NVME_ADMIN_SECURITY_SEND;
693
694 typedef union {
695 NVME_ADMIN_IDENTIFY Identify;
696 NVME_ADMIN_CRIOCQ CrIoCq;
697 NVME_ADMIN_CRIOSQ CrIoSq;
698 NVME_ADMIN_DEIOCQ DeIoCq;
699 NVME_ADMIN_DEIOSQ DeIoSq;
700 NVME_ADMIN_ABORT Abort;
701 NVME_ADMIN_FIRMWARE_ACTIVATE Activate;
702 NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD FirmwareImageDownload;
703 NVME_ADMIN_GET_FEATURES GetFeatures;
704 NVME_ADMIN_GET_LOG_PAGE GetLogPage;
705 NVME_ADMIN_SET_FEATURES SetFeatures;
706 NVME_ADMIN_FORMAT_NVM FormatNvm;
707 NVME_ADMIN_SECURITY_RECEIVE SecurityReceive;
708 NVME_ADMIN_SECURITY_SEND SecuritySend;
709 } NVME_ADMIN_CMD;
710
711 typedef struct {
712 UINT32 Cdw10;
713 UINT32 Cdw11;
714 UINT32 Cdw12;
715 UINT32 Cdw13;
716 UINT32 Cdw14;
717 UINT32 Cdw15;
718 } NVME_RAW;
719
720 typedef union {
721 NVME_ADMIN_CMD Admin; // Union of Admin commands
722 NVME_CMD Nvm; // Union of Nvm commands
723 NVME_RAW Raw;
724 } NVME_PAYLOAD;
725
726 //
727 // Submission Queue
728 //
729 typedef struct {
730 //
731 // CDW 0, Common to all comnmands
732 //
733 UINT8 Opc; // Opcode
734 UINT8 Fuse:2; // Fused Operation
735 UINT8 Rsvd1:5;
736 UINT8 Psdt:1; // PRP or SGL for Data Transfer
737 UINT16 Cid; // Command Identifier
738
739 //
740 // CDW 1
741 //
742 UINT32 Nsid; // Namespace Identifier
743
744 //
745 // CDW 2,3
746 //
747 UINT64 Rsvd2;
748
749 //
750 // CDW 4,5
751 //
752 UINT64 Mptr; // Metadata Pointer
753
754 //
755 // CDW 6-9
756 //
757 UINT64 Prp[2]; // First and second PRP entries
758
759 NVME_PAYLOAD Payload;
760
761 } NVME_SQ;
762
763 //
764 // Completion Queue
765 //
766 typedef struct {
767 //
768 // CDW 0
769 //
770 UINT32 Dword0;
771 //
772 // CDW 1
773 //
774 UINT32 Rsvd1;
775 //
776 // CDW 2
777 //
778 UINT16 Sqhd; // Submission Queue Head Pointer
779 UINT16 Sqid; // Submission Queue Identifier
780 //
781 // CDW 3
782 //
783 UINT16 Cid; // Command Identifier
784 UINT16 Pt:1; // Phase Tag
785 UINT16 Sc:8; // Status Code
786 UINT16 Sct:3; // Status Code Type
787 UINT16 Rsvd2:2;
788 UINT16 Mo:1; // More
789 UINT16 Dnr:1; // Retry
790 } NVME_CQ;
791
792 //
793 // Nvm Express Admin cmd opcodes
794 //
795 #define NVME_ADMIN_DELIOSQ_OPC 0
796 #define NVME_ADMIN_CRIOSQ_OPC 1
797 #define NVME_ADMIN_DELIOCQ_OPC 4
798 #define NVME_ADMIN_CRIOCQ_OPC 5
799 #define NVME_ADMIN_IDENTIFY_OPC 6
800 #define NVME_ADMIN_SECURITY_SEND_OPC 0x81
801 #define NVME_ADMIN_SECURITY_RECV_OPC 0x82
802
803 #define NVME_IO_FLUSH_OPC 0
804 #define NVME_IO_WRITE_OPC 1
805 #define NVME_IO_READ_OPC 2
806
807 //
808 // Offset from the beginning of private Data queue Buffer
809 //
810 #define NVME_ASQ_BUF_OFFSET EFI_PAGE_SIZE
811
812 #pragma pack()
813
814 #endif
815
EFI Development Kit II mirror for PVE