2 Header file for Registers and Structure definitions
4 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 #ifndef __OPAL_PASSWORD_NVME_REG_H__
15 #define __OPAL_PASSWORD_NVME_REG_H__
18 // PCI Header for PCIe root port configuration
20 #define NVME_PCIE_PCICMD 0x04
21 #define NVME_PCIE_BNUM 0x18
22 #define NVME_PCIE_SEC_BNUM 0x19
23 #define NVME_PCIE_IOBL 0x1C
24 #define NVME_PCIE_MBL 0x20
25 #define NVME_PCIE_PMBL 0x24
26 #define NVME_PCIE_PMBU32 0x28
27 #define NVME_PCIE_PMLU32 0x2C
28 #define NVME_PCIE_INTR 0x3C
31 // NVMe related definitions
33 #define PCI_CLASS_MASS_STORAGE_NVM 0x08 // mass storage sub-class non-volatile memory.
34 #define PCI_IF_NVMHCI 0x02 // mass storage programming interface NVMHCI.
36 #define NVME_ASQ_SIZE 1 // Number of admin submission queue entries, which is 0-based
37 #define NVME_ACQ_SIZE 1 // Number of admin completion queue entries, which is 0-based
39 #define NVME_CSQ_SIZE 63 // Number of I/O submission queue entries, which is 0-based
40 #define NVME_CCQ_SIZE 63 // Number of I/O completion queue entries, which is 0-based
42 #define NVME_MAX_IO_QUEUES 2 // Number of I/O queues supported by the driver, 1 for AQ, 1 for CQ
44 #define NVME_CSQ_DEPTH (NVME_CSQ_SIZE+1)
45 #define NVME_CCQ_DEPTH (NVME_CCQ_SIZE+1)
46 #define NVME_PRP_SIZE (4) // Pages of PRP list
48 #define NVME_CONTROLLER_ID 0
51 // Time out Value for Nvme transaction execution
53 #define NVME_GENERIC_TIMEOUT 5000000 ///< us
54 #define NVME_CMD_WAIT 100 ///< us
55 #define NVME_CMD_TIMEOUT 20000000 ///< us
59 #define NVME_MEM_MAX_SIZE \
61 1 /* Controller Data */ + \
62 1 /* Identify Data */ + \
67 NVME_PRP_SIZE * NVME_CSQ_DEPTH /* PRPs */ \
72 // controller register offsets
74 #define NVME_CAP_OFFSET 0x0000 // Controller Capabilities
75 #define NVME_VER_OFFSET 0x0008 // Version
76 #define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set
77 #define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear
78 #define NVME_CC_OFFSET 0x0014 // Controller Configuration
79 #define NVME_CSTS_OFFSET 0x001c // Controller Status
80 #define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes
81 #define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address
82 #define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address
83 #define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tail Doorbell
84 #define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Head Doorbell
87 // These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))
88 // Get the doorbell stride bit shift Value from the controller capabilities.
90 #define NVME_SQTDBL_OFFSET(QID, DSTRD) 0x1000 + ((2 * (QID)) * (4 << (DSTRD))) // Submission Queue y (NVM) Tail Doorbell
91 #define NVME_CQHDBL_OFFSET(QID, DSTRD) 0x1000 + (((2 * (QID)) + 1) * (4 << (DSTRD))) // Completion Queue y (NVM) Head Doorbell
97 // 3.1.1 Offset 00h: CAP - Controller Capabilities
100 UINT16 Mqes
; // Maximum Queue Entries Supported
101 UINT8 Cqr
:1; // Contiguous Queues Required
102 UINT8 Ams
:2; // Arbitration Mechanism Supported
107 UINT16 Css
:4; // Command Sets Supported
115 // 3.1.2 Offset 08h: VS - Version
118 UINT16 Mnr
; // Minor version number
119 UINT16 Mjr
; // Major version number
123 // 3.1.5 Offset 14h: CC - Controller Configuration
126 UINT16 En
:1; // Enable
128 UINT16 Css
:3; // Command Set Selected
129 UINT16 Mps
:4; // Memory Page Size
130 UINT16 Ams
:3; // Arbitration Mechanism Selected
131 UINT16 Shn
:2; // Shutdown Notification
132 UINT8 Iosqes
:4; // I/O Submission Queue Entry Size
133 UINT8 Iocqes
:4; // I/O Completion Queue Entry Size
138 // 3.1.6 Offset 1Ch: CSTS - Controller Status
141 UINT32 Rdy
:1; // Ready
142 UINT32 Cfs
:1; // Controller Fatal Status
143 UINT32 Shst
:2; // Shutdown Status
144 UINT32 Nssro
:1; // NVM Subsystem Reset Occurred
149 // 3.1.8 Offset 24h: AQA - Admin Queue Attributes
152 UINT16 Asqs
:12; // Submission Queue Size
154 UINT16 Acqs
:12; // Completion Queue Size
159 // 3.1.9 Offset 28h: ASQ - Admin Submission Queue Base Address
161 #define NVME_ASQ UINT64
164 // 3.1.10 Offset 30h: ACQ - Admin Completion Queue Base Address
166 #define NVME_ACQ UINT64
169 // 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell
177 // 3.1.12 Offset (1000h + ((2y + 1) * (4 << CAP.DSTRD))): CQyHDBL - Completion Queue y Head Doorbell
185 // NVM command set structures
193 UINT64 Slba
; /* Starting Sector Address */
197 UINT16 Nlb
; /* Number of Sectors */
199 UINT16 Prinfo
:4; /* Protection Info Check */
200 UINT16 Fua
:1; /* Force Unit Access */
201 UINT16 Lr
:1; /* Limited Retry */
205 UINT32 Af
:4; /* Access Frequency */
206 UINT32 Al
:2; /* Access Latency */
207 UINT32 Sr
:1; /* Sequential Request */
208 UINT32 In
:1; /* Incompressible */
213 UINT32 Eilbrt
; /* Expected Initial Logical Block Reference Tag */
217 UINT16 Elbat
; /* Expected Logical Block Application Tag */
218 UINT16 Elbatm
; /* Expected Logical Block Application Tag Mask */
228 UINT64 Slba
; /* Starting Sector Address */
232 UINT16 Nlb
; /* Number of Sectors */
234 UINT16 Prinfo
:4; /* Protection Info Check */
235 UINT16 Fua
:1; /* Force Unit Access */
236 UINT16 Lr
:1; /* Limited Retry */
240 UINT32 Af
:4; /* Access Frequency */
241 UINT32 Al
:2; /* Access Latency */
242 UINT32 Sr
:1; /* Sequential Request */
243 UINT32 In
:1; /* Incompressible */
248 UINT32 Ilbrt
; /* Initial Logical Block Reference Tag */
252 UINT16 Lbat
; /* Logical Block Application Tag */
253 UINT16 Lbatm
; /* Logical Block Application Tag Mask */
263 UINT32 Flush
; /* Flush */
267 // Write Uncorrectable command
273 UINT64 Slba
; /* Starting LBA */
277 UINT32 Nlb
:16; /* Number of Logical Blocks */
279 } NVME_WRITE_UNCORRECTABLE
;
282 // Write Zeroes command
288 UINT64 Slba
; /* Starting LBA */
292 UINT16 Nlb
; /* Number of Logical Blocks */
294 UINT16 Prinfo
:4; /* Protection Info Check */
295 UINT16 Fua
:1; /* Force Unit Access */
296 UINT16 Lr
:1; /* Limited Retry */
304 UINT32 Ilbrt
; /* Initial Logical Block Reference Tag */
308 UINT16 Lbat
; /* Logical Block Application Tag */
309 UINT16 Lbatm
; /* Logical Block Application Tag Mask */
319 UINT64 Slba
; /* Starting LBA */
323 UINT16 Nlb
; /* Number of Logical Blocks */
325 UINT16 Prinfo
:4; /* Protection Info Check */
326 UINT16 Fua
:1; /* Force Unit Access */
327 UINT16 Lr
:1; /* Limited Retry */
335 UINT32 Eilbrt
; /* Expected Initial Logical Block Reference Tag */
339 UINT16 Elbat
; /* Expected Logical Block Application Tag */
340 UINT16 Elbatm
; /* Expected Logical Block Application Tag Mask */
347 NVME_WRITE_UNCORRECTABLE WriteUncorrectable
;
348 NVME_WRITE_ZEROES WriteZeros
;
349 NVME_COMPARE Compare
;
353 UINT16 Mp
; /* Maximum Power */
354 UINT8 Rsvd1
; /* Reserved as of Nvm Express 1.1 Spec */
355 UINT8 Mps
:1; /* Max Power Scale */
356 UINT8 Nops
:1; /* Non-Operational State */
357 UINT8 Rsvd2
:6; /* Reserved as of Nvm Express 1.1 Spec */
358 UINT32 Enlat
; /* Entry Latency */
359 UINT32 Exlat
; /* Exit Latency */
360 UINT8 Rrt
:5; /* Relative Read Throughput */
361 UINT8 Rsvd3
:3; /* Reserved as of Nvm Express 1.1 Spec */
362 UINT8 Rrl
:5; /* Relative Read Leatency */
363 UINT8 Rsvd4
:3; /* Reserved as of Nvm Express 1.1 Spec */
364 UINT8 Rwt
:5; /* Relative Write Throughput */
365 UINT8 Rsvd5
:3; /* Reserved as of Nvm Express 1.1 Spec */
366 UINT8 Rwl
:5; /* Relative Write Leatency */
367 UINT8 Rsvd6
:3; /* Reserved as of Nvm Express 1.1 Spec */
368 UINT8 Rsvd7
[16]; /* Reserved as of Nvm Express 1.1 Spec */
372 // Identify Controller Data
376 // Controller Capabilities and Features 0-255
378 UINT16 Vid
; /* PCI Vendor ID */
379 UINT16 Ssvid
; /* PCI sub-system vendor ID */
380 UINT8 Sn
[20]; /* Produce serial number */
382 UINT8 Mn
[40]; /* Proeduct model number */
383 UINT8 Fr
[8]; /* Firmware Revision */
384 UINT8 Rab
; /* Recommended Arbitration Burst */
385 UINT8 Ieee_oiu
[3]; /* Organization Unique Identifier */
386 UINT8 Cmic
; /* Multi-interface Capabilities */
387 UINT8 Mdts
; /* Maximum Data Transfer Size */
388 UINT8 Cntlid
[2]; /* Controller ID */
389 UINT8 Rsvd1
[176]; /* Reserved as of Nvm Express 1.1 Spec */
391 // Admin Command Set Attributes
393 UINT16 Oacs
; /* Optional Admin Command Support */
394 UINT8 Acl
; /* Abort Command Limit */
395 UINT8 Aerl
; /* Async Event Request Limit */
396 UINT8 Frmw
; /* Firmware updates */
397 UINT8 Lpa
; /* Log Page Attributes */
398 UINT8 Elpe
; /* Error Log Page Entries */
399 UINT8 Npss
; /* Number of Power States Support */
400 UINT8 Avscc
; /* Admin Vendor Specific Command Configuration */
401 UINT8 Apsta
; /* Autonomous Power State Transition Attributes */
402 UINT8 Rsvd2
[246]; /* Reserved as of Nvm Express 1.1 Spec */
404 // NVM Command Set Attributes
406 UINT8 Sqes
; /* Submission Queue Entry Size */
407 UINT8 Cqes
; /* Completion Queue Entry Size */
408 UINT16 Rsvd3
; /* Reserved as of Nvm Express 1.1 Spec */
409 UINT32 Nn
; /* Number of Namespaces */
410 UINT16 Oncs
; /* Optional NVM Command Support */
411 UINT16 Fuses
; /* Fused Operation Support */
412 UINT8 Fna
; /* Format NVM Attributes */
413 UINT8 Vwc
; /* Volatile Write Cache */
414 UINT16 Awun
; /* Atomic Write Unit Normal */
415 UINT16 Awupf
; /* Atomic Write Unit Power Fail */
416 UINT8 Nvscc
; /* NVM Vendor Specific Command Configuration */
417 UINT8 Rsvd4
; /* Reserved as of Nvm Express 1.1 Spec */
418 UINT16 Acwu
; /* Atomic Compare & Write Unit */
419 UINT16 Rsvd5
; /* Reserved as of Nvm Express 1.1 Spec */
420 UINT32 Sgls
; /* SGL Support */
421 UINT8 Rsvd6
[164]; /* Reserved as of Nvm Express 1.1 Spec */
423 // I/O Command set Attributes
425 UINT8 Rsvd7
[1344]; /* Reserved as of Nvm Express 1.1 Spec */
427 // Power State Descriptors
429 NVME_PSDESCRIPTOR PsDescriptor
[32];
431 UINT8 VendorData
[1024]; /* Vendor specific Data */
432 } NVME_ADMIN_CONTROLLER_DATA
;
435 UINT16 Security
: 1; /* supports security send/receive commands */
436 UINT16 Format
: 1; /* supports format nvm command */
437 UINT16 Firmware
: 1; /* supports firmware activate/download commands */
438 UINT16 Oacs_rsvd
: 13;
439 } OACS
; // optional admin command support: NVME_ADMIN_CONTROLLER_DATA.Oacs
442 UINT16 Ms
; /* Metadata Size */
443 UINT8 Lbads
; /* LBA Data Size */
444 UINT8 Rp
:2; /* Relative Performance */
445 #define LBAF_RP_BEST 00b
446 #define LBAF_RP_BETTER 01b
447 #define LBAF_RP_GOOD 10b
448 #define LBAF_RP_DEGRADED 11b
449 UINT8 Rsvd1
:6; /* Reserved as of Nvm Express 1.1 Spec */
453 // Identify Namespace Data
457 // NVM Command Set Specific
459 UINT64 Nsze
; /* Namespace Size (total number of blocks in formatted namespace) */
460 UINT64 Ncap
; /* Namespace Capacity (max number of logical blocks) */
461 UINT64 Nuse
; /* Namespace Utilization */
462 UINT8 Nsfeat
; /* Namespace Features */
463 UINT8 Nlbaf
; /* Number of LBA Formats */
464 UINT8 Flbas
; /* Formatted LBA Size */
465 UINT8 Mc
; /* Metadata Capabilities */
466 UINT8 Dpc
; /* End-to-end Data Protection capabilities */
467 UINT8 Dps
; /* End-to-end Data Protection Type Settings */
468 UINT8 Nmic
; /* Namespace Multi-path I/O and Namespace Sharing Capabilities */
469 UINT8 Rescap
; /* Reservation Capabilities */
470 UINT8 Rsvd1
[88]; /* Reserved as of Nvm Express 1.1 Spec */
471 UINT64 Eui64
; /* IEEE Extended Unique Identifier */
475 NVME_LBAFORMAT LbaFormat
[16];
477 UINT8 Rsvd2
[192]; /* Reserved as of Nvm Express 1.1 Spec */
478 UINT8 VendorData
[3712]; /* Vendor specific Data */
479 } NVME_ADMIN_NAMESPACE_DATA
;
482 // NvmExpress Admin Identify Cmd
490 } NVME_ADMIN_IDENTIFY
;
493 // NvmExpress Admin Create I/O Completion Queue
499 UINT32 Qid
:16; /* Queue Identifier */
500 UINT32 Qsize
:16; /* Queue Size */
505 UINT32 Pc
:1; /* Physically Contiguous */
506 UINT32 Ien
:1; /* Interrupts Enabled */
507 UINT32 Rsvd1
:14; /* reserved as of Nvm Express 1.1 Spec */
508 UINT32 Iv
:16; /* Interrupt Vector */
512 // NvmExpress Admin Create I/O Submission Queue
518 UINT32 Qid
:16; /* Queue Identifier */
519 UINT32 Qsize
:16; /* Queue Size */
524 UINT32 Pc
:1; /* Physically Contiguous */
525 UINT32 Qprio
:2; /* Queue Priority */
526 UINT32 Rsvd1
:13; /* Reserved as of Nvm Express 1.1 Spec */
527 UINT32 Cqid
:16; /* Completion Queue ID */
531 // NvmExpress Admin Delete I/O Completion Queue
542 // NvmExpress Admin Delete I/O Submission Queue
553 // NvmExpress Admin Security Send
559 UINT32 Resv
:8; /* Reserve */
560 UINT32 Spsp
:16; /* SP Specific */
561 UINT32 Secp
:8; /* Security Protocol */
566 UINT32 Tl
; /* Transfer Length */
567 } NVME_ADMIN_SECSEND
;
570 // NvmExpress Admin Abort Command
576 UINT32 Sqid
:16; /* Submission Queue identifier */
577 UINT32 Cid
:16; /* Command Identifier */
581 // NvmExpress Admin Firmware Activate Command
587 UINT32 Fs
:3; /* Submission Queue identifier */
588 UINT32 Aa
:2; /* Command Identifier */
590 } NVME_ADMIN_FIRMWARE_ACTIVATE
;
593 // NvmExpress Admin Firmware Image Download Command
599 UINT32 Numd
; /* Number of Dwords */
603 UINT32 Ofst
; /* Offset */
604 } NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD
;
607 // NvmExpress Admin Get Features Command
613 UINT32 Fid
:8; /* Feature Identifier */
614 UINT32 Sel
:3; /* Select */
616 } NVME_ADMIN_GET_FEATURES
;
619 // NvmExpress Admin Get Log Page Command
625 UINT32 Lid
:8; /* Log Page Identifier */
626 #define LID_ERROR_INFO
627 #define LID_SMART_INFO
628 #define LID_FW_SLOT_INFO
630 UINT32 Numd
:12; /* Number of Dwords */
631 UINT32 Rsvd2
:4; /* Reserved as of Nvm Express 1.1 Spec */
632 } NVME_ADMIN_GET_LOG_PAGE
;
635 // NvmExpress Admin Set Features Command
641 UINT32 Fid
:8; /* Feature Identifier */
643 UINT32 Sv
:1; /* Save */
644 } NVME_ADMIN_SET_FEATURES
;
647 // NvmExpress Admin Format NVM Command
653 UINT32 Lbaf
:4; /* LBA Format */
654 UINT32 Ms
:1; /* Metadata Settings */
655 UINT32 Pi
:3; /* Protection Information */
656 UINT32 Pil
:1; /* Protection Information Location */
657 UINT32 Ses
:3; /* Secure Erase Settings */
659 } NVME_ADMIN_FORMAT_NVM
;
662 // NvmExpress Admin Security Receive Command
669 UINT32 Spsp
:16; /* SP Specific */
670 UINT32 Secp
:8; /* Security Protocol */
674 UINT32 Al
; /* Allocation Length */
675 } NVME_ADMIN_SECURITY_RECEIVE
;
678 // NvmExpress Admin Security Send Command
685 UINT32 Spsp
:16; /* SP Specific */
686 UINT32 Secp
:8; /* Security Protocol */
690 UINT32 Tl
; /* Transfer Length */
691 } NVME_ADMIN_SECURITY_SEND
;
694 NVME_ADMIN_IDENTIFY Identify
;
695 NVME_ADMIN_CRIOCQ CrIoCq
;
696 NVME_ADMIN_CRIOSQ CrIoSq
;
697 NVME_ADMIN_DEIOCQ DeIoCq
;
698 NVME_ADMIN_DEIOSQ DeIoSq
;
699 NVME_ADMIN_ABORT Abort
;
700 NVME_ADMIN_FIRMWARE_ACTIVATE Activate
;
701 NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD FirmwareImageDownload
;
702 NVME_ADMIN_GET_FEATURES GetFeatures
;
703 NVME_ADMIN_GET_LOG_PAGE GetLogPage
;
704 NVME_ADMIN_SET_FEATURES SetFeatures
;
705 NVME_ADMIN_FORMAT_NVM FormatNvm
;
706 NVME_ADMIN_SECURITY_RECEIVE SecurityReceive
;
707 NVME_ADMIN_SECURITY_SEND SecuritySend
;
720 NVME_ADMIN_CMD Admin
; // Union of Admin commands
721 NVME_CMD Nvm
; // Union of Nvm commands
730 // CDW 0, Common to all comnmands
733 UINT8 Fuse
:2; // Fused Operation
735 UINT8 Psdt
:1; // PRP or SGL for Data Transfer
736 UINT16 Cid
; // Command Identifier
741 UINT32 Nsid
; // Namespace Identifier
751 UINT64 Mptr
; // Metadata Pointer
756 UINT64 Prp
[2]; // First and second PRP entries
758 NVME_PAYLOAD Payload
;
777 UINT16 Sqhd
; // Submission Queue Head Pointer
778 UINT16 Sqid
; // Submission Queue Identifier
782 UINT16 Cid
; // Command Identifier
783 UINT16 Pt
:1; // Phase Tag
784 UINT16 Sc
:8; // Status Code
785 UINT16 Sct
:3; // Status Code Type
788 UINT16 Dnr
:1; // Retry
792 // Nvm Express Admin cmd opcodes
794 #define NVME_ADMIN_DELIOSQ_OPC 0
795 #define NVME_ADMIN_CRIOSQ_OPC 1
796 #define NVME_ADMIN_DELIOCQ_OPC 4
797 #define NVME_ADMIN_CRIOCQ_OPC 5
798 #define NVME_ADMIN_IDENTIFY_OPC 6
799 #define NVME_ADMIN_SECURITY_SEND_OPC 0x81
800 #define NVME_ADMIN_SECURITY_RECV_OPC 0x82
802 #define NVME_IO_FLUSH_OPC 0
803 #define NVME_IO_WRITE_OPC 1
804 #define NVME_IO_READ_OPC 2
807 // Offset from the beginning of private Data queue Buffer
809 #define NVME_ASQ_BUF_OFFSET EFI_PAGE_SIZE