SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/ArchRegisters.h

   1 /** @file
   2   IA32 register defintions needed by debug transfer protocol.
   3
   4   Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php.
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef _ARCH_REGISTERS_H_
  16 #define _ARCH_REGISTERS_H_
  17
  18 ///
  19 /// FXSAVE_STATE
  20 /// FP / MMX / XMM registers (see fxrstor instruction definition)
  21 ///
  22 typedef struct {
  23   UINT16  Fcw;
  24   UINT16  Fsw;
  25   UINT16  Ftw;
  26   UINT16  Opcode;
  27   UINT32  Eip;
  28   UINT16  Cs;
  29   UINT16  Reserved1;
  30   UINT32  DataOffset;
  31   UINT16  Ds;
  32   UINT8   Reserved2[2];
  33   UINT32  Mxcsr;
  34   UINT32  Mxcsr_Mask;
  35   UINT8   St0Mm0[10];
  36   UINT8   Reserved3[6];
  37   UINT8   St1Mm1[10];
  38   UINT8   Reserved4[6];
  39   UINT8   St2Mm2[10];
  40   UINT8   Reserved5[6];
  41   UINT8   St3Mm3[10];
  42   UINT8   Reserved6[6];
  43   UINT8   St4Mm4[10];
  44   UINT8   Reserved7[6];
  45   UINT8   St5Mm5[10];
  46   UINT8   Reserved8[6];
  47   UINT8   St6Mm6[10];
  48   UINT8   Reserved9[6];
  49   UINT8   St7Mm7[10];
  50   UINT8   Reserved10[6];
  51   UINT8   Xmm0[16];
  52   UINT8   Xmm1[16];
  53   UINT8   Xmm2[16];
  54   UINT8   Xmm3[16];
  55   UINT8   Xmm4[16];
  56   UINT8   Xmm5[16];
  57   UINT8   Xmm6[16];
  58   UINT8   Xmm7[16];
  59   UINT8   Reserved11[14 * 16];
  60 } DEBUG_DATA_IA32_FX_SAVE_STATE;
  61
  62 ///
  63 ///  IA-32 processor context definition
  64 ///
  65 typedef struct {
  66   DEBUG_DATA_IA32_FX_SAVE_STATE  FxSaveState;
  67   UINT32                         Dr0;
  68   UINT32                         Dr1;
  69   UINT32                         Dr2;
  70   UINT32                         Dr3;
  71   UINT32                         Dr6;
  72   UINT32                         Dr7;
  73   UINT32                         Eflags;
  74   UINT32                         Ldtr;
  75   UINT32                         Tr;
  76   UINT32                         Gdtr[2];
  77   UINT32                         Idtr[2];
  78   UINT32                         Eip;
  79   UINT32                         Gs;
  80   UINT32                         Fs;
  81   UINT32                         Es;
  82   UINT32                         Ds;
  83   UINT32                         Cs;
  84   UINT32                         Ss;
  85   UINT32                         Cr0;
  86   UINT32                         Cr1;  ///< Reserved
  87   UINT32                         Cr2;
  88   UINT32                         Cr3;
  89   UINT32                         Cr4;
  90   UINT32                         Edi;
  91   UINT32                         Esi;
  92   UINT32                         Ebp;
  93   UINT32                         Esp;
  94   UINT32                         Edx;
  95   UINT32                         Ecx;
  96   UINT32                         Ebx;
  97   UINT32                         Eax;
  98 } DEBUG_DATA_IA32_SYSTEM_CONTEXT;
  99
 100 ///
 101 ///  IA32 GROUP register
 102 ///
 103 typedef struct {
 104   UINT16         Cs;
 105   UINT16         Ds;
 106   UINT16         Es;
 107   UINT16         Fs;
 108   UINT16         Gs;
 109   UINT16         Ss;
 110   UINT32         Eflags;
 111   UINT32         Ebp;
 112   UINT32         Eip;
 113   UINT32         Esp;
 114   UINT32         Eax;
 115   UINT32         Ebx;
 116   UINT32         Ecx;
 117   UINT32         Edx;
 118   UINT32         Esi;
 119   UINT32         Edi;
 120   UINT32         Dr0;
 121   UINT32         Dr1;
 122   UINT32         Dr2;
 123   UINT32         Dr3;
 124   UINT32         Dr6;
 125   UINT32         Dr7;
 126 } DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_IA32;
 127
 128 ///
 129 ///  IA32 Segment Limit GROUP register
 130 ///
 131 typedef struct {
 132   UINT32         CsLim;
 133   UINT32         SsLim;
 134   UINT32         GsLim;
 135   UINT32         FsLim;
 136   UINT32         EsLim;
 137   UINT32         DsLim;
 138   UINT32         LdtLim;
 139   UINT32         TssLim;
 140 } DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM_IA32;
 141
 142 ///
 143 ///  IA32 Segment Base GROUP register
 144 ///
 145 typedef struct {
 146   UINT32         CsBas;
 147   UINT32         SsBas;
 148   UINT32         GsBas;
 149   UINT32         FsBas;
 150   UINT32         EsBas;
 151   UINT32         DsBas;
 152   UINT32         LdtBas;
 153   UINT32         TssBas;
 154 } DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE_IA32;
 155
 156 #endif