]> git.proxmox.com Git - mirror_edk2.git/blob - SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/DebugCommunicationLibUsb3Internal.h
projects / mirror_edk2.git / blob
? search:


66757dafaebe7e9b916ad66f5e46d3d5b10e2474
[mirror_edk2.git] / SourceLevelDebugPkg / Library / DebugCommunicationLibUsb3 / DebugCommunicationLibUsb3Internal.h
1 /** @file
2 Debug Port Library implementation based on usb3 debug port.
3
4 Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php.
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #ifndef __USB3_DEBUG_PORT_LIB_INTERNAL__
16 #define __USB3_DEBUG_PORT_LIB_INTERNAL__
17
18 #include <Uefi.h>
19 #include <Base.h>
20 #include <IndustryStandard/Usb.h>
21 #include <Library/IoLib.h>
22 #include <IndustryStandard/Pci.h>
23 #include <Library/PcdLib.h>
24 #include <Library/UefiLib.h>
25 #include <Library/UefiBootServicesTableLib.h>
26 #include <Library/MemoryAllocationLib.h>
27 #include <Library/DebugLib.h>
28 #include <Library/BaseMemoryLib.h>
29 #include <Library/BaseLib.h>
30 #include <Library/TimerLib.h>
31 #include <Library/DebugCommunicationLib.h>
32 #include <Library/PciLib.h>
33
34 //
35 // USB Debug GUID value
36 //
37 #define USB3_DBG_GUID \
38 { \
39 0xb2a56f4d, 0x9177, 0x4fc8, { 0xa6, 0x77, 0xdd, 0x96, 0x3e, 0xb4, 0xcb, 0x1b } \
40 }
41
42 //
43 // The state machine of usb debug port
44 //
45 #define USB3DBG_NO_DBG_CAB 0 // The XHCI host controller does not support debug capability
46 #define USB3DBG_DBG_CAB 1 // The XHCI host controller supports debug capability
47 #define USB3DBG_ENABLED 2 // The XHCI debug device is enabled
48 #define USB3DBG_NOT_ENABLED 4 // The XHCI debug device is not enabled
49 #define USB3DBG_UNINITIALIZED 255 // The XHCI debug device is uninitialized
50
51 #define USB3_DEBUG_PORT_WRITE_MAX_PACKET_SIZE 0x08
52
53 //
54 // MaxPacketSize for DbC Endpoint Descriptor IN and OUT
55 //
56 #define XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE 0x400
57
58 #define XHCI_DEBUG_DEVICE_VENDOR_ID 0x0525
59 #define XHCI_DEBUG_DEVICE_PRODUCT_ID 0x127A
60 #define XHCI_DEBUG_DEVICE_PROTOCOL 0xFF
61 #define XHCI_DEBUG_DEVICE_REVISION 0x00
62
63 #define XHCI_BASE_ADDRESS_64_BIT_MASK 0xFFFFFFFFFFFF0000ULL
64 #define XHCI_BASE_ADDRESS_32_BIT_MASK 0xFFFF0000
65
66 #define PCI_CAPABILITY_ID_DEBUG_PORT 0x0A
67 #define XHC_HCCPARAMS_OFFSET 0x10
68 #define XHC_CAPABILITY_ID_MASK 0xFF
69 #define XHC_NEXT_CAPABILITY_MASK 0xFF00
70
71 #define XHC_HCSPARAMS1_OFFSET 0x4 // Structural Parameters 1
72 #define XHC_USBCMD_OFFSET 0x0 // USB Command Register Offset
73 #define XHC_USBSTS_OFFSET 0x4 // USB Status Register Offset
74 #define XHC_PORTSC_OFFSET 0x400 // Port Status and Control Register Offset
75
76 #define XHC_USBCMD_RUN BIT0 // Run/Stop
77 #define XHC_USBCMD_RESET BIT1 // Host Controller Reset
78
79 #define XHC_USBSTS_HALT BIT0
80
81 //
82 // Indicate the timeout when data is transferred in microsecond. 0 means infinite timeout.
83 //
84 #define DATA_TRANSFER_WRITE_TIMEOUT 0
85 #define DATA_TRANSFER_READ_TIMEOUT 50000
86 #define DATA_TRANSFER_POLL_TIMEOUT 1000
87 #define XHC_DEBUG_PORT_1_MILLISECOND 1000
88 //
89 // XHCI port power off/on delay
90 //
91 #define XHC_DEBUG_PORT_ON_OFF_DELAY 100000
92
93 //
94 // USB debug device string descritpor (header size + unicode string length)
95 //
96 #define STRING0_DESC_LEN 4
97 #define MANU_DESC_LEN 12
98 #define PRODUCT_DESC_LEN 40
99 #define SERIAL_DESC_LEN 4
100
101 //
102 // Debug Capability Register Offset
103 //
104 #define XHC_DC_DCID 0x0
105 #define XHC_DC_DCDB 0x4
106 #define XHC_DC_DCERSTSZ 0x8
107 #define XHC_DC_DCERSTBA 0x10
108 #define XHC_DC_DCERDP 0x18
109 #define XHC_DC_DCCTRL 0x20
110 #define XHC_DC_DCST 0x24
111 #define XHC_DC_DCPORTSC 0x28
112 #define XHC_DC_DCCP 0x30
113 #define XHC_DC_DCDDI1 0x38
114 #define XHC_DC_DCDDI2 0x3C
115
116 #define TRB_TYPE_LINK 6
117
118 #define ERST_NUMBER 0x01
119 #define TR_RING_TRB_NUMBER 0x100
120 #define EVENT_RING_TRB_NUMBER 0x200
121
122 #define ED_BULK_OUT 2
123 #define ED_BULK_IN 6
124
125 #define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))
126 #define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINT64)(UINTN)(Addr64), 32) & 0xFFFFFFFF))
127 #define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
128
129 //
130 // Endpoint Type (EP Type).
131 //
132 #define ED_NOT_VALID 0
133 #define ED_ISOCH_OUT 1
134 #define ED_BULK_OUT 2
135 #define ED_INTERRUPT_OUT 3
136 #define ED_CONTROL_BIDIR 4
137 #define ED_ISOCH_IN 5
138 #define ED_BULK_IN 6
139 #define ED_INTERRUPT_IN 7
140
141 //
142 // 6.4.5 TRB Completion Codes
143 //
144 #define TRB_COMPLETION_INVALID 0
145 #define TRB_COMPLETION_SUCCESS 1
146 #define TRB_COMPLETION_DATA_BUFFER_ERROR 2
147 #define TRB_COMPLETION_BABBLE_ERROR 3
148 #define TRB_COMPLETION_USB_TRANSACTION_ERROR 4
149 #define TRB_COMPLETION_TRB_ERROR 5
150 #define TRB_COMPLETION_STALL_ERROR 6
151 #define TRB_COMPLETION_SHORT_PACKET 13
152
153 //
154 // 6.4.6 TRB Types
155 //
156 #define TRB_TYPE_NORMAL 1
157 #define TRB_TYPE_SETUP_STAGE 2
158 #define TRB_TYPE_DATA_STAGE 3
159 #define TRB_TYPE_STATUS_STAGE 4
160 #define TRB_TYPE_ISOCH 5
161 #define TRB_TYPE_LINK 6
162 #define TRB_TYPE_EVENT_DATA 7
163 #define TRB_TYPE_NO_OP 8
164 #define TRB_TYPE_EN_SLOT 9
165 #define TRB_TYPE_DIS_SLOT 10
166 #define TRB_TYPE_ADDRESS_DEV 11
167 #define TRB_TYPE_CON_ENDPOINT 12
168 #define TRB_TYPE_EVALU_CONTXT 13
169 #define TRB_TYPE_RESET_ENDPOINT 14
170 #define TRB_TYPE_STOP_ENDPOINT 15
171 #define TRB_TYPE_SET_TR_DEQUE 16
172 #define TRB_TYPE_RESET_DEV 17
173 #define TRB_TYPE_GET_PORT_BANW 21
174 #define TRB_TYPE_FORCE_HEADER 22
175 #define TRB_TYPE_NO_OP_COMMAND 23
176 #define TRB_TYPE_TRANS_EVENT 32
177 #define TRB_TYPE_COMMAND_COMPLT_EVENT 33
178 #define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34
179 #define TRB_TYPE_HOST_CONTROLLER_EVENT 37
180 #define TRB_TYPE_DEVICE_NOTIFI_EVENT 38
181 #define TRB_TYPE_MFINDEX_WRAP_EVENT 39
182
183 //
184 // Convert millisecond to microsecond.
185 //
186 #define XHC_1_MILLISECOND (1000)
187 #define XHC_POLL_DELAY (1000)
188 #define XHC_GENERIC_TIMEOUT (10 * 1000)
189
190 #define EFI_USB_SPEED_FULL 0x0000 ///< 12 Mb/s, USB 1.1 OHCI and UHCI HC.
191 #define EFI_USB_SPEED_LOW 0x0001 ///< 1 Mb/s, USB 1.1 OHCI and UHCI HC.
192 #define EFI_USB_SPEED_HIGH 0x0002 ///< 480 Mb/s, USB 2.0 EHCI HC.
193 #define EFI_USB_SPEED_SUPER 0x0003 ///< 4.8 Gb/s, USB 3.0 XHCI HC.
194
195 //
196 // Transfer types, used in URB to identify the transfer type
197 //
198 #define XHC_CTRL_TRANSFER 0x01
199 #define XHC_BULK_TRANSFER 0x02
200 #define XHC_INT_TRANSFER_SYNC 0x04
201 #define XHC_INT_TRANSFER_ASYNC 0x08
202 #define XHC_INT_ONLY_TRANSFER_ASYNC 0x10
203
204 //
205 // USB Transfer Results
206 //
207 #define EFI_USB_NOERROR 0x00
208 #define EFI_USB_ERR_NOTEXECUTE 0x01
209 #define EFI_USB_ERR_STALL 0x02
210 #define EFI_USB_ERR_BUFFER 0x04
211 #define EFI_USB_ERR_BABBLE 0x08
212 #define EFI_USB_ERR_NAK 0x10
213 #define EFI_USB_ERR_CRC 0x20
214 #define EFI_USB_ERR_TIMEOUT 0x40
215 #define EFI_USB_ERR_BITSTUFF 0x80
216 #define EFI_USB_ERR_SYSTEM 0x100
217
218 #pragma pack(1)
219
220 //
221 // 7.6.9 OUT/IN EP Context: 64 bytes
222 // 7.6.9.2 When used by the DbC it is always a 64 byte data structure
223 //
224 typedef struct _ENDPOINT_CONTEXT_64 {
225 UINT32 EPState:3;
226 UINT32 RsvdZ1:5;
227 UINT32 Mult:2; // set to 0
228 UINT32 MaxPStreams:5; // set to 0
229 UINT32 LSA:1; // set to 0
230 UINT32 Interval:8; // set to 0
231 UINT32 RsvdZ2:8;
232
233 UINT32 RsvdZ3:1;
234 UINT32 CErr:2;
235 UINT32 EPType:3;
236 UINT32 RsvdZ4:1;
237 UINT32 HID:1; // set to 0
238 UINT32 MaxBurstSize:8;
239 UINT32 MaxPacketSize:16;
240
241 UINT32 PtrLo;
242
243 UINT32 PtrHi;
244
245 UINT32 AverageTRBLength:16;
246 UINT32 MaxESITPayload:16; // set to 0
247
248 UINT32 RsvdZ5; // Reserved
249 UINT32 RsvdZ6;
250 UINT32 RsvdZ7;
251
252 UINT32 RsvdZ8;
253 UINT32 RsvdZ9;
254 UINT32 RsvdZ10;
255 UINT32 RsvdZ11;
256
257 UINT32 RsvdZ12;
258 UINT32 RsvdZ13;
259 UINT32 RsvdZ14;
260 UINT32 RsvdZ15;
261 } ENDPOINT_CONTEXT_64;
262
263 //
264 // 6.4.1.1 Normal TRB: 16 bytes
265 // A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and
266 // Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer
267 // Rings, and to define the Data stage information for Control Transfer Rings.
268 //
269 typedef struct _TRANSFER_TRB_NORMAL {
270 UINT32 TRBPtrLo;
271
272 UINT32 TRBPtrHi;
273
274 UINT32 Length:17;
275 UINT32 TDSize:5;
276 UINT32 IntTarget:10;
277
278 UINT32 CycleBit:1;
279 UINT32 ENT:1;
280 UINT32 ISP:1;
281 UINT32 NS:1;
282 UINT32 CH:1;
283 UINT32 IOC:1;
284 UINT32 IDT:1;
285 UINT32 RsvdZ1:2;
286 UINT32 BEI:1;
287 UINT32 Type:6;
288 UINT32 RsvdZ2:16;
289 } TRANSFER_TRB_NORMAL;
290
291 //
292 // 6.4.2.1 Transfer Event TRB: 16 bytes
293 // A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1
294 // for more information on the use and operation of Transfer Events.
295 //
296 typedef struct _EVT_TRB_TRANSFER {
297 UINT32 TRBPtrLo;
298
299 UINT32 TRBPtrHi;
300
301 UINT32 Length:24;
302 UINT32 Completecode:8;
303
304 UINT32 CycleBit:1;
305 UINT32 RsvdZ1:1;
306 UINT32 ED:1;
307 UINT32 RsvdZ2:7;
308 UINT32 Type:6;
309 UINT32 EndpointId:5;
310 UINT32 RsvdZ3:3;
311 UINT32 SlotId:8;
312 } EVT_TRB_TRANSFER;
313
314 //
315 // 6.4.4.1 Link TRB: 16 bytes
316 // A Link TRB provides support for non-contiguous TRB Rings.
317 //
318 typedef struct _LINK_TRB {
319 UINT32 PtrLo;
320
321 UINT32 PtrHi;
322
323 UINT32 RsvdZ1:22;
324 UINT32 InterTarget:10;
325
326 UINT32 CycleBit:1;
327 UINT32 TC:1;
328 UINT32 RsvdZ2:2;
329 UINT32 CH:1;
330 UINT32 IOC:1;
331 UINT32 RsvdZ3:4;
332 UINT32 Type:6;
333 UINT32 RsvdZ4:16;
334 } LINK_TRB;
335
336 //
337 // TRB Template: 16 bytes
338 //
339 typedef struct _TRB_TEMPLATE {
340 UINT32 Parameter1;
341
342 UINT32 Parameter2;
343
344 UINT32 Status;
345
346 UINT32 CycleBit:1;
347 UINT32 RsvdZ1:9;
348 UINT32 Type:6;
349 UINT32 Control:16;
350 } TRB_TEMPLATE;
351
352 //
353 // Refer to XHCI 6.5 Event Ring Segment Table: 16 bytes
354 //
355 typedef struct _EVENT_RING_SEG_TABLE_ENTRY {
356 UINT32 PtrLo;
357 UINT32 PtrHi;
358 UINT32 RingTrbSize:16;
359 UINT32 RsvdZ1:16;
360 UINT32 RsvdZ2;
361 } EVENT_RING_SEG_TABLE_ENTRY;
362
363 //
364 // Size: 40 bytes
365 //
366 typedef struct _EVENT_RING {
367 EFI_PHYSICAL_ADDRESS ERSTBase;
368 EFI_PHYSICAL_ADDRESS EventRingSeg0;
369 UINT32 TrbNumber;
370 EFI_PHYSICAL_ADDRESS EventRingEnqueue;
371 EFI_PHYSICAL_ADDRESS EventRingDequeue;
372 UINT32 EventRingCCS;
373 } EVENT_RING;
374
375 // Size: 32 bytes
376 typedef struct _TRANSFER_RING {
377 EFI_PHYSICAL_ADDRESS RingSeg0;
378 UINT32 TrbNumber;
379 EFI_PHYSICAL_ADDRESS RingEnqueue;
380 EFI_PHYSICAL_ADDRESS RingDequeue;
381 UINT32 RingPCS;
382 } TRANSFER_RING;
383
384 //
385 // Size: 64 bytes
386 //
387 typedef struct _DBC_INFO_CONTEXT {
388 UINT64 String0DescAddress;
389 UINT64 ManufacturerStrDescAddress;
390 UINT64 ProductStrDescAddress;
391 UINT64 SerialNumberStrDescAddress;
392 UINT64 String0Length:8;
393 UINT64 ManufacturerStrLength:8;
394 UINT64 ProductStrLength:8;
395 UINT64 SerialNumberStrLength:8;
396 UINT64 RsvdZ1:32;
397 UINT64 RsvdZ2;
398 UINT64 RsvdZ3;
399 UINT64 RsvdZ4;
400 } DBC_INFO_CONTEXT;
401
402 //
403 // Debug Capability Context Data Structure: 192 bytes
404 //
405 typedef struct _XHC_DC_CONTEXT {
406 DBC_INFO_CONTEXT DbcInfoContext;
407 ENDPOINT_CONTEXT_64 EpOutContext;
408 ENDPOINT_CONTEXT_64 EpInContext;
409 } XHC_DC_CONTEXT;
410
411 //
412 // Size: 16 bytes
413 //
414 typedef union _TRB {
415 TRB_TEMPLATE TrbTemplate;
416 TRANSFER_TRB_NORMAL TrbNormal;
417 } TRB;
418
419 ///
420 /// USB data transfer direction
421 ///
422 typedef enum {
423 EfiUsbDataIn,
424 EfiUsbDataOut,
425 EfiUsbNoData
426 } EFI_USB_DATA_DIRECTION;
427
428 //
429 // URB (Usb Request Block) contains information for all kinds of
430 // usb requests.
431 //
432 typedef struct _URB {
433 //
434 // Transfer data buffer
435 //
436 EFI_PHYSICAL_ADDRESS Data;
437 UINT32 DataLen;
438
439 //
440 // Execute result
441 //
442 UINT32 Result;
443 //
444 // Completed data length
445 //
446 UINT32 Completed;
447 //
448 // Tranfer Ring info
449 //
450 EFI_PHYSICAL_ADDRESS Ring;
451 EFI_PHYSICAL_ADDRESS Trb;
452 BOOLEAN Finished;
453 EFI_USB_DATA_DIRECTION Direction;
454 } URB;
455
456 typedef struct _USB3_DEBUG_PORT_INSTANCE {
457 UINT8 Initialized;
458
459 //
460 // The flag indicates debug capability is supported
461 //
462 BOOLEAN DebugSupport;
463
464 //
465 // The flag indicates debug device is ready
466 //
467 BOOLEAN Ready;
468
469 //
470 // The flag indicates the instance is from HOB
471 //
472 BOOLEAN FromHob;
473
474 //
475 // IOMMU PPI Notify registered
476 //
477 BOOLEAN PpiNotifyRegistered;
478
479 //
480 // Prevent notification being interrupted by debug timer
481 //
482 BOOLEAN InNotify;
483
484 //
485 // PciIo protocol event
486 //
487 EFI_PHYSICAL_ADDRESS PciIoEvent;
488
489 //
490 // The flag indicates if USB 3.0 ports has been turn off/on power
491 //
492 BOOLEAN ChangePortPower;
493
494 //
495 // XHCI MMIO Base address
496 //
497 EFI_PHYSICAL_ADDRESS XhciMmioBase;
498
499 //
500 // XHCI OP RegisterBase address
501 //
502 EFI_PHYSICAL_ADDRESS XhciOpRegister;
503
504 //
505 // XHCI Debug Register Base Address
506 //
507 EFI_PHYSICAL_ADDRESS DebugCapabilityBase;
508
509 //
510 // XHCI Debug Capability offset
511 //
512 UINT64 DebugCapabilityOffset;
513
514 //
515 // XHCI Debug Context Address
516 //
517 EFI_PHYSICAL_ADDRESS DebugCapabilityContext;
518
519 //
520 // Transfer Ring
521 //
522 TRANSFER_RING TransferRingOut;
523 TRANSFER_RING TransferRingIn;
524
525 //
526 // EventRing
527 //
528 EVENT_RING EventRing;
529
530 //
531 // URB - Read
532 //
533 URB UrbOut;
534
535 //
536 // URB - Write
537 //
538 URB UrbIn;
539
540 //
541 // The available data length in the following data buffer.
542 //
543 UINT8 DataCount;
544 //
545 // The data buffer address for data read and poll.
546 //
547 EFI_PHYSICAL_ADDRESS Data;
548 } USB3_DEBUG_PORT_HANDLE;
549
550 #pragma pack()
551
552 /**
553 Read XHCI debug register.
554
555 @param Handle Debug port handle.
556 @param Offset The offset of the debug register.
557
558 @return The register content read
559
560 **/
561 UINT32
562 XhcReadDebugReg (
563 IN USB3_DEBUG_PORT_HANDLE *Handle,
564 IN UINT32 Offset
565 );
566
567 /**
568 Set one bit of the debug register while keeping other bits.
569
570 @param Handle Debug port handle.
571 @param Offset The offset of the debug register.
572 @param Bit The bit mask of the register to set.
573
574 **/
575 VOID
576 XhcSetDebugRegBit (
577 IN USB3_DEBUG_PORT_HANDLE *Handle,
578 IN UINT32 Offset,
579 IN UINT32 Bit
580 );
581
582 /**
583 Write the data to the debug register.
584
585 @param Handle Debug port handle.
586 @param Offset The offset of the debug register.
587 @param Data The data to write.
588
589 **/
590 VOID
591 XhcWriteDebugReg (
592 IN USB3_DEBUG_PORT_HANDLE *Handle,
593 IN UINT32 Offset,
594 IN UINT32 Data
595 );
596
597 /**
598 Discover the USB3 debug device.
599
600 @param Handle Debug port handle.
601
602 @retval RETURN_SUCCESS The serial device was initialized.
603 @retval RETURN_DEVICE_ERROR The serial device could not be initialized.
604
605 **/
606 RETURN_STATUS
607 DiscoverUsb3DebugPort(
608 USB3_DEBUG_PORT_HANDLE *Handle
609 );
610
611 /**
612 Initialize the Serial Device hardware.
613
614 @param Handle Debug port handle.
615
616 @retval RETURN_SUCCESS The serial device was initialized successfully.
617 @retval !RETURN_SUCCESS Error.
618
619 **/
620 RETURN_STATUS
621 InitializeUsb3DebugPort (
622 USB3_DEBUG_PORT_HANDLE *Handle
623 );
624
625 /**
626 Return XHCI MMIO base address.
627
628 **/
629 EFI_PHYSICAL_ADDRESS
630 GetXhciBaseAddress (
631 VOID
632 );
633
634 /**
635 Verifies if the bit positions specified by a mask are set in a register.
636
637 @param[in, out] Register UNITN register
638 @param[in] BitMask 32-bit mask
639
640 @return BOOLEAN - TRUE if all bits specified by the mask are enabled.
641 - FALSE even if one of the bits specified by the mask
642 is not enabled.
643 **/
644 BOOLEAN
645 XhcIsBitSet(
646 UINTN Register,
647 UINT32 BitMask
648 );
649
650 /**
651 Sets bits as per the enabled bit positions in the mask.
652
653 @param[in, out] Register UINTN register
654 @param[in] BitMask 32-bit mask
655 **/
656 VOID
657 XhcSetR32Bit(
658 UINTN Register,
659 UINT32 BitMask
660 );
661
662 /**
663 Clears bits as per the enabled bit positions in the mask.
664
665 @param[in, out] Register UINTN register
666 @param[in] BitMask 32-bit mask
667 **/
668 VOID
669 XhcClearR32Bit(
670 IN OUT UINTN Register,
671 IN UINT32 BitMask
672 );
673
674 /**
675 Initialize USB3 debug port.
676
677 This method invokes various internal functions to facilitate
678 detection and initialization of USB3 debug port.
679
680 @retval RETURN_SUCCESS The serial device was initialized.
681 **/
682 RETURN_STATUS
683 EFIAPI
684 USB3Initialize (
685 VOID
686 );
687
688 /**
689 Return command register value in XHCI controller.
690
691 **/
692 UINT16
693 GetXhciPciCommand (
694 VOID
695 );
696
697 /**
698 Allocate aligned memory for XHC's usage.
699
700 @param BufferSize The size, in bytes, of the Buffer.
701
702 @return A pointer to the allocated buffer or NULL if allocation fails.
703
704 **/
705 VOID*
706 AllocateAlignBuffer (
707 IN UINTN BufferSize
708 );
709
710 /**
711 The real function to initialize USB3 debug port.
712
713 This method invokes various internal functions to facilitate
714 detection and initialization of USB3 debug port.
715
716 @retval RETURN_SUCCESS The serial device was initialized.
717 **/
718 RETURN_STATUS
719 EFIAPI
720 USB3InitializeReal (
721 VOID
722 );
723
724 /**
725 Submits bulk transfer to a bulk endpoint of a USB device.
726
727 @param Handle The instance of debug device.
728 @param Direction The direction of data transfer.
729 @param Data Array of pointers to the buffers of data to transmit
730 from or receive into.
731 @param DataLength The lenght of the data buffer.
732 @param Timeout Indicates the maximum time, in millisecond, which
733 the transfer is allowed to complete.
734
735 @retval EFI_SUCCESS The transfer was completed successfully.
736 @retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resource.
737 @retval EFI_INVALID_PARAMETER Some parameters are invalid.
738 @retval EFI_TIMEOUT The transfer failed due to timeout.
739 @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.
740
741 **/
742 EFI_STATUS
743 EFIAPI
744 XhcDataTransfer (
745 IN USB3_DEBUG_PORT_HANDLE *Handle,
746 IN EFI_USB_DATA_DIRECTION Direction,
747 IN OUT VOID *Data,
748 IN OUT UINTN *DataLength,
749 IN UINTN Timeout
750 );
751
752 /**
753 Initialize usb debug port hardware.
754
755 @param Handle Debug port handle.
756
757 @retval TRUE The usb debug port hardware configuration is changed.
758 @retval FALSE The usb debug port hardware configuration is not changed.
759
760 **/
761 RETURN_STATUS
762 EFIAPI
763 InitializeUsbDebugHardware (
764 IN USB3_DEBUG_PORT_HANDLE *Handle
765 );
766
767 /**
768 Discover and initialize usb debug port.
769
770 @param Handle Debug port handle.
771
772 **/
773 VOID
774 DiscoverInitializeUsbDebugPort (
775 IN USB3_DEBUG_PORT_HANDLE *Handle
776 );
777
778 /**
779 Return USB3 debug instance address.
780
781 **/
782 USB3_DEBUG_PORT_HANDLE *
783 GetUsb3DebugPortInstance (
784 VOID
785 );
786
787 #endif //__SERIAL_PORT_LIB_USB__
EFI Development Kit II mirror for PVE