2 Debug Port Library implementation based on usb3 debug port.
4 Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php.
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #ifndef __USB3_DEBUG_PORT_LIB_INTERNAL__
16 #define __USB3_DEBUG_PORT_LIB_INTERNAL__
20 #include <IndustryStandard/Usb.h>
21 #include <Library/IoLib.h>
22 #include <IndustryStandard/Pci.h>
23 #include <Library/PcdLib.h>
24 #include <Library/UefiLib.h>
25 #include <Library/UefiBootServicesTableLib.h>
26 #include <Library/MemoryAllocationLib.h>
27 #include <Library/DebugLib.h>
28 #include <Library/BaseMemoryLib.h>
29 #include <Library/BaseLib.h>
30 #include <Library/TimerLib.h>
31 #include <Library/DebugCommunicationLib.h>
32 #include <Library/PciLib.h>
35 // USB Debug GUID value
37 #define USB3_DBG_GUID \
39 0xb2a56f4d, 0x9177, 0x4fc8, { 0xa6, 0x77, 0xdd, 0x96, 0x3e, 0xb4, 0xcb, 0x1b } \
43 // The state machine of usb debug port
45 #define USB3DBG_NO_DBG_CAB 0 // The XHCI host controller does not support debug capability
46 #define USB3DBG_DBG_CAB 1 // The XHCI host controller supports debug capability
47 #define USB3DBG_ENABLED 2 // The XHCI debug device is enabled
48 #define USB3DBG_NOT_ENABLED 4 // The XHCI debug device is not enabled
49 #define USB3DBG_UNINITIALIZED 255 // The XHCI debug device is uninitialized
51 #define USB3_DEBUG_PORT_WRITE_MAX_PACKET_SIZE 0x08
54 // MaxPacketSize for DbC Endpoint Descriptor IN and OUT
56 #define XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE 0x400
58 #define XHCI_DEBUG_DEVICE_VENDOR_ID 0x0525
59 #define XHCI_DEBUG_DEVICE_PRODUCT_ID 0x127A
60 #define XHCI_DEBUG_DEVICE_PROTOCOL 0xFF
61 #define XHCI_DEBUG_DEVICE_REVISION 0x00
63 #define XHCI_BASE_ADDRESS_64_BIT_MASK 0xFFFFFFFFFFFF0000ULL
64 #define XHCI_BASE_ADDRESS_32_BIT_MASK 0xFFFF0000
66 #define PCI_CAPABILITY_ID_DEBUG_PORT 0x0A
67 #define XHC_HCCPARAMS_OFFSET 0x10
68 #define XHC_CAPABILITY_ID_MASK 0xFF
69 #define XHC_NEXT_CAPABILITY_MASK 0xFF00
71 #define XHC_HCSPARAMS1_OFFSET 0x4 // Structural Parameters 1
72 #define XHC_USBCMD_OFFSET 0x0 // USB Command Register Offset
73 #define XHC_USBSTS_OFFSET 0x4 // USB Status Register Offset
74 #define XHC_PORTSC_OFFSET 0x400 // Port Status and Control Register Offset
76 #define XHC_USBCMD_RUN BIT0 // Run/Stop
77 #define XHC_USBCMD_RESET BIT1 // Host Controller Reset
79 #define XHC_USBSTS_HALT BIT0
82 // Indicate the timeout when data is transferred in microsecond. 0 means infinite timeout.
84 #define DATA_TRANSFER_WRITE_TIMEOUT 0
85 #define DATA_TRANSFER_READ_TIMEOUT 50000
86 #define DATA_TRANSFER_POLL_TIMEOUT 1000
87 #define XHC_DEBUG_PORT_1_MILLISECOND 1000
89 // XHCI port power off/on delay
91 #define XHC_DEBUG_PORT_ON_OFF_DELAY 100000
94 // USB debug device string descritpor (header size + unicode string length)
96 #define STRING0_DESC_LEN 4
97 #define MANU_DESC_LEN 12
98 #define PRODUCT_DESC_LEN 40
99 #define SERIAL_DESC_LEN 4
102 // Debug Capability Register Offset
104 #define XHC_DC_DCID 0x0
105 #define XHC_DC_DCDB 0x4
106 #define XHC_DC_DCERSTSZ 0x8
107 #define XHC_DC_DCERSTBA 0x10
108 #define XHC_DC_DCERDP 0x18
109 #define XHC_DC_DCCTRL 0x20
110 #define XHC_DC_DCST 0x24
111 #define XHC_DC_DCPORTSC 0x28
112 #define XHC_DC_DCCP 0x30
113 #define XHC_DC_DCDDI1 0x38
114 #define XHC_DC_DCDDI2 0x3C
116 #define TRB_TYPE_LINK 6
118 #define ERST_NUMBER 0x01
119 #define TR_RING_TRB_NUMBER 0x100
120 #define EVENT_RING_TRB_NUMBER 0x200
122 #define ED_BULK_OUT 2
125 #define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))
126 #define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINT64)(UINTN)(Addr64), 32) & 0xFFFFFFFF))
127 #define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
130 // Endpoint Type (EP Type).
132 #define ED_NOT_VALID 0
133 #define ED_ISOCH_OUT 1
134 #define ED_BULK_OUT 2
135 #define ED_INTERRUPT_OUT 3
136 #define ED_CONTROL_BIDIR 4
137 #define ED_ISOCH_IN 5
139 #define ED_INTERRUPT_IN 7
142 // 6.4.5 TRB Completion Codes
144 #define TRB_COMPLETION_INVALID 0
145 #define TRB_COMPLETION_SUCCESS 1
146 #define TRB_COMPLETION_DATA_BUFFER_ERROR 2
147 #define TRB_COMPLETION_BABBLE_ERROR 3
148 #define TRB_COMPLETION_USB_TRANSACTION_ERROR 4
149 #define TRB_COMPLETION_TRB_ERROR 5
150 #define TRB_COMPLETION_STALL_ERROR 6
151 #define TRB_COMPLETION_SHORT_PACKET 13
156 #define TRB_TYPE_NORMAL 1
157 #define TRB_TYPE_SETUP_STAGE 2
158 #define TRB_TYPE_DATA_STAGE 3
159 #define TRB_TYPE_STATUS_STAGE 4
160 #define TRB_TYPE_ISOCH 5
161 #define TRB_TYPE_LINK 6
162 #define TRB_TYPE_EVENT_DATA 7
163 #define TRB_TYPE_NO_OP 8
164 #define TRB_TYPE_EN_SLOT 9
165 #define TRB_TYPE_DIS_SLOT 10
166 #define TRB_TYPE_ADDRESS_DEV 11
167 #define TRB_TYPE_CON_ENDPOINT 12
168 #define TRB_TYPE_EVALU_CONTXT 13
169 #define TRB_TYPE_RESET_ENDPOINT 14
170 #define TRB_TYPE_STOP_ENDPOINT 15
171 #define TRB_TYPE_SET_TR_DEQUE 16
172 #define TRB_TYPE_RESET_DEV 17
173 #define TRB_TYPE_GET_PORT_BANW 21
174 #define TRB_TYPE_FORCE_HEADER 22
175 #define TRB_TYPE_NO_OP_COMMAND 23
176 #define TRB_TYPE_TRANS_EVENT 32
177 #define TRB_TYPE_COMMAND_COMPLT_EVENT 33
178 #define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34
179 #define TRB_TYPE_HOST_CONTROLLER_EVENT 37
180 #define TRB_TYPE_DEVICE_NOTIFI_EVENT 38
181 #define TRB_TYPE_MFINDEX_WRAP_EVENT 39
184 // Convert millisecond to microsecond.
186 #define XHC_1_MILLISECOND (1000)
187 #define XHC_POLL_DELAY (1000)
188 #define XHC_GENERIC_TIMEOUT (10 * 1000)
190 #define EFI_USB_SPEED_FULL 0x0000 ///< 12 Mb/s, USB 1.1 OHCI and UHCI HC.
191 #define EFI_USB_SPEED_LOW 0x0001 ///< 1 Mb/s, USB 1.1 OHCI and UHCI HC.
192 #define EFI_USB_SPEED_HIGH 0x0002 ///< 480 Mb/s, USB 2.0 EHCI HC.
193 #define EFI_USB_SPEED_SUPER 0x0003 ///< 4.8 Gb/s, USB 3.0 XHCI HC.
196 // Transfer types, used in URB to identify the transfer type
198 #define XHC_CTRL_TRANSFER 0x01
199 #define XHC_BULK_TRANSFER 0x02
200 #define XHC_INT_TRANSFER_SYNC 0x04
201 #define XHC_INT_TRANSFER_ASYNC 0x08
202 #define XHC_INT_ONLY_TRANSFER_ASYNC 0x10
205 // USB Transfer Results
207 #define EFI_USB_NOERROR 0x00
208 #define EFI_USB_ERR_NOTEXECUTE 0x01
209 #define EFI_USB_ERR_STALL 0x02
210 #define EFI_USB_ERR_BUFFER 0x04
211 #define EFI_USB_ERR_BABBLE 0x08
212 #define EFI_USB_ERR_NAK 0x10
213 #define EFI_USB_ERR_CRC 0x20
214 #define EFI_USB_ERR_TIMEOUT 0x40
215 #define EFI_USB_ERR_BITSTUFF 0x80
216 #define EFI_USB_ERR_SYSTEM 0x100
221 // 7.6.9 OUT/IN EP Context: 64 bytes
222 // 7.6.9.2 When used by the DbC it is always a 64 byte data structure
224 typedef struct _ENDPOINT_CONTEXT_64
{
227 UINT32 Mult
:2; // set to 0
228 UINT32 MaxPStreams
:5; // set to 0
229 UINT32 LSA
:1; // set to 0
230 UINT32 Interval
:8; // set to 0
237 UINT32 HID
:1; // set to 0
238 UINT32 MaxBurstSize
:8;
239 UINT32 MaxPacketSize
:16;
245 UINT32 AverageTRBLength
:16;
246 UINT32 MaxESITPayload
:16; // set to 0
248 UINT32 RsvdZ5
; // Reserved
261 } ENDPOINT_CONTEXT_64
;
264 // 6.4.1.1 Normal TRB: 16 bytes
265 // A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and
266 // Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer
267 // Rings, and to define the Data stage information for Control Transfer Rings.
269 typedef struct _TRANSFER_TRB_NORMAL
{
289 } TRANSFER_TRB_NORMAL
;
292 // 6.4.2.1 Transfer Event TRB: 16 bytes
293 // A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1
294 // for more information on the use and operation of Transfer Events.
296 typedef struct _EVT_TRB_TRANSFER
{
302 UINT32 Completecode
:8;
315 // 6.4.4.1 Link TRB: 16 bytes
316 // A Link TRB provides support for non-contiguous TRB Rings.
318 typedef struct _LINK_TRB
{
324 UINT32 InterTarget
:10;
337 // TRB Template: 16 bytes
339 typedef struct _TRB_TEMPLATE
{
353 // Refer to XHCI 6.5 Event Ring Segment Table: 16 bytes
355 typedef struct _EVENT_RING_SEG_TABLE_ENTRY
{
358 UINT32 RingTrbSize
:16;
361 } EVENT_RING_SEG_TABLE_ENTRY
;
366 typedef struct _EVENT_RING
{
367 EFI_PHYSICAL_ADDRESS ERSTBase
;
368 EFI_PHYSICAL_ADDRESS EventRingSeg0
;
370 EFI_PHYSICAL_ADDRESS EventRingEnqueue
;
371 EFI_PHYSICAL_ADDRESS EventRingDequeue
;
376 typedef struct _TRANSFER_RING
{
377 EFI_PHYSICAL_ADDRESS RingSeg0
;
379 EFI_PHYSICAL_ADDRESS RingEnqueue
;
380 EFI_PHYSICAL_ADDRESS RingDequeue
;
387 typedef struct _DBC_INFO_CONTEXT
{
388 UINT64 String0DescAddress
;
389 UINT64 ManufacturerStrDescAddress
;
390 UINT64 ProductStrDescAddress
;
391 UINT64 SerialNumberStrDescAddress
;
392 UINT64 String0Length
:8;
393 UINT64 ManufacturerStrLength
:8;
394 UINT64 ProductStrLength
:8;
395 UINT64 SerialNumberStrLength
:8;
403 // Debug Capability Context Data Structure: 192 bytes
405 typedef struct _XHC_DC_CONTEXT
{
406 DBC_INFO_CONTEXT DbcInfoContext
;
407 ENDPOINT_CONTEXT_64 EpOutContext
;
408 ENDPOINT_CONTEXT_64 EpInContext
;
415 TRB_TEMPLATE TrbTemplate
;
416 TRANSFER_TRB_NORMAL TrbNormal
;
420 /// USB data transfer direction
426 } EFI_USB_DATA_DIRECTION
;
429 // URB (Usb Request Block) contains information for all kinds of
432 typedef struct _URB
{
434 // Transfer data buffer
436 EFI_PHYSICAL_ADDRESS Data
;
444 // Completed data length
450 EFI_PHYSICAL_ADDRESS Ring
;
451 EFI_PHYSICAL_ADDRESS Trb
;
453 EFI_USB_DATA_DIRECTION Direction
;
456 typedef struct _USB3_DEBUG_PORT_INSTANCE
{
460 // The flag indicates debug capability is supported
462 BOOLEAN DebugSupport
;
465 // The flag indicates debug device is ready
470 // The flag indicates the instance is from HOB
475 // Prevent notification being interrupted by debug timer
480 // PciIo protocol event
482 EFI_PHYSICAL_ADDRESS PciIoEvent
;
485 // The flag indicates if USB 3.0 ports has been turn off/on power
487 BOOLEAN ChangePortPower
;
490 // XHCI MMIO Base address
492 EFI_PHYSICAL_ADDRESS XhciMmioBase
;
495 // XHCI OP RegisterBase address
497 EFI_PHYSICAL_ADDRESS XhciOpRegister
;
500 // XHCI Debug Register Base Address
502 EFI_PHYSICAL_ADDRESS DebugCapabilityBase
;
505 // XHCI Debug Capability offset
507 UINT64 DebugCapabilityOffset
;
510 // XHCI Debug Context Address
512 EFI_PHYSICAL_ADDRESS DebugCapabilityContext
;
517 TRANSFER_RING TransferRingOut
;
518 TRANSFER_RING TransferRingIn
;
523 EVENT_RING EventRing
;
536 // The available data length in the following data buffer.
540 // The data buffer address for data read and poll.
542 EFI_PHYSICAL_ADDRESS Data
;
543 } USB3_DEBUG_PORT_HANDLE
;
548 Read XHCI debug register.
550 @param Handle Debug port handle.
551 @param Offset The offset of the debug register.
553 @return The register content read
558 IN USB3_DEBUG_PORT_HANDLE
*Handle
,
563 Set one bit of the debug register while keeping other bits.
565 @param Handle Debug port handle.
566 @param Offset The offset of the debug register.
567 @param Bit The bit mask of the register to set.
572 IN USB3_DEBUG_PORT_HANDLE
*Handle
,
578 Write the data to the debug register.
580 @param Handle Debug port handle.
581 @param Offset The offset of the debug register.
582 @param Data The data to write.
587 IN USB3_DEBUG_PORT_HANDLE
*Handle
,
593 Verifies if the bit positions specified by a mask are set in a register.
595 @param[in, out] Register UNITN register
596 @param[in] BitMask 32-bit mask
598 @return BOOLEAN - TRUE if all bits specified by the mask are enabled.
599 - FALSE even if one of the bits specified by the mask
609 Sets bits as per the enabled bit positions in the mask.
611 @param[in, out] Register UINTN register
612 @param[in] BitMask 32-bit mask
621 Clears bits as per the enabled bit positions in the mask.
623 @param[in, out] Register UINTN register
624 @param[in] BitMask 32-bit mask
628 IN OUT UINTN Register
,
633 Initialize USB3 debug port.
635 This method invokes various internal functions to facilitate
636 detection and initialization of USB3 debug port.
638 @retval RETURN_SUCCESS The serial device was initialized.
647 Return command register value in XHCI controller.
656 Allocate aligned memory for XHC's usage.
658 @param BufferSize The size, in bytes, of the Buffer.
660 @return A pointer to the allocated buffer or NULL if allocation fails.
664 AllocateAlignBuffer (
669 The real function to initialize USB3 debug port.
671 This method invokes various internal functions to facilitate
672 detection and initialization of USB3 debug port.
674 @retval RETURN_SUCCESS The serial device was initialized.
683 Submits bulk transfer to a bulk endpoint of a USB device.
685 @param Handle The instance of debug device.
686 @param Direction The direction of data transfer.
687 @param Data Array of pointers to the buffers of data to transmit
688 from or receive into.
689 @param DataLength The lenght of the data buffer.
690 @param Timeout Indicates the maximum time, in millisecond, which
691 the transfer is allowed to complete.
693 @retval EFI_SUCCESS The transfer was completed successfully.
694 @retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resource.
695 @retval EFI_INVALID_PARAMETER Some parameters are invalid.
696 @retval EFI_TIMEOUT The transfer failed due to timeout.
697 @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.
703 IN USB3_DEBUG_PORT_HANDLE
*Handle
,
704 IN EFI_USB_DATA_DIRECTION Direction
,
706 IN OUT UINTN
*DataLength
,
711 Initialize usb debug port hardware.
713 @param Handle Debug port handle.
715 @retval TRUE The usb debug port hardware configuration is changed.
716 @retval FALSE The usb debug port hardware configuration is not changed.
721 InitializeUsbDebugHardware (
722 IN USB3_DEBUG_PORT_HANDLE
*Handle
726 Return USB3 debug instance address pointer.
729 EFI_PHYSICAL_ADDRESS
*
730 GetUsb3DebugPortInstanceAddrPtr (
735 Return USB3 debug instance address.
738 USB3_DEBUG_PORT_HANDLE
*
739 GetUsb3DebugPortInstance (
743 #endif //__SERIAL_PORT_LIB_USB__