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[mirror_edk2.git] / SourceLevelDebugPkg / Library / DebugCommunicationLibUsb3 / DebugCommunicationLibUsb3Internal.h
1 /** @file
2 Debug Port Library implementation based on usb3 debug port.
3
4 Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
6
7 **/
8
9 #ifndef __USB3_DEBUG_PORT_LIB_INTERNAL__
10 #define __USB3_DEBUG_PORT_LIB_INTERNAL__
11
12 #include <Uefi.h>
13 #include <Base.h>
14 #include <IndustryStandard/Usb.h>
15 #include <Library/IoLib.h>
16 #include <IndustryStandard/Pci.h>
17 #include <Library/PcdLib.h>
18 #include <Library/UefiLib.h>
19 #include <Library/UefiBootServicesTableLib.h>
20 #include <Library/MemoryAllocationLib.h>
21 #include <Library/DebugLib.h>
22 #include <Library/BaseMemoryLib.h>
23 #include <Library/BaseLib.h>
24 #include <Library/TimerLib.h>
25 #include <Library/DebugCommunicationLib.h>
26 #include <Library/PciLib.h>
27
28 //
29 // USB Debug GUID value
30 //
31 #define USB3_DBG_GUID \
32 { \
33 0xb2a56f4d, 0x9177, 0x4fc8, { 0xa6, 0x77, 0xdd, 0x96, 0x3e, 0xb4, 0xcb, 0x1b } \
34 }
35
36 //
37 // The state machine of usb debug port
38 //
39 #define USB3DBG_NO_DBG_CAB 0 // The XHCI host controller does not support debug capability
40 #define USB3DBG_DBG_CAB 1 // The XHCI host controller supports debug capability
41 #define USB3DBG_ENABLED 2 // The XHCI debug device is enabled
42 #define USB3DBG_NOT_ENABLED 4 // The XHCI debug device is not enabled
43 #define USB3DBG_UNINITIALIZED 255 // The XHCI debug device is uninitialized
44
45 #define USB3_DEBUG_PORT_WRITE_MAX_PACKET_SIZE 0x08
46
47 //
48 // MaxPacketSize for DbC Endpoint Descriptor IN and OUT
49 //
50 #define XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE 0x400
51
52 #define XHCI_DEBUG_DEVICE_VENDOR_ID 0x0525
53 #define XHCI_DEBUG_DEVICE_PRODUCT_ID 0x127A
54 #define XHCI_DEBUG_DEVICE_PROTOCOL 0xFF
55 #define XHCI_DEBUG_DEVICE_REVISION 0x00
56
57 #define XHCI_BASE_ADDRESS_64_BIT_MASK 0xFFFFFFFFFFFF0000ULL
58 #define XHCI_BASE_ADDRESS_32_BIT_MASK 0xFFFF0000
59
60 #define PCI_CAPABILITY_ID_DEBUG_PORT 0x0A
61 #define XHC_HCCPARAMS_OFFSET 0x10
62 #define XHC_CAPABILITY_ID_MASK 0xFF
63 #define XHC_NEXT_CAPABILITY_MASK 0xFF00
64
65 #define XHC_HCSPARAMS1_OFFSET 0x4 // Structural Parameters 1
66 #define XHC_USBCMD_OFFSET 0x0 // USB Command Register Offset
67 #define XHC_USBSTS_OFFSET 0x4 // USB Status Register Offset
68 #define XHC_PORTSC_OFFSET 0x400 // Port Status and Control Register Offset
69
70 #define XHC_USBCMD_RUN BIT0 // Run/Stop
71 #define XHC_USBCMD_RESET BIT1 // Host Controller Reset
72
73 #define XHC_USBSTS_HALT BIT0
74
75 //
76 // Indicate the timeout when data is transferred in microsecond. 0 means infinite timeout.
77 //
78 #define DATA_TRANSFER_WRITE_TIMEOUT 0
79 #define DATA_TRANSFER_READ_TIMEOUT 50000
80 #define DATA_TRANSFER_POLL_TIMEOUT 1000
81 #define XHC_DEBUG_PORT_1_MILLISECOND 1000
82 //
83 // XHCI port power off/on delay
84 //
85 #define XHC_DEBUG_PORT_ON_OFF_DELAY 100000
86
87 //
88 // USB debug device string descriptor (header size + unicode string length)
89 //
90 #define STRING0_DESC_LEN 4
91 #define MANU_DESC_LEN 12
92 #define PRODUCT_DESC_LEN 40
93 #define SERIAL_DESC_LEN 4
94
95 //
96 // Debug Capability Register Offset
97 //
98 #define XHC_DC_DCID 0x0
99 #define XHC_DC_DCDB 0x4
100 #define XHC_DC_DCERSTSZ 0x8
101 #define XHC_DC_DCERSTBA 0x10
102 #define XHC_DC_DCERDP 0x18
103 #define XHC_DC_DCCTRL 0x20
104 #define XHC_DC_DCST 0x24
105 #define XHC_DC_DCPORTSC 0x28
106 #define XHC_DC_DCCP 0x30
107 #define XHC_DC_DCDDI1 0x38
108 #define XHC_DC_DCDDI2 0x3C
109
110 #define TRB_TYPE_LINK 6
111
112 #define ERST_NUMBER 0x01
113 #define TR_RING_TRB_NUMBER 0x100
114 #define EVENT_RING_TRB_NUMBER 0x200
115
116 #define ED_BULK_OUT 2
117 #define ED_BULK_IN 6
118
119 #define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))
120 #define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINT64)(UINTN)(Addr64), 32) & 0xFFFFFFFF))
121 #define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
122
123 //
124 // Endpoint Type (EP Type).
125 //
126 #define ED_NOT_VALID 0
127 #define ED_ISOCH_OUT 1
128 #define ED_BULK_OUT 2
129 #define ED_INTERRUPT_OUT 3
130 #define ED_CONTROL_BIDIR 4
131 #define ED_ISOCH_IN 5
132 #define ED_BULK_IN 6
133 #define ED_INTERRUPT_IN 7
134
135 //
136 // 6.4.5 TRB Completion Codes
137 //
138 #define TRB_COMPLETION_INVALID 0
139 #define TRB_COMPLETION_SUCCESS 1
140 #define TRB_COMPLETION_DATA_BUFFER_ERROR 2
141 #define TRB_COMPLETION_BABBLE_ERROR 3
142 #define TRB_COMPLETION_USB_TRANSACTION_ERROR 4
143 #define TRB_COMPLETION_TRB_ERROR 5
144 #define TRB_COMPLETION_STALL_ERROR 6
145 #define TRB_COMPLETION_SHORT_PACKET 13
146
147 //
148 // 6.4.6 TRB Types
149 //
150 #define TRB_TYPE_NORMAL 1
151 #define TRB_TYPE_SETUP_STAGE 2
152 #define TRB_TYPE_DATA_STAGE 3
153 #define TRB_TYPE_STATUS_STAGE 4
154 #define TRB_TYPE_ISOCH 5
155 #define TRB_TYPE_LINK 6
156 #define TRB_TYPE_EVENT_DATA 7
157 #define TRB_TYPE_NO_OP 8
158 #define TRB_TYPE_EN_SLOT 9
159 #define TRB_TYPE_DIS_SLOT 10
160 #define TRB_TYPE_ADDRESS_DEV 11
161 #define TRB_TYPE_CON_ENDPOINT 12
162 #define TRB_TYPE_EVALU_CONTXT 13
163 #define TRB_TYPE_RESET_ENDPOINT 14
164 #define TRB_TYPE_STOP_ENDPOINT 15
165 #define TRB_TYPE_SET_TR_DEQUE 16
166 #define TRB_TYPE_RESET_DEV 17
167 #define TRB_TYPE_GET_PORT_BANW 21
168 #define TRB_TYPE_FORCE_HEADER 22
169 #define TRB_TYPE_NO_OP_COMMAND 23
170 #define TRB_TYPE_TRANS_EVENT 32
171 #define TRB_TYPE_COMMAND_COMPLT_EVENT 33
172 #define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34
173 #define TRB_TYPE_HOST_CONTROLLER_EVENT 37
174 #define TRB_TYPE_DEVICE_NOTIFI_EVENT 38
175 #define TRB_TYPE_MFINDEX_WRAP_EVENT 39
176
177 //
178 // Convert millisecond to microsecond.
179 //
180 #define XHC_1_MILLISECOND (1000)
181 #define XHC_POLL_DELAY (1000)
182 #define XHC_GENERIC_TIMEOUT (10 * 1000)
183
184 #define EFI_USB_SPEED_FULL 0x0000 ///< 12 Mb/s, USB 1.1 OHCI and UHCI HC.
185 #define EFI_USB_SPEED_LOW 0x0001 ///< 1 Mb/s, USB 1.1 OHCI and UHCI HC.
186 #define EFI_USB_SPEED_HIGH 0x0002 ///< 480 Mb/s, USB 2.0 EHCI HC.
187 #define EFI_USB_SPEED_SUPER 0x0003 ///< 4.8 Gb/s, USB 3.0 XHCI HC.
188
189 //
190 // Transfer types, used in URB to identify the transfer type
191 //
192 #define XHC_CTRL_TRANSFER 0x01
193 #define XHC_BULK_TRANSFER 0x02
194 #define XHC_INT_TRANSFER_SYNC 0x04
195 #define XHC_INT_TRANSFER_ASYNC 0x08
196 #define XHC_INT_ONLY_TRANSFER_ASYNC 0x10
197
198 //
199 // USB Transfer Results
200 //
201 #define EFI_USB_NOERROR 0x00
202 #define EFI_USB_ERR_NOTEXECUTE 0x01
203 #define EFI_USB_ERR_STALL 0x02
204 #define EFI_USB_ERR_BUFFER 0x04
205 #define EFI_USB_ERR_BABBLE 0x08
206 #define EFI_USB_ERR_NAK 0x10
207 #define EFI_USB_ERR_CRC 0x20
208 #define EFI_USB_ERR_TIMEOUT 0x40
209 #define EFI_USB_ERR_BITSTUFF 0x80
210 #define EFI_USB_ERR_SYSTEM 0x100
211
212 #pragma pack(1)
213
214 //
215 // 7.6.9 OUT/IN EP Context: 64 bytes
216 // 7.6.9.2 When used by the DbC it is always a 64 byte data structure
217 //
218 typedef struct _ENDPOINT_CONTEXT_64 {
219 UINT32 EPState:3;
220 UINT32 RsvdZ1:5;
221 UINT32 Mult:2; // set to 0
222 UINT32 MaxPStreams:5; // set to 0
223 UINT32 LSA:1; // set to 0
224 UINT32 Interval:8; // set to 0
225 UINT32 RsvdZ2:8;
226
227 UINT32 RsvdZ3:1;
228 UINT32 CErr:2;
229 UINT32 EPType:3;
230 UINT32 RsvdZ4:1;
231 UINT32 HID:1; // set to 0
232 UINT32 MaxBurstSize:8;
233 UINT32 MaxPacketSize:16;
234
235 UINT32 PtrLo;
236
237 UINT32 PtrHi;
238
239 UINT32 AverageTRBLength:16;
240 UINT32 MaxESITPayload:16; // set to 0
241
242 UINT32 RsvdZ5; // Reserved
243 UINT32 RsvdZ6;
244 UINT32 RsvdZ7;
245
246 UINT32 RsvdZ8;
247 UINT32 RsvdZ9;
248 UINT32 RsvdZ10;
249 UINT32 RsvdZ11;
250
251 UINT32 RsvdZ12;
252 UINT32 RsvdZ13;
253 UINT32 RsvdZ14;
254 UINT32 RsvdZ15;
255 } ENDPOINT_CONTEXT_64;
256
257 //
258 // 6.4.1.1 Normal TRB: 16 bytes
259 // A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and
260 // Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer
261 // Rings, and to define the Data stage information for Control Transfer Rings.
262 //
263 typedef struct _TRANSFER_TRB_NORMAL {
264 UINT32 TRBPtrLo;
265
266 UINT32 TRBPtrHi;
267
268 UINT32 Length:17;
269 UINT32 TDSize:5;
270 UINT32 IntTarget:10;
271
272 UINT32 CycleBit:1;
273 UINT32 ENT:1;
274 UINT32 ISP:1;
275 UINT32 NS:1;
276 UINT32 CH:1;
277 UINT32 IOC:1;
278 UINT32 IDT:1;
279 UINT32 RsvdZ1:2;
280 UINT32 BEI:1;
281 UINT32 Type:6;
282 UINT32 RsvdZ2:16;
283 } TRANSFER_TRB_NORMAL;
284
285 //
286 // 6.4.2.1 Transfer Event TRB: 16 bytes
287 // A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1
288 // for more information on the use and operation of Transfer Events.
289 //
290 typedef struct _EVT_TRB_TRANSFER {
291 UINT32 TRBPtrLo;
292
293 UINT32 TRBPtrHi;
294
295 UINT32 Length:24;
296 UINT32 Completecode:8;
297
298 UINT32 CycleBit:1;
299 UINT32 RsvdZ1:1;
300 UINT32 ED:1;
301 UINT32 RsvdZ2:7;
302 UINT32 Type:6;
303 UINT32 EndpointId:5;
304 UINT32 RsvdZ3:3;
305 UINT32 SlotId:8;
306 } EVT_TRB_TRANSFER;
307
308 //
309 // 6.4.4.1 Link TRB: 16 bytes
310 // A Link TRB provides support for non-contiguous TRB Rings.
311 //
312 typedef struct _LINK_TRB {
313 UINT32 PtrLo;
314
315 UINT32 PtrHi;
316
317 UINT32 RsvdZ1:22;
318 UINT32 InterTarget:10;
319
320 UINT32 CycleBit:1;
321 UINT32 TC:1;
322 UINT32 RsvdZ2:2;
323 UINT32 CH:1;
324 UINT32 IOC:1;
325 UINT32 RsvdZ3:4;
326 UINT32 Type:6;
327 UINT32 RsvdZ4:16;
328 } LINK_TRB;
329
330 //
331 // TRB Template: 16 bytes
332 //
333 typedef struct _TRB_TEMPLATE {
334 UINT32 Parameter1;
335
336 UINT32 Parameter2;
337
338 UINT32 Status;
339
340 UINT32 CycleBit:1;
341 UINT32 RsvdZ1:9;
342 UINT32 Type:6;
343 UINT32 Control:16;
344 } TRB_TEMPLATE;
345
346 //
347 // Refer to XHCI 6.5 Event Ring Segment Table: 16 bytes
348 //
349 typedef struct _EVENT_RING_SEG_TABLE_ENTRY {
350 UINT32 PtrLo;
351 UINT32 PtrHi;
352 UINT32 RingTrbSize:16;
353 UINT32 RsvdZ1:16;
354 UINT32 RsvdZ2;
355 } EVENT_RING_SEG_TABLE_ENTRY;
356
357 //
358 // Size: 40 bytes
359 //
360 typedef struct _EVENT_RING {
361 EFI_PHYSICAL_ADDRESS ERSTBase;
362 EFI_PHYSICAL_ADDRESS EventRingSeg0;
363 UINT32 TrbNumber;
364 EFI_PHYSICAL_ADDRESS EventRingEnqueue;
365 EFI_PHYSICAL_ADDRESS EventRingDequeue;
366 UINT32 EventRingCCS;
367 } EVENT_RING;
368
369 // Size: 32 bytes
370 typedef struct _TRANSFER_RING {
371 EFI_PHYSICAL_ADDRESS RingSeg0;
372 UINT32 TrbNumber;
373 EFI_PHYSICAL_ADDRESS RingEnqueue;
374 EFI_PHYSICAL_ADDRESS RingDequeue;
375 UINT32 RingPCS;
376 } TRANSFER_RING;
377
378 //
379 // Size: 64 bytes
380 //
381 typedef struct _DBC_INFO_CONTEXT {
382 UINT64 String0DescAddress;
383 UINT64 ManufacturerStrDescAddress;
384 UINT64 ProductStrDescAddress;
385 UINT64 SerialNumberStrDescAddress;
386 UINT64 String0Length:8;
387 UINT64 ManufacturerStrLength:8;
388 UINT64 ProductStrLength:8;
389 UINT64 SerialNumberStrLength:8;
390 UINT64 RsvdZ1:32;
391 UINT64 RsvdZ2;
392 UINT64 RsvdZ3;
393 UINT64 RsvdZ4;
394 } DBC_INFO_CONTEXT;
395
396 //
397 // Debug Capability Context Data Structure: 192 bytes
398 //
399 typedef struct _XHC_DC_CONTEXT {
400 DBC_INFO_CONTEXT DbcInfoContext;
401 ENDPOINT_CONTEXT_64 EpOutContext;
402 ENDPOINT_CONTEXT_64 EpInContext;
403 } XHC_DC_CONTEXT;
404
405 //
406 // Size: 16 bytes
407 //
408 typedef union _TRB {
409 TRB_TEMPLATE TrbTemplate;
410 TRANSFER_TRB_NORMAL TrbNormal;
411 } TRB;
412
413 ///
414 /// USB data transfer direction
415 ///
416 typedef enum {
417 EfiUsbDataIn,
418 EfiUsbDataOut,
419 EfiUsbNoData
420 } EFI_USB_DATA_DIRECTION;
421
422 //
423 // URB (Usb Request Block) contains information for all kinds of
424 // usb requests.
425 //
426 typedef struct _URB {
427 //
428 // Transfer data buffer
429 //
430 EFI_PHYSICAL_ADDRESS Data;
431 UINT32 DataLen;
432
433 //
434 // Execute result
435 //
436 UINT32 Result;
437 //
438 // Completed data length
439 //
440 UINT32 Completed;
441 //
442 // Tranfer Ring info
443 //
444 EFI_PHYSICAL_ADDRESS Ring;
445 EFI_PHYSICAL_ADDRESS Trb;
446 BOOLEAN Finished;
447 EFI_USB_DATA_DIRECTION Direction;
448 } URB;
449
450 typedef struct _USB3_DEBUG_PORT_INSTANCE {
451 UINT8 Initialized;
452
453 //
454 // The flag indicates debug capability is supported
455 //
456 BOOLEAN DebugSupport;
457
458 //
459 // The flag indicates debug device is ready
460 //
461 BOOLEAN Ready;
462
463 //
464 // The flag indicates the instance is from HOB
465 //
466 BOOLEAN FromHob;
467
468 //
469 // Prevent notification being interrupted by debug timer
470 //
471 BOOLEAN InNotify;
472
473 //
474 // PciIo protocol event
475 //
476 EFI_PHYSICAL_ADDRESS PciIoEvent;
477
478 //
479 // The flag indicates if USB 3.0 ports has been turn off/on power
480 //
481 BOOLEAN ChangePortPower;
482
483 //
484 // XHCI MMIO Base address
485 //
486 EFI_PHYSICAL_ADDRESS XhciMmioBase;
487
488 //
489 // XHCI OP RegisterBase address
490 //
491 EFI_PHYSICAL_ADDRESS XhciOpRegister;
492
493 //
494 // XHCI Debug Register Base Address
495 //
496 EFI_PHYSICAL_ADDRESS DebugCapabilityBase;
497
498 //
499 // XHCI Debug Capability offset
500 //
501 UINT64 DebugCapabilityOffset;
502
503 //
504 // XHCI Debug Context Address
505 //
506 EFI_PHYSICAL_ADDRESS DebugCapabilityContext;
507
508 //
509 // Transfer Ring
510 //
511 TRANSFER_RING TransferRingOut;
512 TRANSFER_RING TransferRingIn;
513
514 //
515 // EventRing
516 //
517 EVENT_RING EventRing;
518
519 //
520 // URB - Read
521 //
522 URB UrbOut;
523
524 //
525 // URB - Write
526 //
527 URB UrbIn;
528
529 //
530 // The available data length in the following data buffer.
531 //
532 UINT8 DataCount;
533 //
534 // The data buffer address for data read and poll.
535 //
536 EFI_PHYSICAL_ADDRESS Data;
537 } USB3_DEBUG_PORT_HANDLE;
538
539 #pragma pack()
540
541 /**
542 Read XHCI debug register.
543
544 @param Handle Debug port handle.
545 @param Offset The offset of the debug register.
546
547 @return The register content read
548
549 **/
550 UINT32
551 XhcReadDebugReg (
552 IN USB3_DEBUG_PORT_HANDLE *Handle,
553 IN UINT32 Offset
554 );
555
556 /**
557 Set one bit of the debug register while keeping other bits.
558
559 @param Handle Debug port handle.
560 @param Offset The offset of the debug register.
561 @param Bit The bit mask of the register to set.
562
563 **/
564 VOID
565 XhcSetDebugRegBit (
566 IN USB3_DEBUG_PORT_HANDLE *Handle,
567 IN UINT32 Offset,
568 IN UINT32 Bit
569 );
570
571 /**
572 Write the data to the debug register.
573
574 @param Handle Debug port handle.
575 @param Offset The offset of the debug register.
576 @param Data The data to write.
577
578 **/
579 VOID
580 XhcWriteDebugReg (
581 IN USB3_DEBUG_PORT_HANDLE *Handle,
582 IN UINT32 Offset,
583 IN UINT32 Data
584 );
585
586 /**
587 Verifies if the bit positions specified by a mask are set in a register.
588
589 @param[in, out] Register UNITN register
590 @param[in] BitMask 32-bit mask
591
592 @return BOOLEAN - TRUE if all bits specified by the mask are enabled.
593 - FALSE even if one of the bits specified by the mask
594 is not enabled.
595 **/
596 BOOLEAN
597 XhcIsBitSet(
598 UINTN Register,
599 UINT32 BitMask
600 );
601
602 /**
603 Sets bits as per the enabled bit positions in the mask.
604
605 @param[in, out] Register UINTN register
606 @param[in] BitMask 32-bit mask
607 **/
608 VOID
609 XhcSetR32Bit(
610 UINTN Register,
611 UINT32 BitMask
612 );
613
614 /**
615 Clears bits as per the enabled bit positions in the mask.
616
617 @param[in, out] Register UINTN register
618 @param[in] BitMask 32-bit mask
619 **/
620 VOID
621 XhcClearR32Bit(
622 IN OUT UINTN Register,
623 IN UINT32 BitMask
624 );
625
626 /**
627 Initialize USB3 debug port.
628
629 This method invokes various internal functions to facilitate
630 detection and initialization of USB3 debug port.
631
632 @retval RETURN_SUCCESS The serial device was initialized.
633 **/
634 RETURN_STATUS
635 EFIAPI
636 USB3Initialize (
637 VOID
638 );
639
640 /**
641 Return command register value in XHCI controller.
642
643 **/
644 UINT16
645 GetXhciPciCommand (
646 VOID
647 );
648
649 /**
650 Allocate aligned memory for XHC's usage.
651
652 @param BufferSize The size, in bytes, of the Buffer.
653
654 @return A pointer to the allocated buffer or NULL if allocation fails.
655
656 **/
657 VOID*
658 AllocateAlignBuffer (
659 IN UINTN BufferSize
660 );
661
662 /**
663 The real function to initialize USB3 debug port.
664
665 This method invokes various internal functions to facilitate
666 detection and initialization of USB3 debug port.
667
668 @retval RETURN_SUCCESS The serial device was initialized.
669 **/
670 RETURN_STATUS
671 EFIAPI
672 USB3InitializeReal (
673 VOID
674 );
675
676 /**
677 Submits bulk transfer to a bulk endpoint of a USB device.
678
679 @param Handle The instance of debug device.
680 @param Direction The direction of data transfer.
681 @param Data Array of pointers to the buffers of data to transmit
682 from or receive into.
683 @param DataLength The length of the data buffer.
684 @param Timeout Indicates the maximum time, in millisecond, which
685 the transfer is allowed to complete.
686
687 @retval EFI_SUCCESS The transfer was completed successfully.
688 @retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resource.
689 @retval EFI_INVALID_PARAMETER Some parameters are invalid.
690 @retval EFI_TIMEOUT The transfer failed due to timeout.
691 @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.
692
693 **/
694 EFI_STATUS
695 EFIAPI
696 XhcDataTransfer (
697 IN USB3_DEBUG_PORT_HANDLE *Handle,
698 IN EFI_USB_DATA_DIRECTION Direction,
699 IN OUT VOID *Data,
700 IN OUT UINTN *DataLength,
701 IN UINTN Timeout
702 );
703
704 /**
705 Initialize usb debug port hardware.
706
707 @param Handle Debug port handle.
708
709 @retval TRUE The usb debug port hardware configuration is changed.
710 @retval FALSE The usb debug port hardware configuration is not changed.
711
712 **/
713 RETURN_STATUS
714 EFIAPI
715 InitializeUsbDebugHardware (
716 IN USB3_DEBUG_PORT_HANDLE *Handle
717 );
718
719 /**
720 Return USB3 debug instance address pointer.
721
722 **/
723 EFI_PHYSICAL_ADDRESS *
724 GetUsb3DebugPortInstanceAddrPtr (
725 VOID
726 );
727
728 /**
729 Return USB3 debug instance address.
730
731 **/
732 USB3_DEBUG_PORT_HANDLE *
733 GetUsb3DebugPortInstance (
734 VOID
735 );
736
737 #endif //__SERIAL_PORT_LIB_USB__
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