SourceLevelDebugPkg DebugUsb3: Fix GCC build failures
[mirror_edk2.git] / SourceLevelDebugPkg / Library / DebugCommunicationLibUsb3 / DebugCommunicationLibUsb3Transfer.c
1 /** @file
2 Debug Port Library implementation based on usb3 debug port.
3
4 Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php.
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14 #include "DebugCommunicationLibUsb3Internal.h"
15
16 /**
17 Synchronize the specified transfer ring to update the enqueue and dequeue pointer.
18
19 @param Handle Debug port handle.
20 @param TrsRing The transfer ring to sync.
21
22 @retval EFI_SUCCESS The transfer ring is synchronized successfully.
23
24 **/
25 EFI_STATUS
26 EFIAPI
27 XhcSyncTrsRing (
28 IN USB3_DEBUG_PORT_HANDLE *Handle,
29 IN TRANSFER_RING *TrsRing
30 )
31 {
32 UINTN Index;
33 TRB_TEMPLATE *TrsTrb;
34 UINT32 CycleBit;
35
36 ASSERT (TrsRing != NULL);
37
38 //
39 // Calculate the latest RingEnqueue and RingPCS
40 //
41 TrsTrb = (TRB_TEMPLATE *)(UINTN) TrsRing->RingEnqueue;
42
43 ASSERT (TrsTrb != NULL);
44
45 for (Index = 0; Index < TrsRing->TrbNumber; Index++) {
46 if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) {
47 break;
48 }
49 TrsTrb++;
50 if ((UINT8) TrsTrb->Type == TRB_TYPE_LINK) {
51 ASSERT (((LINK_TRB*)TrsTrb)->TC != 0);
52 //
53 // set cycle bit in Link TRB as normal
54 //
55 ((LINK_TRB*)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;
56 //
57 // Toggle PCS maintained by software
58 //
59 TrsRing->RingPCS = (TrsRing->RingPCS & BIT0) ? 0 : 1;
60 TrsTrb = (TRB_TEMPLATE *)(UINTN)((TrsTrb->Parameter1 | LShiftU64 ((UINT64)TrsTrb->Parameter2, 32)) & ~0x0F);
61 }
62 }
63 ASSERT (Index != TrsRing->TrbNumber);
64
65 if ((EFI_PHYSICAL_ADDRESS)(UINTN) TrsTrb != TrsRing->RingEnqueue) {
66 TrsRing->RingEnqueue = (EFI_PHYSICAL_ADDRESS)(UINTN) TrsTrb;
67 }
68
69 //
70 // Clear the Trb context for enqueue, but reserve the PCS bit which indicates free Trb.
71 //
72 CycleBit = TrsTrb->CycleBit;
73 ZeroMem (TrsTrb, sizeof (TRB_TEMPLATE));
74 TrsTrb->CycleBit = CycleBit;
75
76 return EFI_SUCCESS;
77 }
78
79 /**
80 Synchronize the specified event ring to update the enqueue and dequeue pointer.
81
82 @param Handle Debug port handle.
83 @param EvtRing The event ring to sync.
84
85 @retval EFI_SUCCESS The event ring is synchronized successfully.
86
87 **/
88 EFI_STATUS
89 EFIAPI
90 XhcSyncEventRing (
91 IN USB3_DEBUG_PORT_HANDLE *Handle,
92 IN EVENT_RING *EvtRing
93 )
94 {
95 UINTN Index;
96 TRB_TEMPLATE *EvtTrb1;
97
98 ASSERT (EvtRing != NULL);
99
100 //
101 // Calculate the EventRingEnqueue and EventRingCCS.
102 // Note: only support single Segment
103 //
104 EvtTrb1 = (TRB_TEMPLATE *)(UINTN) EvtRing->EventRingDequeue;
105
106 for (Index = 0; Index < EvtRing->TrbNumber; Index++) {
107 if (EvtTrb1->CycleBit != EvtRing->EventRingCCS) {
108 break;
109 }
110
111 EvtTrb1++;
112
113 if ((UINTN)EvtTrb1 >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
114 EvtTrb1 = (TRB_TEMPLATE *)(UINTN) EvtRing->EventRingSeg0;
115 EvtRing->EventRingCCS = (EvtRing->EventRingCCS) ? 0 : 1;
116 }
117 }
118
119 if (Index < EvtRing->TrbNumber) {
120 EvtRing->EventRingEnqueue = (EFI_PHYSICAL_ADDRESS)(UINTN)EvtTrb1;
121 } else {
122 ASSERT (FALSE);
123 }
124
125 return EFI_SUCCESS;
126 }
127
128 /**
129 Check if there is a new generated event.
130
131 @param Handle Debug port handle.
132 @param EvtRing The event ring to check.
133 @param NewEvtTrb The new event TRB found.
134
135 @retval EFI_SUCCESS Found a new event TRB at the event ring.
136 @retval EFI_NOT_READY The event ring has no new event.
137
138 **/
139 EFI_STATUS
140 EFIAPI
141 XhcCheckNewEvent (
142 IN USB3_DEBUG_PORT_HANDLE *Handle,
143 IN EVENT_RING *EvtRing,
144 OUT TRB_TEMPLATE **NewEvtTrb
145 )
146 {
147 EFI_STATUS Status;
148
149 ASSERT (EvtRing != NULL);
150
151 *NewEvtTrb = (TRB_TEMPLATE *)(UINTN) EvtRing->EventRingDequeue;
152
153 if (EvtRing->EventRingDequeue == EvtRing->EventRingEnqueue) {
154 return EFI_NOT_READY;
155 }
156
157 Status = EFI_SUCCESS;
158
159 EvtRing->EventRingDequeue += sizeof (TRB_TEMPLATE);
160 //
161 // If the dequeue pointer is beyond the ring, then roll-back it to the begining of the ring.
162 //
163 if ((UINTN)EvtRing->EventRingDequeue >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
164 EvtRing->EventRingDequeue = EvtRing->EventRingSeg0;
165 }
166
167 return Status;
168 }
169
170 /**
171 Check if the Trb is a transaction of the URB.
172
173 @param Ring The transfer ring to be checked.
174 @param Trb The TRB to be checked.
175
176 @retval TRUE It is a transaction of the URB.
177 @retval FALSE It is not any transaction of the URB.
178
179 **/
180 BOOLEAN
181 IsTrbInTrsRing (
182 IN TRANSFER_RING *Ring,
183 IN TRB_TEMPLATE *Trb
184 )
185 {
186 TRB_TEMPLATE *CheckedTrb;
187 UINTN Index;
188
189 CheckedTrb = (TRB_TEMPLATE *)(UINTN) Ring->RingSeg0;
190
191 ASSERT (Ring->TrbNumber == TR_RING_TRB_NUMBER);
192
193 for (Index = 0; Index < Ring->TrbNumber; Index++) {
194 if (Trb == CheckedTrb) {
195 return TRUE;
196 }
197 CheckedTrb++;
198 }
199
200 return FALSE;
201 }
202
203 /**
204 Check the URB's execution result and update the URB's
205 result accordingly.
206
207 @param Handle Debug port handle.
208 @param Urb The URB to check result.
209
210 **/
211 VOID
212 XhcCheckUrbResult (
213 IN USB3_DEBUG_PORT_HANDLE *Handle,
214 IN URB *Urb
215 )
216 {
217 EVT_TRB_TRANSFER *EvtTrb;
218 TRB_TEMPLATE *TRBPtr;
219 UINTN Index;
220 EFI_STATUS Status;
221 URB *CheckedUrb;
222 UINT64 XhcDequeue;
223 UINT32 High;
224 UINT32 Low;
225
226 ASSERT ((Handle != NULL) && (Urb != NULL));
227
228 if (Urb->Finished) {
229 goto EXIT;
230 }
231
232 EvtTrb = NULL;
233
234 //
235 // Traverse the event ring to find out all new events from the previous check.
236 //
237 XhcSyncEventRing (Handle, &Handle->EventRing);
238
239 for (Index = 0; Index < Handle->EventRing.TrbNumber; Index++) {
240
241 Status = XhcCheckNewEvent (Handle, &Handle->EventRing, ((TRB_TEMPLATE **)&EvtTrb));
242 if (Status == EFI_NOT_READY) {
243 //
244 // All new events are handled, return directly.
245 //
246 goto EXIT;
247 }
248
249 if ((EvtTrb->Type != TRB_TYPE_COMMAND_COMPLT_EVENT) && (EvtTrb->Type != TRB_TYPE_TRANS_EVENT)) {
250 continue;
251 }
252
253 TRBPtr = (TRB_TEMPLATE *)(UINTN)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64) EvtTrb->TRBPtrHi, 32));
254
255 if (IsTrbInTrsRing ((TRANSFER_RING *)(UINTN)(Urb->Ring), TRBPtr)) {
256 CheckedUrb = Urb;
257 } else if (IsTrbInTrsRing ((TRANSFER_RING *)(UINTN)(Handle->UrbIn.Ring), TRBPtr)) {
258 //
259 // If it is read event and it should be generated by poll, and current operation is write, we need save data into internal buffer.
260 // Internal buffer is used by next read.
261 //
262 Handle->DataCount = (UINT8) (Handle->UrbIn.DataLen - EvtTrb->Length);
263 CopyMem ((VOID *)(UINTN)Handle->Data, (VOID *)(UINTN)Handle->UrbIn.Data, Handle->DataCount);
264 //
265 // Fill this TRB complete with CycleBit, otherwise next read will fail with old TRB.
266 //
267 TRBPtr->CycleBit = (TRBPtr->CycleBit & BIT0) ? 0 : 1;
268 continue;
269 } else {
270 continue;
271 }
272
273 if ((EvtTrb->Completecode == TRB_COMPLETION_SHORT_PACKET) ||
274 (EvtTrb->Completecode == TRB_COMPLETION_SUCCESS)) {
275 //
276 // The length of data which were transferred.
277 //
278 CheckedUrb->Completed += (((TRANSFER_TRB_NORMAL*)TRBPtr)->Length - EvtTrb->Length);
279 } else {
280 CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;
281 }
282 //
283 // This Urb has been processed
284 //
285 CheckedUrb->Finished = TRUE;
286 }
287
288 EXIT:
289 //
290 // Advance event ring to last available entry
291 //
292 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
293 // So divide it to two 32-bytes width register access.
294 //
295 Low = XhcReadDebugReg (Handle, XHC_DC_DCERDP);
296 High = XhcReadDebugReg (Handle, XHC_DC_DCERDP + 4);
297 XhcDequeue = (UINT64)(LShiftU64((UINT64)High, 32) | Low);
298
299 if ((XhcDequeue & (~0x0F)) != ((UINT64)(UINTN)Handle->EventRing.EventRingDequeue & (~0x0F))) {
300 //
301 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
302 // So divide it to two 32-bytes width register access.
303 //
304 XhcWriteDebugReg (Handle, XHC_DC_DCERDP, XHC_LOW_32BIT (Handle->EventRing.EventRingDequeue));
305 XhcWriteDebugReg (Handle, XHC_DC_DCERDP + 4, XHC_HIGH_32BIT (Handle->EventRing.EventRingDequeue));
306 }
307 }
308
309 /**
310 Ring the door bell to notify XHCI there is a transaction to be executed.
311
312 @param Handle Debug port handle.
313 @param Urb The pointer to URB.
314
315 @retval EFI_SUCCESS Successfully ring the door bell.
316
317 **/
318 EFI_STATUS
319 EFIAPI
320 XhcRingDoorBell (
321 IN USB3_DEBUG_PORT_HANDLE *Handle,
322 IN URB *Urb
323 )
324 {
325 UINT32 Dcdb;
326
327 //
328 // 7.6.8.2 DCDB Register
329 //
330 Dcdb = (Urb->Direction == EfiUsbDataIn) ? 0x100 : 0x0;
331
332 XhcWriteDebugReg (
333 Handle,
334 XHC_DC_DCDB,
335 Dcdb
336 );
337
338 return EFI_SUCCESS;
339 }
340
341 /**
342 Execute the transfer by polling the URB. This is a synchronous operation.
343
344 @param Handle Debug port handle.
345 @param Urb The URB to execute.
346 @param Timeout The time to wait before abort, in microsecond.
347
348 **/
349 VOID
350 XhcExecTransfer (
351 IN USB3_DEBUG_PORT_HANDLE *Handle,
352 IN URB *Urb,
353 IN UINTN Timeout
354 )
355 {
356 TRANSFER_RING *Ring;
357 TRB_TEMPLATE *Trb;
358 UINTN Loop;
359 UINTN Index;
360
361 Loop = Timeout / XHC_DEBUG_PORT_1_MILLISECOND;
362 if (Timeout == 0) {
363 Loop = 0xFFFFFFFF;
364 }
365 XhcRingDoorBell (Handle, Urb);
366 //
367 // Event Ring Not Empty bit can only be set to 1 by XHC after ringing door bell with some delay.
368 //
369 for (Index = 0; Index < Loop; Index++) {
370 XhcCheckUrbResult (Handle, Urb);
371 if (Urb->Finished) {
372 break;
373 }
374 MicroSecondDelay (XHC_DEBUG_PORT_1_MILLISECOND);
375 }
376 if (Index == Loop) {
377 //
378 // If time out occurs.
379 //
380 Urb->Result |= EFI_USB_ERR_TIMEOUT;
381 }
382 //
383 // If URB transfer is error, restore transfer ring to original value before URB transfer
384 // This will make the current transfer TRB is always at the latest unused one in transfer ring.
385 //
386 Ring = (TRANSFER_RING *)(UINTN) Urb->Ring;
387 if ((Urb->Result != EFI_USB_NOERROR) && (Urb->Direction == EfiUsbDataIn)) {
388 //
389 // Adjust Enqueue pointer
390 //
391 Ring->RingEnqueue = Urb->Trb;
392 //
393 // Clear CCS flag for next use
394 //
395 Trb = (TRB_TEMPLATE *)(UINTN) Urb->Trb;
396 Trb->CycleBit = ((~Ring->RingPCS) & BIT0);
397 } else {
398 //
399 // Update transfer ring for next transfer.
400 //
401 XhcSyncTrsRing (Handle, Ring);
402 }
403 }
404
405 /**
406 Create a transfer TRB.
407
408 @param Handle Debug port handle.
409 @param Urb The urb used to construct the transfer TRB.
410
411 @return Created TRB or NULL
412
413 **/
414 EFI_STATUS
415 XhcCreateTransferTrb (
416 IN USB3_DEBUG_PORT_HANDLE *Handle,
417 IN URB *Urb
418 )
419 {
420 TRANSFER_RING *EPRing;
421 TRB *Trb;
422
423 if (Urb->Direction == EfiUsbDataIn) {
424 EPRing = &Handle->TransferRingIn;
425 } else {
426 EPRing = &Handle->TransferRingOut;
427 }
428
429 Urb->Ring = (EFI_PHYSICAL_ADDRESS)(UINTN) EPRing;
430 XhcSyncTrsRing (Handle, EPRing);
431
432 Urb->Trb = EPRing->RingEnqueue;
433 Trb = (TRB *)(UINTN)EPRing->RingEnqueue;
434 Trb->TrbNormal.TRBPtrLo = XHC_LOW_32BIT (Urb->Data);
435 Trb->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT (Urb->Data);
436 Trb->TrbNormal.Length = Urb->DataLen;
437 Trb->TrbNormal.TDSize = 0;
438 Trb->TrbNormal.IntTarget = 0;
439 Trb->TrbNormal.ISP = 1;
440 Trb->TrbNormal.IOC = 1;
441 Trb->TrbNormal.Type = TRB_TYPE_NORMAL;
442
443 //
444 // Update the cycle bit to indicate this TRB has been consumed.
445 //
446 Trb->TrbNormal.CycleBit = EPRing->RingPCS & BIT0;
447
448 return EFI_SUCCESS;
449 }
450
451 /**
452 Create a new URB for a new transaction.
453
454 @param Handle Debug port handle.
455 @param Direction The direction of data flow.
456 @param Data The user data to transfer
457 @param DataLen The length of data buffer
458
459 @return Created URB or NULL
460
461 **/
462 URB*
463 XhcCreateUrb (
464 IN USB3_DEBUG_PORT_HANDLE *Handle,
465 IN EFI_USB_DATA_DIRECTION Direction,
466 IN VOID *Data,
467 IN UINTN DataLen
468 )
469 {
470 EFI_STATUS Status;
471 URB *Urb;
472 EFI_PHYSICAL_ADDRESS UrbData;
473
474 if (Direction == EfiUsbDataIn) {
475 Urb = &Handle->UrbIn;
476 } else {
477 Urb = &Handle->UrbOut;
478 }
479
480 UrbData = Urb->Data;
481
482 ZeroMem (Urb, sizeof (URB));
483 Urb->Direction = Direction;
484
485 //
486 // Allocate memory to move data from CAR or SMRAM to normal memory
487 // to make XHCI DMA successfully
488 // re-use the pre-allocate buffer in PEI to avoid DXE memory service or gBS are not ready
489 //
490 Urb->Data = UrbData;
491
492 if (Direction == EfiUsbDataIn) {
493 //
494 // Do not break URB data in buffer as it may contain the data which were just put in via DMA by XHC
495 //
496 Urb->DataLen = (UINT32) DataLen;
497 } else {
498 //
499 // Put data into URB data out buffer which will create TRBs
500 //
501 ZeroMem ((VOID*)(UINTN) Urb->Data, DataLen);
502 CopyMem ((VOID*)(UINTN) Urb->Data, Data, DataLen);
503 Urb->DataLen = (UINT32) DataLen;
504 }
505
506 Status = XhcCreateTransferTrb (Handle, Urb);
507 ASSERT_EFI_ERROR (Status);
508
509 return Urb;
510 }
511
512 /**
513 Submits bulk transfer to a bulk endpoint of a USB device.
514
515 @param Handle Debug port handle.
516 @param Direction The direction of data transfer.
517 @param Data Array of pointers to the buffers of data to transmit
518 from or receive into.
519 @param DataLength The lenght of the data buffer.
520 @param Timeout Indicates the maximum time, in microsecond, which
521 the transfer is allowed to complete.
522
523 @retval EFI_SUCCESS The transfer was completed successfully.
524 @retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resource.
525 @retval EFI_INVALID_PARAMETER Some parameters are invalid.
526 @retval EFI_TIMEOUT The transfer failed due to timeout.
527 @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.
528
529 **/
530 EFI_STATUS
531 EFIAPI
532 XhcDataTransfer (
533 IN USB3_DEBUG_PORT_HANDLE *Handle,
534 IN EFI_USB_DATA_DIRECTION Direction,
535 IN OUT VOID *Data,
536 IN OUT UINTN *DataLength,
537 IN UINTN Timeout
538 )
539 {
540 URB *Urb;
541 EFI_STATUS Status;
542
543 //
544 // Validate the parameters
545 //
546 if ((DataLength == NULL) || (*DataLength == 0) || (Data == NULL)) {
547 return EFI_INVALID_PARAMETER;
548 }
549
550 //
551 // Create a new URB, insert it into the asynchronous
552 // schedule list, then poll the execution status.
553 //
554 Urb = XhcCreateUrb (Handle, Direction, Data, *DataLength);
555 ASSERT (Urb != NULL);
556
557 XhcExecTransfer (Handle, Urb, Timeout);
558
559 *DataLength = Urb->Completed;
560
561 Status = EFI_TIMEOUT;
562 if (Urb->Result == EFI_USB_NOERROR) {
563 Status = EFI_SUCCESS;
564 }
565
566 if (Direction == EfiUsbDataIn) {
567 //
568 // Move data from internal buffer to outside buffer (outside buffer may be in SMRAM...)
569 // SMRAM does not allow to do DMA, so we create an internal buffer.
570 //
571 CopyMem (Data, (VOID *)(UINTN)Urb->Data, *DataLength);
572 }
573
574 return Status;
575 }
576