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1 /** @file
2 UEFI Application to display CPUID leaf information.
3
4 Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
6
7 **/
8
9 #include <Uefi.h>
10 #include <Library/BaseLib.h>
11 #include <Library/UefiLib.h>
12 #include <Register/Intel/Cpuid.h>
13
14 ///
15 /// Macro used to display the value of a bit field in a register returned by CPUID.
16 ///
17 #define PRINT_BIT_FIELD(Variable, FieldName) \
18 Print (L"%5a%42a: %x\n", #Variable, #FieldName, Variable.Bits.FieldName);
19
20 ///
21 /// Macro used to display the value of a register returned by CPUID.
22 ///
23 #define PRINT_VALUE(Variable, Description) \
24 Print (L"%5a%42a: %x\n", #Variable, #Description, Variable);
25
26 ///
27 /// Structure for cache description lookup table
28 ///
29 typedef struct {
30 UINT8 CacheDescriptor;
31 CHAR8 *Type;
32 CHAR8 *Description;
33 } CPUID_CACHE_INFO_DESCRIPTION;
34
35 ///
36 /// Cache description lookup table
37 ///
38 CPUID_CACHE_INFO_DESCRIPTION mCpuidCacheInfoDescription[] = {
39 { 0x00, "General", "Null descriptor, this byte contains no information" },
40 { 0x01, "TLB", "Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries" },
41 { 0x02, "TLB", "Instruction TLB: 4 MByte pages, fully associative, 2 entries" },
42 { 0x03, "TLB", "Data TLB: 4 KByte pages, 4-way set associative, 64 entries" },
43 { 0x04, "TLB", "Data TLB: 4 MByte pages, 4-way set associative, 8 entries" },
44 { 0x05, "TLB", "Data TLB1: 4 MByte pages, 4-way set associative, 32 entries" },
45 { 0x06, "Cache", "1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size" },
46 { 0x08, "Cache", "1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size" },
47 { 0x09, "Cache", "1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size" },
48 { 0x0A, "Cache", "1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size" },
49 { 0x0B, "TLB", "Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries" },
50 { 0x0C, "Cache", "1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size" },
51 { 0x0D, "Cache", "1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size" },
52 { 0x0E, "Cache", "1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size" },
53 { 0x1D, "Cache", "2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size" },
54 { 0x21, "Cache", "2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size" },
55 { 0x22, "Cache", "3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector" },
56 { 0x23, "Cache", "3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },
57 { 0x24, "Cache", "2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size" },
58 { 0x25, "Cache", "3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },
59 { 0x29, "Cache", "3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },
60 { 0x2C, "Cache", "1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size" },
61 { 0x30, "Cache", "1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size" },
62 { 0x40, "Cache", "No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache" },
63 { 0x41, "Cache", "2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size" },
64 { 0x42, "Cache", "2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size" },
65 { 0x43, "Cache", "2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size" },
66 { 0x44, "Cache", "2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size" },
67 { 0x45, "Cache", "2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size" },
68 { 0x46, "Cache", "3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size" },
69 { 0x47, "Cache", "3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size" },
70 { 0x48, "Cache", "2nd-level cache: 3MByte, 12-way set associative, 64 byte line size" },
71 { 0x49, "Cache", "3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model 06H). 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size" },
72 { 0x4A, "Cache", "3rd-level cache: 6MByte, 12-way set associative, 64 byte line size" },
73 { 0x4B, "Cache", "3rd-level cache: 8MByte, 16-way set associative, 64 byte line size" },
74 { 0x4C, "Cache", "3rd-level cache: 12MByte, 12-way set associative, 64 byte line size" },
75 { 0x4D, "Cache", "3rd-level cache: 16MByte, 16-way set associative, 64 byte line size" },
76 { 0x4E, "Cache", "2nd-level cache: 6MByte, 24-way set associative, 64 byte line size" },
77 { 0x4F, "TLB", "Instruction TLB: 4 KByte pages, 32 entries" },
78 { 0x50, "TLB", "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries" },
79 { 0x51, "TLB", "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries" },
80 { 0x52, "TLB", "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries" },
81 { 0x55, "TLB", "Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries" },
82 { 0x56, "TLB", "Data TLB0: 4 MByte pages, 4-way set associative, 16 entries" },
83 { 0x57, "TLB", "Data TLB0: 4 KByte pages, 4-way associative, 16 entries" },
84 { 0x59, "TLB", "Data TLB0: 4 KByte pages, fully associative, 16 entries" },
85 { 0x5A, "TLB", "Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries" },
86 { 0x5B, "TLB", "Data TLB: 4 KByte and 4 MByte pages, 64 entries" },
87 { 0x5C, "TLB", "Data TLB: 4 KByte and 4 MByte pages,128 entries" },
88 { 0x5D, "TLB", "Data TLB: 4 KByte and 4 MByte pages,256 entries" },
89 { 0x60, "Cache", "1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size" },
90 { 0x61, "TLB", "Instruction TLB: 4 KByte pages, fully associative, 48 entries" },
91 { 0x63, "TLB", "Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries" },
92 { 0x64, "TLB", "Data TLB: 4 KByte pages, 4-way set associative, 512 entries" },
93 { 0x66, "Cache", "1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size" },
94 { 0x67, "Cache", "1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size" },
95 { 0x68, "Cache", "1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size" },
96 { 0x6A, "Cache", "uTLB: 4 KByte pages, 8-way set associative, 64 entries" },
97 { 0x6B, "Cache", "DTLB: 4 KByte pages, 8-way set associative, 256 entries" },
98 { 0x6C, "Cache", "DTLB: 2M/4M pages, 8-way set associative, 128 entries" },
99 { 0x6D, "Cache", "DTLB: 1 GByte pages, fully associative, 16 entries" },
100 { 0x70, "Cache", "Trace cache: 12 K-uop, 8-way set associative" },
101 { 0x71, "Cache", "Trace cache: 16 K-uop, 8-way set associative" },
102 { 0x72, "Cache", "Trace cache: 32 K-uop, 8-way set associative" },
103 { 0x76, "TLB", "Instruction TLB: 2M/4M pages, fully associative, 8 entries" },
104 { 0x78, "Cache", "2nd-level cache: 1 MByte, 4-way set associative, 64byte line size" },
105 { 0x79, "Cache", "2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },
106 { 0x7A, "Cache", "2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },
107 { 0x7B, "Cache", "2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },
108 { 0x7C, "Cache", "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector" },
109 { 0x7D, "Cache", "2nd-level cache: 2 MByte, 8-way set associative, 64byte line size" },
110 { 0x7F, "Cache", "2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size" },
111 { 0x80, "Cache", "2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size" },
112 { 0x82, "Cache", "2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size" },
113 { 0x83, "Cache", "2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size" },
114 { 0x84, "Cache", "2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size" },
115 { 0x85, "Cache", "2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size" },
116 { 0x86, "Cache", "2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size" },
117 { 0x87, "Cache", "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size" },
118 { 0xA0, "DTLB", "DTLB: 4k pages, fully associative, 32 entries" },
119 { 0xB0, "TLB", "Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries" },
120 { 0xB1, "TLB", "Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries" },
121 { 0xB2, "TLB", "Instruction TLB: 4KByte pages, 4-way set associative, 64 entries" },
122 { 0xB3, "TLB", "Data TLB: 4 KByte pages, 4-way set associative, 128 entries" },
123 { 0xB4, "TLB", "Data TLB1: 4 KByte pages, 4-way associative, 256 entries" },
124 { 0xB5, "TLB", "Instruction TLB: 4KByte pages, 8-way set associative, 64 entries" },
125 { 0xB6, "TLB", "Instruction TLB: 4KByte pages, 8-way set associative, 128 entries" },
126 { 0xBA, "TLB", "Data TLB1: 4 KByte pages, 4-way associative, 64 entries" },
127 { 0xC0, "TLB", "Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries" },
128 { 0xC1, "STLB", "Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries" },
129 { 0xC2, "DTLB", "DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries" },
130 { 0xC3, "STLB", "Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries." },
131 { 0xC4, "DTLB", "DTLB: 2M/4M Byte pages, 4-way associative, 32 entries" },
132 { 0xCA, "STLB", "Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries" },
133 { 0xD0, "Cache", "3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size" },
134 { 0xD1, "Cache", "3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size" },
135 { 0xD2, "Cache", "3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size" },
136 { 0xD6, "Cache", "3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size" },
137 { 0xD7, "Cache", "3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size" },
138 { 0xD8, "Cache", "3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size" },
139 { 0xDC, "Cache", "3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size" },
140 { 0xDD, "Cache", "3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size" },
141 { 0xDE, "Cache", "3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size" },
142 { 0xE2, "Cache", "3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size" },
143 { 0xE3, "Cache", "3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size" },
144 { 0xE4, "Cache", "3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size" },
145 { 0xEA, "Cache", "3rd-level cache: 12MByte, 24-way set associative, 64 byte line size" },
146 { 0xEB, "Cache", "3rd-level cache: 18MByte, 24-way set associative, 64 byte line size" },
147 { 0xEC, "Cache", "3rd-level cache: 24MByte, 24-way set associative, 64 byte line size" },
148 { 0xF0, "Prefetch", "64-Byte prefetching" },
149 { 0xF1, "Prefetch", "128-Byte prefetching" },
150 { 0xFE, "General", "CPUID leaf 2 does not report TLB descriptor information; use CPUID leaf 18H to query TLB and other address translation parameters." },
151 { 0xFF, "General", "CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters" }
152 };
153
154 ///
155 /// The maximum supported CPUID leaf index starting from leaf 0x00000000.
156 ///
157 UINT32 gMaximumBasicFunction = CPUID_SIGNATURE;
158
159 ///
160 /// The maximum supported CPUID leaf index starting from leaf 0x80000000.
161 ///
162 UINT32 gMaximumExtendedFunction = CPUID_EXTENDED_FUNCTION;
163
164 /**
165 Display CPUID_SIGNATURE leaf.
166
167 **/
168 VOID
169 CpuidSignature (
170 VOID
171 )
172 {
173 UINT32 Eax;
174 UINT32 Ebx;
175 UINT32 Ecx;
176 UINT32 Edx;
177 CHAR8 Signature[13];
178
179 AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);
180
181 Print (L"CPUID_SIGNATURE (Leaf %08x)\n", CPUID_SIGNATURE);
182 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx, Edx);
183 PRINT_VALUE (Eax, MaximumLeaf);
184 *(UINT32 *)(Signature + 0) = Ebx;
185 *(UINT32 *)(Signature + 4) = Edx;
186 *(UINT32 *)(Signature + 8) = Ecx;
187 Signature[12] = 0;
188 Print (L" Signature = %a\n", Signature);
189
190 gMaximumBasicFunction = Eax;
191 }
192
193 /**
194 Display CPUID_VERSION_INFO leaf.
195
196 **/
197 VOID
198 CpuidVersionInfo (
199 VOID
200 )
201 {
202 CPUID_VERSION_INFO_EAX Eax;
203 CPUID_VERSION_INFO_EBX Ebx;
204 CPUID_VERSION_INFO_ECX Ecx;
205 CPUID_VERSION_INFO_EDX Edx;
206 UINT32 DisplayFamily;
207 UINT32 DisplayModel;
208
209 if (CPUID_VERSION_INFO > gMaximumBasicFunction) {
210 return;
211 }
212
213 AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
214
215 Print (L"CPUID_VERSION_INFO (Leaf %08x)\n", CPUID_VERSION_INFO);
216 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
217
218 DisplayFamily = Eax.Bits.FamilyId;
219 if (Eax.Bits.FamilyId == 0x0F) {
220 DisplayFamily |= (Eax.Bits.ExtendedFamilyId << 4);
221 }
222
223 DisplayModel = Eax.Bits.Model;
224 if ((Eax.Bits.FamilyId == 0x06) || (Eax.Bits.FamilyId == 0x0f)) {
225 DisplayModel |= (Eax.Bits.ExtendedModelId << 4);
226 }
227
228 Print (L" Family = %x Model = %x Stepping = %x\n", DisplayFamily, DisplayModel, Eax.Bits.SteppingId);
229
230 PRINT_BIT_FIELD (Eax, SteppingId);
231 PRINT_BIT_FIELD (Eax, Model);
232 PRINT_BIT_FIELD (Eax, FamilyId);
233 PRINT_BIT_FIELD (Eax, ProcessorType);
234 PRINT_BIT_FIELD (Eax, ExtendedModelId);
235 PRINT_BIT_FIELD (Eax, ExtendedFamilyId);
236 PRINT_BIT_FIELD (Ebx, BrandIndex);
237 PRINT_BIT_FIELD (Ebx, CacheLineSize);
238 PRINT_BIT_FIELD (Ebx, MaximumAddressableIdsForLogicalProcessors);
239 PRINT_BIT_FIELD (Ebx, InitialLocalApicId);
240 PRINT_BIT_FIELD (Ecx, SSE3);
241 PRINT_BIT_FIELD (Ecx, PCLMULQDQ);
242 PRINT_BIT_FIELD (Ecx, DTES64);
243 PRINT_BIT_FIELD (Ecx, MONITOR);
244 PRINT_BIT_FIELD (Ecx, DS_CPL);
245 PRINT_BIT_FIELD (Ecx, VMX);
246 PRINT_BIT_FIELD (Ecx, SMX);
247 PRINT_BIT_FIELD (Ecx, TM2);
248 PRINT_BIT_FIELD (Ecx, SSSE3);
249 PRINT_BIT_FIELD (Ecx, CNXT_ID);
250 PRINT_BIT_FIELD (Ecx, SDBG);
251 PRINT_BIT_FIELD (Ecx, FMA);
252 PRINT_BIT_FIELD (Ecx, CMPXCHG16B);
253 PRINT_BIT_FIELD (Ecx, xTPR_Update_Control);
254 PRINT_BIT_FIELD (Ecx, PDCM);
255 PRINT_BIT_FIELD (Ecx, PCID);
256 PRINT_BIT_FIELD (Ecx, DCA);
257 PRINT_BIT_FIELD (Ecx, SSE4_1);
258 PRINT_BIT_FIELD (Ecx, SSE4_2);
259 PRINT_BIT_FIELD (Ecx, x2APIC);
260 PRINT_BIT_FIELD (Ecx, MOVBE);
261 PRINT_BIT_FIELD (Ecx, POPCNT);
262 PRINT_BIT_FIELD (Ecx, TSC_Deadline);
263 PRINT_BIT_FIELD (Ecx, AESNI);
264 PRINT_BIT_FIELD (Ecx, XSAVE);
265 PRINT_BIT_FIELD (Ecx, OSXSAVE);
266 PRINT_BIT_FIELD (Ecx, AVX);
267 PRINT_BIT_FIELD (Ecx, F16C);
268 PRINT_BIT_FIELD (Ecx, RDRAND);
269 PRINT_BIT_FIELD (Edx, FPU);
270 PRINT_BIT_FIELD (Edx, VME);
271 PRINT_BIT_FIELD (Edx, DE);
272 PRINT_BIT_FIELD (Edx, PSE);
273 PRINT_BIT_FIELD (Edx, TSC);
274 PRINT_BIT_FIELD (Edx, MSR);
275 PRINT_BIT_FIELD (Edx, PAE);
276 PRINT_BIT_FIELD (Edx, MCE);
277 PRINT_BIT_FIELD (Edx, CX8);
278 PRINT_BIT_FIELD (Edx, APIC);
279 PRINT_BIT_FIELD (Edx, SEP);
280 PRINT_BIT_FIELD (Edx, MTRR);
281 PRINT_BIT_FIELD (Edx, PGE);
282 PRINT_BIT_FIELD (Edx, MCA);
283 PRINT_BIT_FIELD (Edx, CMOV);
284 PRINT_BIT_FIELD (Edx, PAT);
285 PRINT_BIT_FIELD (Edx, PSE_36);
286 PRINT_BIT_FIELD (Edx, PSN);
287 PRINT_BIT_FIELD (Edx, CLFSH);
288 PRINT_BIT_FIELD (Edx, DS);
289 PRINT_BIT_FIELD (Edx, ACPI);
290 PRINT_BIT_FIELD (Edx, MMX);
291 PRINT_BIT_FIELD (Edx, FXSR);
292 PRINT_BIT_FIELD (Edx, SSE);
293 PRINT_BIT_FIELD (Edx, SSE2);
294 PRINT_BIT_FIELD (Edx, SS);
295 PRINT_BIT_FIELD (Edx, HTT);
296 PRINT_BIT_FIELD (Edx, TM);
297 PRINT_BIT_FIELD (Edx, PBE);
298 }
299
300 /**
301 Lookup a cache description string from the mCpuidCacheInfoDescription table.
302
303 @param[in] CacheDescriptor Cache descriptor value from CPUID_CACHE_INFO.
304
305 **/
306 CPUID_CACHE_INFO_DESCRIPTION *
307 LookupCacheDescription (
308 UINT8 CacheDescriptor
309 )
310 {
311 UINTN NumDescriptors;
312 UINTN Descriptor;
313
314 if (CacheDescriptor == 0x00) {
315 return NULL;
316 }
317
318 NumDescriptors = sizeof (mCpuidCacheInfoDescription)/sizeof (mCpuidCacheInfoDescription[0]);
319 for (Descriptor = 0; Descriptor < NumDescriptors; Descriptor++) {
320 if (CacheDescriptor == mCpuidCacheInfoDescription[Descriptor].CacheDescriptor) {
321 return &mCpuidCacheInfoDescription[Descriptor];
322 }
323 }
324
325 return NULL;
326 }
327
328 /**
329 Display CPUID_CACHE_INFO leaf for each supported cache descriptor.
330
331 **/
332 VOID
333 CpuidCacheInfo (
334 VOID
335 )
336 {
337 CPUID_CACHE_INFO_CACHE_TLB Eax;
338 CPUID_CACHE_INFO_CACHE_TLB Ebx;
339 CPUID_CACHE_INFO_CACHE_TLB Ecx;
340 CPUID_CACHE_INFO_CACHE_TLB Edx;
341 UINTN Index;
342 CPUID_CACHE_INFO_DESCRIPTION *CacheDescription;
343
344 if (CPUID_CACHE_INFO > gMaximumBasicFunction) {
345 return;
346 }
347
348 AsmCpuid (CPUID_CACHE_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
349
350 Print (L"CPUID_CACHE_INFO (Leaf %08x)\n", CPUID_CACHE_INFO);
351 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
352 if (Eax.Bits.NotValid == 0) {
353 //
354 // Process Eax.CacheDescriptor[1..3]. Ignore Eax.CacheDescriptor[0]
355 //
356 for (Index = 1; Index < 4; Index++) {
357 CacheDescription = LookupCacheDescription (Eax.CacheDescriptor[Index]);
358 if (CacheDescription != NULL) {
359 Print (
360 L" %-8a %a\n",
361 CacheDescription->Type,
362 CacheDescription->Description
363 );
364 }
365 }
366 }
367
368 if (Ebx.Bits.NotValid == 0) {
369 //
370 // Process Ebx.CacheDescriptor[0..3]
371 //
372 for (Index = 0; Index < 4; Index++) {
373 CacheDescription = LookupCacheDescription (Ebx.CacheDescriptor[Index]);
374 if (CacheDescription != NULL) {
375 Print (
376 L" %-8a %a\n",
377 CacheDescription->Type,
378 CacheDescription->Description
379 );
380 }
381 }
382 }
383
384 if (Ecx.Bits.NotValid == 0) {
385 //
386 // Process Ecx.CacheDescriptor[0..3]
387 //
388 for (Index = 0; Index < 4; Index++) {
389 CacheDescription = LookupCacheDescription (Ecx.CacheDescriptor[Index]);
390 if (CacheDescription != NULL) {
391 Print (
392 L" %-8a %a\n",
393 CacheDescription->Type,
394 CacheDescription->Description
395 );
396 }
397 }
398 }
399
400 if (Edx.Bits.NotValid == 0) {
401 //
402 // Process Edx.CacheDescriptor[0..3]
403 //
404 for (Index = 0; Index < 4; Index++) {
405 CacheDescription = LookupCacheDescription (Edx.CacheDescriptor[Index]);
406 if (CacheDescription != NULL) {
407 Print (
408 L" %-8a %a\n",
409 CacheDescription->Type,
410 CacheDescription->Description
411 );
412 }
413 }
414 }
415 }
416
417 /**
418 Display CPUID_SERIAL_NUMBER leaf if it is supported.
419
420 **/
421 VOID
422 CpuidSerialNumber (
423 VOID
424 )
425 {
426 CPUID_VERSION_INFO_EDX VersionInfoEdx;
427 UINT32 Ecx;
428 UINT32 Edx;
429
430 Print (L"CPUID_SERIAL_NUMBER (Leaf %08x)\n", CPUID_SERIAL_NUMBER);
431
432 if (CPUID_SERIAL_NUMBER > gMaximumBasicFunction) {
433 return;
434 }
435
436 AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
437 if (VersionInfoEdx.Bits.PSN == 0) {
438 Print (L" Not Supported\n");
439 return;
440 }
441
442 AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx);
443 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, 0, Ecx, Edx);
444 Print (L" Processor Serial Number = %08x%08x%08x\n", 0, Edx, Ecx);
445 }
446
447 /**
448 Display CPUID_CACHE_PARAMS for all supported sub-leafs.
449
450 **/
451 VOID
452 CpuidCacheParams (
453 VOID
454 )
455 {
456 UINT32 CacheLevel;
457 CPUID_CACHE_PARAMS_EAX Eax;
458 CPUID_CACHE_PARAMS_EBX Ebx;
459 UINT32 Ecx;
460 CPUID_CACHE_PARAMS_EDX Edx;
461
462 if (CPUID_CACHE_PARAMS > gMaximumBasicFunction) {
463 return;
464 }
465
466 CacheLevel = 0;
467 do {
468 AsmCpuidEx (
469 CPUID_CACHE_PARAMS,
470 CacheLevel,
471 &Eax.Uint32,
472 &Ebx.Uint32,
473 &Ecx,
474 &Edx.Uint32
475 );
476 if (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL) {
477 Print (L"CPUID_CACHE_PARAMS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_CACHE_PARAMS, CacheLevel);
478 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx, Edx.Uint32);
479 PRINT_BIT_FIELD (Eax, CacheType);
480 PRINT_BIT_FIELD (Eax, CacheLevel);
481 PRINT_BIT_FIELD (Eax, SelfInitializingCache);
482 PRINT_BIT_FIELD (Eax, FullyAssociativeCache);
483 PRINT_BIT_FIELD (Eax, MaximumAddressableIdsForLogicalProcessors);
484 PRINT_BIT_FIELD (Eax, MaximumAddressableIdsForProcessorCores);
485 PRINT_BIT_FIELD (Ebx, LineSize);
486 PRINT_BIT_FIELD (Ebx, LinePartitions);
487 PRINT_BIT_FIELD (Ebx, Ways);
488 PRINT_VALUE (Ecx, NumberOfSets);
489 PRINT_BIT_FIELD (Edx, Invalidate);
490 PRINT_BIT_FIELD (Edx, CacheInclusiveness);
491 PRINT_BIT_FIELD (Edx, ComplexCacheIndexing);
492 }
493
494 CacheLevel++;
495 } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);
496 }
497
498 /**
499 Display CPUID_MONITOR_MWAIT leaf.
500
501 **/
502 VOID
503 CpuidMonitorMwait (
504 VOID
505 )
506 {
507 CPUID_MONITOR_MWAIT_EAX Eax;
508 CPUID_MONITOR_MWAIT_EBX Ebx;
509 CPUID_MONITOR_MWAIT_ECX Ecx;
510 CPUID_MONITOR_MWAIT_EDX Edx;
511
512 if (CPUID_MONITOR_MWAIT > gMaximumBasicFunction) {
513 return;
514 }
515
516 AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
517
518 Print (L"CPUID_MONITOR_MWAIT (Leaf %08x)\n", CPUID_MONITOR_MWAIT);
519 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
520
521 PRINT_BIT_FIELD (Eax, SmallestMonitorLineSize);
522 PRINT_BIT_FIELD (Ebx, LargestMonitorLineSize);
523 PRINT_BIT_FIELD (Ecx, ExtensionsSupported);
524 PRINT_BIT_FIELD (Ecx, InterruptAsBreak);
525 PRINT_BIT_FIELD (Edx, C0States);
526 PRINT_BIT_FIELD (Edx, C1States);
527 PRINT_BIT_FIELD (Edx, C2States);
528 PRINT_BIT_FIELD (Edx, C3States);
529 PRINT_BIT_FIELD (Edx, C4States);
530 PRINT_BIT_FIELD (Edx, C5States);
531 PRINT_BIT_FIELD (Edx, C6States);
532 PRINT_BIT_FIELD (Edx, C7States);
533 }
534
535 /**
536 Display CPUID_THERMAL_POWER_MANAGEMENT leaf.
537
538 **/
539 VOID
540 CpuidThermalPowerManagement (
541 VOID
542 )
543 {
544 CPUID_THERMAL_POWER_MANAGEMENT_EAX Eax;
545 CPUID_THERMAL_POWER_MANAGEMENT_EBX Ebx;
546 CPUID_THERMAL_POWER_MANAGEMENT_ECX Ecx;
547
548 if (CPUID_THERMAL_POWER_MANAGEMENT > gMaximumBasicFunction) {
549 return;
550 }
551
552 AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
553
554 Print (L"CPUID_THERMAL_POWER_MANAGEMENT (Leaf %08x)\n", CPUID_THERMAL_POWER_MANAGEMENT);
555 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, 0);
556
557 PRINT_BIT_FIELD (Eax, DigitalTemperatureSensor);
558 PRINT_BIT_FIELD (Eax, TurboBoostTechnology);
559 PRINT_BIT_FIELD (Eax, ARAT);
560 PRINT_BIT_FIELD (Eax, PLN);
561 PRINT_BIT_FIELD (Eax, ECMD);
562 PRINT_BIT_FIELD (Eax, PTM);
563 PRINT_BIT_FIELD (Eax, HWP);
564 PRINT_BIT_FIELD (Eax, HWP_Notification);
565 PRINT_BIT_FIELD (Eax, HWP_Activity_Window);
566 PRINT_BIT_FIELD (Eax, HWP_Energy_Performance_Preference);
567 PRINT_BIT_FIELD (Eax, HWP_Package_Level_Request);
568 PRINT_BIT_FIELD (Eax, HDC);
569 PRINT_BIT_FIELD (Eax, TurboBoostMaxTechnology30);
570 PRINT_BIT_FIELD (Eax, HWPCapabilities);
571 PRINT_BIT_FIELD (Eax, HWPPECIOverride);
572 PRINT_BIT_FIELD (Eax, FlexibleHWP);
573 PRINT_BIT_FIELD (Eax, FastAccessMode);
574 PRINT_BIT_FIELD (Eax, IgnoringIdleLogicalProcessorHWPRequest);
575 PRINT_BIT_FIELD (Ebx, InterruptThresholds);
576 PRINT_BIT_FIELD (Ecx, HardwareCoordinationFeedback);
577 PRINT_BIT_FIELD (Ecx, PerformanceEnergyBias);
578 }
579
580 /**
581 Display CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS for all supported sub-leafs.
582
583 **/
584 VOID
585 CpuidStructuredExtendedFeatureFlags (
586 VOID
587 )
588 {
589 UINT32 Eax;
590 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;
591 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx;
592 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX Edx;
593 UINT32 SubLeaf;
594
595 if (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS > gMaximumBasicFunction) {
596 return;
597 }
598
599 AsmCpuidEx (
600 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
601 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
602 &Eax,
603 NULL,
604 NULL,
605 NULL
606 );
607 for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) {
608 AsmCpuidEx (
609 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
610 SubLeaf,
611 NULL,
612 &Ebx.Uint32,
613 &Ecx.Uint32,
614 &Edx.Uint32
615 );
616 if ((Ebx.Uint32 != 0) || (Ecx.Uint32 != 0) || (Edx.Uint32 != 0)) {
617 Print (L"CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, SubLeaf);
618 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
619 PRINT_BIT_FIELD (Ebx, FSGSBASE);
620 PRINT_BIT_FIELD (Ebx, IA32_TSC_ADJUST);
621 PRINT_BIT_FIELD (Ebx, SGX);
622 PRINT_BIT_FIELD (Ebx, BMI1);
623 PRINT_BIT_FIELD (Ebx, HLE);
624 PRINT_BIT_FIELD (Ebx, AVX2);
625 PRINT_BIT_FIELD (Ebx, FDP_EXCPTN_ONLY);
626 PRINT_BIT_FIELD (Ebx, SMEP);
627 PRINT_BIT_FIELD (Ebx, BMI2);
628 PRINT_BIT_FIELD (Ebx, EnhancedRepMovsbStosb);
629 PRINT_BIT_FIELD (Ebx, INVPCID);
630 PRINT_BIT_FIELD (Ebx, RTM);
631 PRINT_BIT_FIELD (Ebx, RDT_M);
632 PRINT_BIT_FIELD (Ebx, DeprecateFpuCsDs);
633 PRINT_BIT_FIELD (Ebx, MPX);
634 PRINT_BIT_FIELD (Ebx, RDT_A);
635 PRINT_BIT_FIELD (Ebx, AVX512F);
636 PRINT_BIT_FIELD (Ebx, AVX512DQ);
637 PRINT_BIT_FIELD (Ebx, RDSEED);
638 PRINT_BIT_FIELD (Ebx, ADX);
639 PRINT_BIT_FIELD (Ebx, SMAP);
640 PRINT_BIT_FIELD (Ebx, AVX512_IFMA);
641 PRINT_BIT_FIELD (Ebx, CLFLUSHOPT);
642 PRINT_BIT_FIELD (Ebx, CLWB);
643 PRINT_BIT_FIELD (Ebx, IntelProcessorTrace);
644 PRINT_BIT_FIELD (Ebx, AVX512PF);
645 PRINT_BIT_FIELD (Ebx, AVX512ER);
646 PRINT_BIT_FIELD (Ebx, AVX512CD);
647 PRINT_BIT_FIELD (Ebx, SHA);
648 PRINT_BIT_FIELD (Ebx, AVX512BW);
649 PRINT_BIT_FIELD (Ebx, AVX512VL);
650
651 PRINT_BIT_FIELD (Ecx, PREFETCHWT1);
652 PRINT_BIT_FIELD (Ecx, AVX512_VBMI);
653 PRINT_BIT_FIELD (Ecx, UMIP);
654 PRINT_BIT_FIELD (Ecx, PKU);
655 PRINT_BIT_FIELD (Ecx, OSPKE);
656 PRINT_BIT_FIELD (Ecx, AVX512_VPOPCNTDQ);
657 PRINT_BIT_FIELD (Ecx, MAWAU);
658 PRINT_BIT_FIELD (Ecx, RDPID);
659 PRINT_BIT_FIELD (Ecx, SGX_LC);
660
661 PRINT_BIT_FIELD (Edx, AVX512_4VNNIW);
662 PRINT_BIT_FIELD (Edx, AVX512_4FMAPS);
663 PRINT_BIT_FIELD (Edx, EnumeratesSupportForIBRSAndIBPB);
664 PRINT_BIT_FIELD (Edx, EnumeratesSupportForSTIBP);
665 PRINT_BIT_FIELD (Edx, EnumeratesSupportForL1D_FLUSH);
666 PRINT_BIT_FIELD (Edx, EnumeratesSupportForCapability);
667 PRINT_BIT_FIELD (Edx, EnumeratesSupportForSSBD);
668 }
669 }
670 }
671
672 /**
673 Display CPUID_DIRECT_CACHE_ACCESS_INFO leaf.
674
675 **/
676 VOID
677 CpuidDirectCacheAccessInfo (
678 VOID
679 )
680 {
681 UINT32 Eax;
682
683 if (CPUID_DIRECT_CACHE_ACCESS_INFO > gMaximumBasicFunction) {
684 return;
685 }
686
687 AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL);
688 Print (L"CPUID_DIRECT_CACHE_ACCESS_INFO (Leaf %08x)\n", CPUID_DIRECT_CACHE_ACCESS_INFO);
689 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, 0, 0, 0);
690 }
691
692 /**
693 Display CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING leaf.
694
695 **/
696 VOID
697 CpuidArchitecturalPerformanceMonitoring (
698 VOID
699 )
700 {
701 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX Eax;
702 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX Ebx;
703 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX Edx;
704
705 if (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING > gMaximumBasicFunction) {
706 return;
707 }
708
709 AsmCpuid (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING, &Eax.Uint32, &Ebx.Uint32, NULL, &Edx.Uint32);
710 Print (L"CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING (Leaf %08x)\n", CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING);
711 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, 0, Edx.Uint32);
712 PRINT_BIT_FIELD (Eax, ArchPerfMonVerID);
713 PRINT_BIT_FIELD (Eax, PerformanceMonitorCounters);
714 PRINT_BIT_FIELD (Eax, PerformanceMonitorCounterWidth);
715 PRINT_BIT_FIELD (Eax, EbxBitVectorLength);
716 PRINT_BIT_FIELD (Ebx, UnhaltedCoreCycles);
717 PRINT_BIT_FIELD (Ebx, InstructionsRetired);
718 PRINT_BIT_FIELD (Ebx, UnhaltedReferenceCycles);
719 PRINT_BIT_FIELD (Ebx, LastLevelCacheReferences);
720 PRINT_BIT_FIELD (Ebx, LastLevelCacheMisses);
721 PRINT_BIT_FIELD (Ebx, BranchInstructionsRetired);
722 PRINT_BIT_FIELD (Ebx, AllBranchMispredictRetired);
723 PRINT_BIT_FIELD (Edx, FixedFunctionPerformanceCounters);
724 PRINT_BIT_FIELD (Edx, FixedFunctionPerformanceCounterWidth);
725 PRINT_BIT_FIELD (Edx, AnyThreadDeprecation);
726 }
727
728 /**
729 Display CPUID_EXTENDED_TOPOLOGY leafs for all supported levels.
730
731 @param[in] LeafFunction Leaf function index for CPUID_EXTENDED_TOPOLOGY.
732
733 **/
734 VOID
735 CpuidExtendedTopology (
736 UINT32 LeafFunction
737 )
738 {
739 CPUID_EXTENDED_TOPOLOGY_EAX Eax;
740 CPUID_EXTENDED_TOPOLOGY_EBX Ebx;
741 CPUID_EXTENDED_TOPOLOGY_ECX Ecx;
742 UINT32 Edx;
743 UINT32 LevelNumber;
744
745 if (LeafFunction > gMaximumBasicFunction) {
746 return;
747 }
748
749 if ((LeafFunction != CPUID_EXTENDED_TOPOLOGY) && (LeafFunction != CPUID_V2_EXTENDED_TOPOLOGY)) {
750 return;
751 }
752
753 LevelNumber = 0;
754 for (LevelNumber = 0; ; LevelNumber++) {
755 AsmCpuidEx (
756 LeafFunction,
757 LevelNumber,
758 &Eax.Uint32,
759 &Ebx.Uint32,
760 &Ecx.Uint32,
761 &Edx
762 );
763 if (Ecx.Bits.LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {
764 break;
765 }
766
767 Print (
768 L"%a (Leaf %08x, Sub-Leaf %08x)\n",
769 LeafFunction == CPUID_EXTENDED_TOPOLOGY ? "CPUID_EXTENDED_TOPOLOGY" : "CPUID_V2_EXTENDED_TOPOLOGY",
770 LeafFunction,
771 LevelNumber
772 );
773 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx);
774 PRINT_BIT_FIELD (Eax, ApicIdShift);
775 PRINT_BIT_FIELD (Ebx, LogicalProcessors);
776 PRINT_BIT_FIELD (Ecx, LevelNumber);
777 PRINT_BIT_FIELD (Ecx, LevelType);
778 PRINT_VALUE (Edx, x2APIC_ID);
779 }
780 }
781
782 /**
783 Display CPUID_EXTENDED_STATE sub-leaf.
784
785 **/
786 VOID
787 CpuidExtendedStateSubLeaf (
788 VOID
789 )
790 {
791 CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax;
792 UINT32 Ebx;
793 CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx;
794 UINT32 Edx;
795
796 AsmCpuidEx (
797 CPUID_EXTENDED_STATE,
798 CPUID_EXTENDED_STATE_SUB_LEAF,
799 &Eax.Uint32,
800 &Ebx,
801 &Ecx.Uint32,
802 &Edx
803 );
804 Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF);
805 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx);
806 PRINT_BIT_FIELD (Eax, XSAVEOPT);
807 PRINT_BIT_FIELD (Eax, XSAVEC);
808 PRINT_BIT_FIELD (Eax, XGETBV);
809 PRINT_BIT_FIELD (Eax, XSAVES);
810 PRINT_VALUE (Ebx, EnabledSaveStateSize_XCR0_IA32_XSS);
811 PRINT_BIT_FIELD (Ecx, XCR0);
812 PRINT_BIT_FIELD (Ecx, HWPState);
813 PRINT_BIT_FIELD (Ecx, PT);
814 PRINT_BIT_FIELD (Ecx, XCR0_1);
815 PRINT_VALUE (Edx, IA32_XSS_Supported_32_63);
816 }
817
818 /**
819 Display CPUID_EXTENDED_STATE size and offset information sub-leaf.
820
821 **/
822 VOID
823 CpuidExtendedStateSizeOffset (
824 VOID
825 )
826 {
827 UINT32 Eax;
828 UINT32 Ebx;
829 CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX Ecx;
830 UINT32 Edx;
831 UINT32 SubLeaf;
832
833 for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) {
834 AsmCpuidEx (
835 CPUID_EXTENDED_STATE,
836 SubLeaf,
837 &Eax,
838 &Ebx,
839 &Ecx.Uint32,
840 &Edx
841 );
842 if (Edx != 0) {
843 Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, SubLeaf);
844 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx.Uint32, Edx);
845 PRINT_VALUE (Eax, FeatureSaveStateSize);
846 PRINT_VALUE (Ebx, FeatureSaveStateOffset);
847 PRINT_BIT_FIELD (Ecx, XSS);
848 PRINT_BIT_FIELD (Ecx, Compacted);
849 }
850 }
851 }
852
853 /**
854 Display CPUID_EXTENDED_STATE main leaf and sub-leafs.
855
856 **/
857 VOID
858 CpuidExtendedStateMainLeaf (
859 VOID
860 )
861 {
862 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax;
863 UINT32 Ebx;
864 UINT32 Ecx;
865 UINT32 Edx;
866
867 if (CPUID_EXTENDED_STATE > gMaximumBasicFunction) {
868 return;
869 }
870
871 AsmCpuidEx (
872 CPUID_EXTENDED_STATE,
873 CPUID_EXTENDED_STATE_MAIN_LEAF,
874 &Eax.Uint32,
875 &Ebx,
876 &Ecx,
877 &Edx
878 );
879 Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF);
880 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx, Edx);
881 PRINT_BIT_FIELD (Eax, x87);
882 PRINT_BIT_FIELD (Eax, SSE);
883 PRINT_BIT_FIELD (Eax, AVX);
884 PRINT_BIT_FIELD (Eax, MPX);
885 PRINT_BIT_FIELD (Eax, AVX_512);
886 PRINT_BIT_FIELD (Eax, IA32_XSS);
887 PRINT_BIT_FIELD (Eax, PKRU);
888 PRINT_BIT_FIELD (Eax, IA32_XSS_2);
889 PRINT_VALUE (Ebx, EnabledSaveStateSize);
890 PRINT_VALUE (Ecx, SupportedSaveStateSize);
891 PRINT_VALUE (Edx, XCR0_Supported_32_63);
892
893 CpuidExtendedStateSubLeaf ();
894 CpuidExtendedStateSizeOffset ();
895 }
896
897 /**
898 Display CPUID_INTEL_RDT_MONITORING enumeration sub-leaf.
899
900 **/
901 VOID
902 CpuidIntelRdtMonitoringEnumerationSubLeaf (
903 VOID
904 )
905 {
906 UINT32 Ebx;
907 CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;
908
909 if (CPUID_INTEL_RDT_MONITORING > gMaximumBasicFunction) {
910 return;
911 }
912
913 AsmCpuidEx (
914 CPUID_INTEL_RDT_MONITORING,
915 CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,
916 NULL,
917 &Ebx,
918 NULL,
919 &Edx.Uint32
920 );
921 Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF);
922 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, 0, Edx.Uint32);
923 PRINT_VALUE (Ebx, Maximum_RMID_Range);
924 PRINT_BIT_FIELD (Edx, L3CacheRDT_M);
925 }
926
927 /**
928 Display CPUID_INTEL_RDT_MONITORING L3 cache capability sub-leaf.
929
930 **/
931 VOID
932 CpuidIntelRdtMonitoringL3CacheCapabilitySubLeaf (
933 VOID
934 )
935 {
936 UINT32 Ebx;
937 UINT32 Ecx;
938 CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx;
939
940 if (CPUID_INTEL_RDT_MONITORING > gMaximumBasicFunction) {
941 return;
942 }
943
944 AsmCpuidEx (
945 CPUID_INTEL_RDT_MONITORING,
946 CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,
947 NULL,
948 &Ebx,
949 &Ecx,
950 &Edx.Uint32
951 );
952 Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF);
953 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, Ecx, Edx.Uint32);
954 PRINT_VALUE (Ebx, OccupancyConversionFactor);
955 PRINT_VALUE (Ecx, Maximum_RMID_Range);
956 PRINT_BIT_FIELD (Edx, L3CacheOccupancyMonitoring);
957 PRINT_BIT_FIELD (Edx, L3CacheTotalBandwidthMonitoring);
958 PRINT_BIT_FIELD (Edx, L3CacheLocalBandwidthMonitoring);
959 }
960
961 /**
962 Display CPUID_INTEL_RDT_ALLOCATION memory bandwidth allocation technology enumeration
963 sub-leaf.
964
965 **/
966 VOID
967 CpuidIntelRdtAllocationMemoryBandwidthSubLeaf (
968 VOID
969 )
970 {
971 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX Eax;
972 UINT32 Ebx;
973 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX Ecx;
974 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX Edx;
975
976 AsmCpuidEx (
977 CPUID_INTEL_RDT_ALLOCATION,
978 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF,
979 &Eax.Uint32,
980 &Ebx,
981 &Ecx.Uint32,
982 &Edx.Uint32
983 );
984 Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF);
985 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32);
986 PRINT_BIT_FIELD (Eax, MaximumMBAThrottling);
987 PRINT_VALUE (Ebx, AllocationUnitBitMap);
988 PRINT_BIT_FIELD (Ecx, Liner);
989 PRINT_BIT_FIELD (Edx, HighestCosNumber);
990 }
991
992 /**
993 Display CPUID_INTEL_RDT_ALLOCATION L3 cache allocation technology enumeration
994 sub-leaf.
995
996 **/
997 VOID
998 CpuidIntelRdtAllocationL3CacheSubLeaf (
999 VOID
1000 )
1001 {
1002 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX Eax;
1003 UINT32 Ebx;
1004 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX Ecx;
1005 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx;
1006
1007 AsmCpuidEx (
1008 CPUID_INTEL_RDT_ALLOCATION,
1009 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,
1010 &Eax.Uint32,
1011 &Ebx,
1012 &Ecx.Uint32,
1013 &Edx.Uint32
1014 );
1015 Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF);
1016 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32);
1017 PRINT_BIT_FIELD (Eax, CapacityLength);
1018 PRINT_VALUE (Ebx, AllocationUnitBitMap);
1019 PRINT_BIT_FIELD (Ecx, CodeDataPrioritization);
1020 PRINT_BIT_FIELD (Edx, HighestCosNumber);
1021 }
1022
1023 /**
1024 Display CPUID_INTEL_RDT_ALLOCATION L2 cache allocation technology enumeration
1025 sub-leaf.
1026
1027 **/
1028 VOID
1029 CpuidIntelRdtAllocationL2CacheSubLeaf (
1030 VOID
1031 )
1032 {
1033 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX Eax;
1034 UINT32 Ebx;
1035 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx;
1036
1037 AsmCpuidEx (
1038 CPUID_INTEL_RDT_ALLOCATION,
1039 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,
1040 &Eax.Uint32,
1041 &Ebx,
1042 NULL,
1043 &Edx.Uint32
1044 );
1045 Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF);
1046 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32);
1047 PRINT_BIT_FIELD (Eax, CapacityLength);
1048 PRINT_VALUE (Ebx, AllocationUnitBitMap);
1049 PRINT_BIT_FIELD (Edx, HighestCosNumber);
1050 }
1051
1052 /**
1053 Display CPUID_INTEL_RDT_ALLOCATION main leaf and sub-leaves.
1054
1055 **/
1056 VOID
1057 CpuidIntelRdtAllocationMainLeaf (
1058 VOID
1059 )
1060 {
1061 CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX Ebx;
1062
1063 if (CPUID_INTEL_RDT_ALLOCATION > gMaximumBasicFunction) {
1064 return;
1065 }
1066
1067 AsmCpuidEx (
1068 CPUID_INTEL_RDT_ALLOCATION,
1069 CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,
1070 NULL,
1071 &Ebx.Uint32,
1072 NULL,
1073 NULL
1074 );
1075 Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF);
1076 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx.Uint32, 0, 0);
1077 PRINT_BIT_FIELD (Ebx, L3CacheAllocation);
1078 PRINT_BIT_FIELD (Ebx, L2CacheAllocation);
1079 PRINT_BIT_FIELD (Ebx, MemoryBandwidth);
1080 CpuidIntelRdtAllocationMemoryBandwidthSubLeaf ();
1081 CpuidIntelRdtAllocationL3CacheSubLeaf ();
1082 CpuidIntelRdtAllocationL2CacheSubLeaf ();
1083 }
1084
1085 /**
1086 Display Sub-Leaf 0 Enumeration of Intel SGX Capabilities.
1087
1088 **/
1089 VOID
1090 CpuidEnumerationOfIntelSgxCapabilities0SubLeaf (
1091 VOID
1092 )
1093 {
1094 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX Eax;
1095 UINT32 Ebx;
1096 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx;
1097
1098 AsmCpuidEx (
1099 CPUID_INTEL_SGX,
1100 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,
1101 &Eax.Uint32,
1102 &Ebx,
1103 NULL,
1104 &Edx.Uint32
1105 );
1106 Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF);
1107 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32);
1108 PRINT_BIT_FIELD (Eax, SGX1);
1109 PRINT_BIT_FIELD (Eax, SGX2);
1110 PRINT_BIT_FIELD (Eax, ENCLV);
1111 PRINT_BIT_FIELD (Eax, ENCLS);
1112 PRINT_BIT_FIELD (Edx, MaxEnclaveSize_Not64);
1113 PRINT_BIT_FIELD (Edx, MaxEnclaveSize_64);
1114 }
1115
1116 /**
1117 Display Sub-Leaf 1 Enumeration of Intel SGX Capabilities.
1118
1119 **/
1120 VOID
1121 CpuidEnumerationOfIntelSgxCapabilities1SubLeaf (
1122 VOID
1123 )
1124 {
1125 UINT32 Eax;
1126 UINT32 Ebx;
1127 UINT32 Ecx;
1128 UINT32 Edx;
1129
1130 AsmCpuidEx (
1131 CPUID_INTEL_SGX,
1132 CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,
1133 &Eax,
1134 &Ebx,
1135 &Ecx,
1136 &Edx
1137 );
1138 Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF);
1139 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx, Edx);
1140 }
1141
1142 /**
1143 Display Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources.
1144
1145 **/
1146 VOID
1147 CpuidEnumerationOfIntelSgxResourcesSubLeaf (
1148 VOID
1149 )
1150 {
1151 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX Eax;
1152 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX Ebx;
1153 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX Ecx;
1154 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX Edx;
1155 UINT32 SubLeaf;
1156
1157 SubLeaf = CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF;
1158 do {
1159 AsmCpuidEx (
1160 CPUID_INTEL_SGX,
1161 SubLeaf,
1162 &Eax.Uint32,
1163 &Ebx.Uint32,
1164 &Ecx.Uint32,
1165 &Edx.Uint32
1166 );
1167 if (Eax.Bits.SubLeafType == 0x1) {
1168 Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, SubLeaf);
1169 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
1170 PRINT_BIT_FIELD (Eax, SubLeafType);
1171 PRINT_BIT_FIELD (Eax, LowAddressOfEpcSection);
1172 PRINT_BIT_FIELD (Ebx, HighAddressOfEpcSection);
1173 PRINT_BIT_FIELD (Ecx, EpcSection);
1174 PRINT_BIT_FIELD (Ecx, LowSizeOfEpcSection);
1175 PRINT_BIT_FIELD (Edx, HighSizeOfEpcSection);
1176 }
1177
1178 SubLeaf++;
1179 } while (Eax.Bits.SubLeafType == 0x1);
1180 }
1181
1182 /**
1183 Display Intel SGX Resource Enumeration.
1184
1185 **/
1186 VOID
1187 CpuidEnumerationOfIntelSgx (
1188 VOID
1189 )
1190 {
1191 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;
1192
1193 if (CPUID_INTEL_SGX > gMaximumBasicFunction) {
1194 return;
1195 }
1196
1197 AsmCpuidEx (
1198 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
1199 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
1200 NULL,
1201 &Ebx.Uint32,
1202 NULL,
1203 NULL
1204 );
1205 if (Ebx.Bits.SGX != 1) {
1206 //
1207 // Only if CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor has support
1208 // for Intel SGX.
1209 //
1210 return;
1211 }
1212
1213 CpuidEnumerationOfIntelSgxCapabilities0SubLeaf ();
1214 CpuidEnumerationOfIntelSgxCapabilities1SubLeaf ();
1215 CpuidEnumerationOfIntelSgxResourcesSubLeaf ();
1216 }
1217
1218 /**
1219 Display CPUID_INTEL_PROCESSOR_TRACE sub-leafs.
1220
1221 @param[in] MaximumSubLeaf Maximum sub-leaf index for CPUID_INTEL_PROCESSOR_TRACE.
1222
1223 **/
1224 VOID
1225 CpuidIntelProcessorTraceSubLeaf (
1226 UINT32 MaximumSubLeaf
1227 )
1228 {
1229 UINT32 SubLeaf;
1230 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX Eax;
1231 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX Ebx;
1232
1233 for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) {
1234 AsmCpuidEx (
1235 CPUID_INTEL_PROCESSOR_TRACE,
1236 SubLeaf,
1237 &Eax.Uint32,
1238 &Ebx.Uint32,
1239 NULL,
1240 NULL
1241 );
1242 Print (L"CPUID_INTEL_PROCESSOR_TRACE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_PROCESSOR_TRACE, SubLeaf);
1243 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, 0, 0);
1244 PRINT_BIT_FIELD (Eax, ConfigurableAddressRanges);
1245 PRINT_BIT_FIELD (Eax, MtcPeriodEncodings);
1246 PRINT_BIT_FIELD (Ebx, CycleThresholdEncodings);
1247 PRINT_BIT_FIELD (Ebx, PsbFrequencyEncodings);
1248 }
1249 }
1250
1251 /**
1252 Display CPUID_INTEL_PROCESSOR_TRACE main leaf and sub-leafs.
1253
1254 **/
1255 VOID
1256 CpuidIntelProcessorTraceMainLeaf (
1257 VOID
1258 )
1259 {
1260 UINT32 Eax;
1261 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Ebx;
1262 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx;
1263
1264 if (CPUID_INTEL_PROCESSOR_TRACE > gMaximumBasicFunction) {
1265 return;
1266 }
1267
1268 AsmCpuidEx (
1269 CPUID_INTEL_PROCESSOR_TRACE,
1270 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,
1271 &Eax,
1272 &Ebx.Uint32,
1273 &Ecx.Uint32,
1274 NULL
1275 );
1276 Print (L"CPUID_INTEL_PROCESSOR_TRACE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF);
1277 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, 0);
1278 PRINT_VALUE (Eax, MaximumSubLeaf);
1279 PRINT_BIT_FIELD (Ebx, Cr3Filter);
1280 PRINT_BIT_FIELD (Ebx, ConfigurablePsb);
1281 PRINT_BIT_FIELD (Ebx, IpTraceStopFiltering);
1282 PRINT_BIT_FIELD (Ebx, Mtc);
1283 PRINT_BIT_FIELD (Ebx, PTWrite);
1284 PRINT_BIT_FIELD (Ebx, PowerEventTrace);
1285 PRINT_BIT_FIELD (Ecx, RTIT);
1286 PRINT_BIT_FIELD (Ecx, ToPA);
1287 PRINT_BIT_FIELD (Ecx, SingleRangeOutput);
1288 PRINT_BIT_FIELD (Ecx, TraceTransportSubsystem);
1289 PRINT_BIT_FIELD (Ecx, LIP);
1290
1291 CpuidIntelProcessorTraceSubLeaf (Eax);
1292 }
1293
1294 /**
1295 Display CPUID_TIME_STAMP_COUNTER leaf.
1296
1297 **/
1298 VOID
1299 CpuidTimeStampCounter (
1300 VOID
1301 )
1302 {
1303 UINT32 Eax;
1304 UINT32 Ebx;
1305 UINT32 Ecx;
1306
1307 if (CPUID_TIME_STAMP_COUNTER > gMaximumBasicFunction) {
1308 return;
1309 }
1310
1311 AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL);
1312 Print (L"CPUID_TIME_STAMP_COUNTER (Leaf %08x)\n", CPUID_TIME_STAMP_COUNTER);
1313 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx, 0);
1314 }
1315
1316 /**
1317 Display CPUID_PROCESSOR_FREQUENCY leaf.
1318
1319 **/
1320 VOID
1321 CpuidProcessorFrequency (
1322 VOID
1323 )
1324 {
1325 CPUID_PROCESSOR_FREQUENCY_EAX Eax;
1326 CPUID_PROCESSOR_FREQUENCY_EBX Ebx;
1327 CPUID_PROCESSOR_FREQUENCY_ECX Ecx;
1328
1329 if (CPUID_PROCESSOR_FREQUENCY > gMaximumBasicFunction) {
1330 return;
1331 }
1332
1333 AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
1334 Print (L"CPUID_PROCESSOR_FREQUENCY (Leaf %08x)\n", CPUID_PROCESSOR_FREQUENCY);
1335 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, 0);
1336 PRINT_BIT_FIELD (Eax, ProcessorBaseFrequency);
1337 PRINT_BIT_FIELD (Ebx, MaximumFrequency);
1338 PRINT_BIT_FIELD (Ecx, BusFrequency);
1339 }
1340
1341 /**
1342 Display CPUID_SOC_VENDOR sub-leafs that contain the SoC Vendor Brand String.
1343 Also display these sub-leafs as a single SoC Vendor Brand String.
1344
1345 **/
1346 VOID
1347 CpuidSocVendorBrandString (
1348 VOID
1349 )
1350 {
1351 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;
1352 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;
1353 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;
1354 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;
1355 //
1356 // Array to store brand string from 3 brand string leafs with
1357 // 4 32-bit brand string values per leaf and an extra value to
1358 // null terminate the string.
1359 //
1360 UINT32 BrandString[3 * 4 + 1];
1361
1362 AsmCpuidEx (
1363 CPUID_SOC_VENDOR,
1364 CPUID_SOC_VENDOR_BRAND_STRING1,
1365 &Eax.Uint32,
1366 &Ebx.Uint32,
1367 &Ecx.Uint32,
1368 &Edx.Uint32
1369 );
1370 Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1);
1371 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
1372 BrandString[0] = Eax.Uint32;
1373 BrandString[1] = Ebx.Uint32;
1374 BrandString[2] = Ecx.Uint32;
1375 BrandString[3] = Edx.Uint32;
1376
1377 AsmCpuidEx (
1378 CPUID_SOC_VENDOR,
1379 CPUID_SOC_VENDOR_BRAND_STRING2,
1380 &Eax.Uint32,
1381 &Ebx.Uint32,
1382 &Ecx.Uint32,
1383 &Edx.Uint32
1384 );
1385 Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2);
1386 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
1387 BrandString[4] = Eax.Uint32;
1388 BrandString[5] = Ebx.Uint32;
1389 BrandString[6] = Ecx.Uint32;
1390 BrandString[7] = Edx.Uint32;
1391
1392 AsmCpuidEx (
1393 CPUID_SOC_VENDOR,
1394 CPUID_SOC_VENDOR_BRAND_STRING3,
1395 &Eax.Uint32,
1396 &Ebx.Uint32,
1397 &Ecx.Uint32,
1398 &Edx.Uint32
1399 );
1400 Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3);
1401 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
1402 BrandString[8] = Eax.Uint32;
1403 BrandString[9] = Ebx.Uint32;
1404 BrandString[10] = Ecx.Uint32;
1405 BrandString[11] = Edx.Uint32;
1406
1407 BrandString[12] = 0;
1408
1409 Print (L"Vendor Brand String = %a\n", (CHAR8 *)BrandString);
1410 }
1411
1412 /**
1413 Display CPUID_SOC_VENDOR main leaf and sub-leafs.
1414
1415 **/
1416 VOID
1417 CpuidSocVendor (
1418 VOID
1419 )
1420 {
1421 UINT32 Eax;
1422 CPUID_SOC_VENDOR_MAIN_LEAF_EBX Ebx;
1423 UINT32 Ecx;
1424 UINT32 Edx;
1425
1426 if (CPUID_SOC_VENDOR > gMaximumBasicFunction) {
1427 return;
1428 }
1429
1430 AsmCpuidEx (
1431 CPUID_SOC_VENDOR,
1432 CPUID_SOC_VENDOR_MAIN_LEAF,
1433 &Eax,
1434 &Ebx.Uint32,
1435 &Ecx,
1436 &Edx
1437 );
1438 Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF);
1439 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx, Edx);
1440 if (Eax < 3) {
1441 Print (L" Not Supported\n");
1442 return;
1443 }
1444
1445 PRINT_VALUE (Eax, MaxSOCID_Index);
1446 PRINT_BIT_FIELD (Ebx, SocVendorId);
1447 PRINT_BIT_FIELD (Ebx, IsVendorScheme);
1448 PRINT_VALUE (Ecx, ProjectID);
1449 PRINT_VALUE (Edx, SteppingID);
1450 CpuidSocVendorBrandString ();
1451 }
1452
1453 /**
1454 Display CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS main leaf and sub-leafs.
1455
1456 **/
1457 VOID
1458 CpuidDeterministicAddressTranslationParameters (
1459 VOID
1460 )
1461 {
1462 UINT32 Eax;
1463 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX Ebx;
1464 UINT32 Ecx;
1465 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX Edx;
1466
1467 if (CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS > gMaximumBasicFunction) {
1468 return;
1469 }
1470
1471 AsmCpuidEx (
1472 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS,
1473 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF,
1474 &Eax,
1475 &Ebx.Uint32,
1476 &Ecx,
1477 &Edx.Uint32
1478 );
1479 Print (L"CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS, CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF);
1480 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx, Edx.Uint32);
1481
1482 PRINT_VALUE (Eax, MaxID_Index);
1483 PRINT_BIT_FIELD (Ebx, Page4K);
1484 PRINT_BIT_FIELD (Ebx, Page2M);
1485 PRINT_BIT_FIELD (Ebx, Page4M);
1486 PRINT_BIT_FIELD (Ebx, Page1G);
1487 PRINT_BIT_FIELD (Ebx, Partitioning);
1488 PRINT_BIT_FIELD (Ebx, Way);
1489
1490 PRINT_VALUE (Ecx, NumberOfSets);
1491
1492 PRINT_BIT_FIELD (Edx, TranslationCacheType);
1493 PRINT_BIT_FIELD (Edx, TranslationCacheLevel);
1494 PRINT_BIT_FIELD (Edx, FullyAssociative);
1495 PRINT_BIT_FIELD (Edx, MaximumNum);
1496 }
1497
1498 /**
1499 Display CPUID_EXTENDED_FUNCTION leaf.
1500
1501 **/
1502 VOID
1503 CpuidExtendedFunction (
1504 VOID
1505 )
1506 {
1507 UINT32 Eax;
1508
1509 AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);
1510 Print (L"CPUID_EXTENDED_FUNCTION (Leaf %08x)\n", CPUID_EXTENDED_FUNCTION);
1511 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, 0, 0, 0);
1512 PRINT_VALUE (Eax, MaximumExtendedFunction);
1513
1514 gMaximumExtendedFunction = Eax;
1515 }
1516
1517 /**
1518 Display CPUID_EXTENDED_CPU_SIG leaf.
1519
1520 **/
1521 VOID
1522 CpuidExtendedCpuSig (
1523 VOID
1524 )
1525 {
1526 UINT32 Eax;
1527 CPUID_EXTENDED_CPU_SIG_ECX Ecx;
1528 CPUID_EXTENDED_CPU_SIG_EDX Edx;
1529
1530 if (CPUID_EXTENDED_CPU_SIG > gMaximumExtendedFunction) {
1531 return;
1532 }
1533
1534 AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32);
1535 Print (L"CPUID_EXTENDED_CPU_SIG (Leaf %08x)\n", CPUID_EXTENDED_CPU_SIG);
1536 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, 0, Ecx.Uint32, Edx.Uint32);
1537 PRINT_BIT_FIELD (Ecx, LAHF_SAHF);
1538 PRINT_BIT_FIELD (Ecx, LZCNT);
1539 PRINT_BIT_FIELD (Ecx, PREFETCHW);
1540 PRINT_BIT_FIELD (Edx, SYSCALL_SYSRET);
1541 PRINT_BIT_FIELD (Edx, NX);
1542 PRINT_BIT_FIELD (Edx, Page1GB);
1543 PRINT_BIT_FIELD (Edx, RDTSCP);
1544 PRINT_BIT_FIELD (Edx, LM);
1545 }
1546
1547 /**
1548 Display CPUID_BRAND_STRING1, CPUID_BRAND_STRING2 and CPUID_BRAND_STRING3
1549 leafs. Also display these three leafs as a single brand string.
1550
1551 **/
1552 VOID
1553 CpuidProcessorBrandString (
1554 VOID
1555 )
1556 {
1557 CPUID_BRAND_STRING_DATA Eax;
1558 CPUID_BRAND_STRING_DATA Ebx;
1559 CPUID_BRAND_STRING_DATA Ecx;
1560 CPUID_BRAND_STRING_DATA Edx;
1561 //
1562 // Array to store brand string from 3 brand string leafs with
1563 // 4 32-bit brand string values per leaf and an extra value to
1564 // null terminate the string.
1565 //
1566 UINT32 BrandString[3 * 4 + 1];
1567
1568 if (CPUID_BRAND_STRING1 <= gMaximumExtendedFunction) {
1569 AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
1570 Print (L"CPUID_BRAND_STRING1 (Leaf %08x)\n", CPUID_BRAND_STRING1);
1571 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
1572 BrandString[0] = Eax.Uint32;
1573 BrandString[1] = Ebx.Uint32;
1574 BrandString[2] = Ecx.Uint32;
1575 BrandString[3] = Edx.Uint32;
1576 }
1577
1578 if (CPUID_BRAND_STRING2 <= gMaximumExtendedFunction) {
1579 AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
1580 Print (L"CPUID_BRAND_STRING2 (Leaf %08x)\n", CPUID_BRAND_STRING2);
1581 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
1582 BrandString[4] = Eax.Uint32;
1583 BrandString[5] = Ebx.Uint32;
1584 BrandString[6] = Ecx.Uint32;
1585 BrandString[7] = Edx.Uint32;
1586 }
1587
1588 if (CPUID_BRAND_STRING3 <= gMaximumExtendedFunction) {
1589 AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
1590 Print (L"CPUID_BRAND_STRING3 (Leaf %08x)\n", CPUID_BRAND_STRING3);
1591 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
1592 BrandString[8] = Eax.Uint32;
1593 BrandString[9] = Ebx.Uint32;
1594 BrandString[10] = Ecx.Uint32;
1595 BrandString[11] = Edx.Uint32;
1596 }
1597
1598 BrandString[12] = 0;
1599
1600 Print (L"Brand String = %a\n", (CHAR8 *)BrandString);
1601 }
1602
1603 /**
1604 Display CPUID_EXTENDED_CACHE_INFO leaf.
1605
1606 **/
1607 VOID
1608 CpuidExtendedCacheInfo (
1609 VOID
1610 )
1611 {
1612 CPUID_EXTENDED_CACHE_INFO_ECX Ecx;
1613
1614 if (CPUID_EXTENDED_CACHE_INFO > gMaximumExtendedFunction) {
1615 return;
1616 }
1617
1618 AsmCpuid (CPUID_EXTENDED_CACHE_INFO, NULL, NULL, &Ecx.Uint32, NULL);
1619 Print (L"CPUID_EXTENDED_CACHE_INFO (Leaf %08x)\n", CPUID_EXTENDED_CACHE_INFO);
1620 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, 0, Ecx.Uint32, 0);
1621 PRINT_BIT_FIELD (Ecx, CacheLineSize);
1622 PRINT_BIT_FIELD (Ecx, L2Associativity);
1623 PRINT_BIT_FIELD (Ecx, CacheSize);
1624 }
1625
1626 /**
1627 Display CPUID_EXTENDED_TIME_STAMP_COUNTER leaf.
1628
1629 **/
1630 VOID
1631 CpuidExtendedTimeStampCounter (
1632 VOID
1633 )
1634 {
1635 CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX Edx;
1636
1637 if (CPUID_EXTENDED_TIME_STAMP_COUNTER > gMaximumExtendedFunction) {
1638 return;
1639 }
1640
1641 AsmCpuid (CPUID_EXTENDED_TIME_STAMP_COUNTER, NULL, NULL, NULL, &Edx.Uint32);
1642 Print (L"CPUID_EXTENDED_TIME_STAMP_COUNTER (Leaf %08x)\n", CPUID_EXTENDED_TIME_STAMP_COUNTER);
1643 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, 0, 0, Edx.Uint32);
1644 PRINT_BIT_FIELD (Edx, InvariantTsc);
1645 }
1646
1647 /**
1648 Display CPUID_VIR_PHY_ADDRESS_SIZE leaf.
1649
1650 **/
1651 VOID
1652 CpuidVirPhyAddressSize (
1653 VOID
1654 )
1655 {
1656 CPUID_VIR_PHY_ADDRESS_SIZE_EAX Eax;
1657
1658 if (CPUID_VIR_PHY_ADDRESS_SIZE > gMaximumExtendedFunction) {
1659 return;
1660 }
1661
1662 AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Eax.Uint32, NULL, NULL, NULL);
1663 Print (L"CPUID_VIR_PHY_ADDRESS_SIZE (Leaf %08x)\n", CPUID_VIR_PHY_ADDRESS_SIZE);
1664 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, 0, 0, 0);
1665 PRINT_BIT_FIELD (Eax, PhysicalAddressBits);
1666 PRINT_BIT_FIELD (Eax, LinearAddressBits);
1667 }
1668
1669 /**
1670 The user Entry Point for Application. The user code starts with this function
1671 as the real entry point for the application.
1672
1673 @param[in] ImageHandle The firmware allocated handle for the EFI image.
1674 @param[in] SystemTable A pointer to the EFI System Table.
1675
1676 @retval EFI_SUCCESS The entry point is executed successfully.
1677 @retval other Some error occurs when executing this entry point.
1678
1679 **/
1680 EFI_STATUS
1681 EFIAPI
1682 UefiMain (
1683 IN EFI_HANDLE ImageHandle,
1684 IN EFI_SYSTEM_TABLE *SystemTable
1685 )
1686 {
1687 Print (L"UEFI CPUID Version 0.5\n");
1688
1689 CpuidSignature ();
1690 CpuidVersionInfo ();
1691 CpuidCacheInfo ();
1692 CpuidSerialNumber ();
1693 CpuidCacheParams ();
1694 CpuidMonitorMwait ();
1695 CpuidThermalPowerManagement ();
1696 CpuidStructuredExtendedFeatureFlags ();
1697 CpuidDirectCacheAccessInfo ();
1698 CpuidArchitecturalPerformanceMonitoring ();
1699 CpuidExtendedTopology (CPUID_EXTENDED_TOPOLOGY);
1700 CpuidExtendedStateMainLeaf ();
1701 CpuidIntelRdtMonitoringEnumerationSubLeaf ();
1702 CpuidIntelRdtMonitoringL3CacheCapabilitySubLeaf ();
1703 CpuidIntelRdtAllocationMainLeaf ();
1704 CpuidEnumerationOfIntelSgx ();
1705 CpuidIntelProcessorTraceMainLeaf ();
1706 CpuidTimeStampCounter ();
1707 CpuidProcessorFrequency ();
1708 CpuidSocVendor ();
1709 CpuidDeterministicAddressTranslationParameters ();
1710 CpuidExtendedTopology (CPUID_V2_EXTENDED_TOPOLOGY);
1711 CpuidExtendedFunction ();
1712 CpuidExtendedCpuSig ();
1713 CpuidProcessorBrandString ();
1714 CpuidExtendedCacheInfo ();
1715 CpuidExtendedTimeStampCounter ();
1716 CpuidVirPhyAddressSize ();
1717
1718 return EFI_SUCCESS;
1719 }
EFI Development Kit II mirror for PVE