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1 /** @file
2 Definitions for CPU S3 data.
3
4 Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #ifndef _ACPI_CPU_DATA_H_
16 #define _ACPI_CPU_DATA_H_
17
18 //
19 // Register types in register table
20 //
21 typedef enum {
22 Msr,
23 ControlRegister,
24 MemoryMapped,
25 CacheControl,
26
27 //
28 // Semaphore type used to control the execute sequence of the Msr.
29 // It will be insert between two Msr which has execute dependence.
30 //
31 Semaphore,
32 InvalidReg
33 } REGISTER_TYPE;
34
35 //
36 // Describe the dependency type for different features.
37 // The value set to CPU_REGISTER_TABLE_ENTRY.Value when the REGISTER_TYPE is Semaphore.
38 //
39 typedef enum {
40 NoneDepType,
41 ThreadDepType,
42 CoreDepType,
43 PackageDepType,
44 InvalidDepType
45 } CPU_FEATURE_DEPENDENCE_TYPE;
46
47 //
48 // CPU information.
49 //
50 typedef struct {
51 //
52 // Record the package count in this CPU.
53 //
54 UINT32 PackageCount;
55 //
56 // Record the max core count in this CPU.
57 // Different packages may have different core count, this value
58 // save the max core count in all the packages.
59 //
60 UINT32 MaxCoreCount;
61 //
62 // Record the max thread count in this CPU.
63 // Different cores may have different thread count, this value
64 // save the max thread count in all the cores.
65 //
66 UINT32 MaxThreadCount;
67 //
68 // This field points to an array.
69 // This array saves valid core count (type UINT32) of each package.
70 // The array has PackageCount elements.
71 //
72 // If the platform does not support MSR setting at S3 resume, and
73 // therefore it doesn't need the dependency semaphores, it should set
74 // this field to 0.
75 //
76 EFI_PHYSICAL_ADDRESS ValidCoreCountPerPackage;
77 } CPU_STATUS_INFORMATION;
78
79 //
80 // Element of register table entry
81 //
82 typedef struct {
83 REGISTER_TYPE RegisterType; // offset 0 - 3
84 UINT32 Index; // offset 4 - 7
85 UINT8 ValidBitStart; // offset 8
86 UINT8 ValidBitLength; // offset 9
87 UINT16 Reserved; // offset 10 - 11
88 UINT32 HighIndex; // offset 12-15, only valid for MemoryMapped
89 UINT64 Value; // offset 16-23
90 } CPU_REGISTER_TABLE_ENTRY;
91
92 //
93 // Register table definition, including current table length,
94 // allocated size of this table, and pointer to the list of table entries.
95 //
96 typedef struct {
97 //
98 // The number of valid entries in the RegisterTableEntry buffer
99 //
100 UINT32 TableLength;
101 UINT32 NumberBeforeReset;
102 //
103 // The size, in bytes, of the RegisterTableEntry buffer
104 //
105 UINT32 AllocatedSize;
106 //
107 // The initial APIC ID of the CPU this register table applies to
108 //
109 UINT32 InitialApicId;
110 //
111 // Physical address of CPU_REGISTER_TABLE_ENTRY structures.
112 //
113 EFI_PHYSICAL_ADDRESS RegisterTableEntry;
114 } CPU_REGISTER_TABLE;
115
116 //
117 // Data structure that is required for ACPI S3 resume. The PCD
118 // PcdCpuS3DataAddress must be set to the physical address where this structure
119 // is allocated
120 //
121 typedef struct {
122 //
123 // Physical address of 4KB buffer allocated below 1MB from memory of type
124 // EfiReservedMemoryType. The buffer is not required to be initialized, but
125 // it is recommended that the buffer be zero-filled. This buffer is used to
126 // wake APs during an ACPI S3 resume.
127 //
128 EFI_PHYSICAL_ADDRESS StartupVector;
129 //
130 // Physical address of structure of type IA32_DESCRIPTOR. The
131 // IA32_DESCRIPTOR structure provides the base address and length of a GDT
132 // The GDT must be filled in with the GDT contents that are
133 // used during an ACPI S3 resume. This is typically the contents of the GDT
134 // used by the boot processor when the platform is booted.
135 //
136 EFI_PHYSICAL_ADDRESS GdtrProfile;
137 //
138 // Physical address of structure of type IA32_DESCRIPTOR. The
139 // IA32_DESCRIPTOR structure provides the base address and length of an IDT.
140 // The IDT must be filled in with the IDT contents that are
141 // used during an ACPI S3 resume. This is typically the contents of the IDT
142 // used by the boot processor when the platform is booted.
143 //
144 EFI_PHYSICAL_ADDRESS IdtrProfile;
145 //
146 // Physical address of a buffer that is used as stacks during ACPI S3 resume.
147 // The total size of this buffer, in bytes, is NumberOfCpus * StackSize. This
148 // structure must be allocated from memory of type EfiACPIMemoryNVS.
149 //
150 EFI_PHYSICAL_ADDRESS StackAddress;
151 //
152 // The size, in bytes, of the stack provided to each CPU during ACPI S3 resume.
153 //
154 UINT32 StackSize;
155 //
156 // The number of CPUs. If a platform does not support hot plug CPUs, then
157 // this is the number of CPUs detected when the platform is booted, regardless
158 // of being enabled or disabled. If a platform does support hot plug CPUs,
159 // then this is the maximum number of CPUs that the platform supports.
160 //
161 UINT32 NumberOfCpus;
162 //
163 // Physical address of structure of type MTRR_SETTINGS that contains a copy
164 // of the MTRR settings that are compatible with the MTRR settings used by
165 // the boot processor when the platform was booted. These MTRR settings are
166 // used during an ACPI S3 resume.
167 //
168 EFI_PHYSICAL_ADDRESS MtrrTable;
169 //
170 // Physical address of an array of CPU_REGISTER_TABLE structures, with
171 // NumberOfCpus entries. If a register table is not required, then the
172 // TableLength and AllocatedSize fields of CPU_REGISTER_TABLE are set to 0.
173 // If TableLength is > 0, then elements of RegisterTableEntry are used to
174 // initialize the CPU that matches InitialApicId, during an ACPI S3 resume,
175 // before SMBASE relocation is performed.
176 //
177 EFI_PHYSICAL_ADDRESS PreSmmInitRegisterTable;
178 //
179 // Physical address of an array of CPU_REGISTER_TABLE structures, with
180 // NumberOfCpus entries. If a register table is not required, then the
181 // TableLength and AllocatedSize fields of CPU_REGISTER_TABLE are set to 0.
182 // If TableLength is > 0, then elements of RegisterTableEntry are used to
183 // initialize the CPU that matches InitialApicId, during an ACPI S3 resume,
184 // after SMBASE relocation is performed.
185 //
186 EFI_PHYSICAL_ADDRESS RegisterTable;
187 //
188 // Physical address of a buffer that contains the machine check handler that
189 // is used during an ACPI S3 Resume. In order for this machine check
190 // handler to be active on an AP during an ACPI S3 resume, the machine check
191 // vector in the IDT provided by IdtrProfile must be initialized to transfer
192 // control to this physical address.
193 //
194 EFI_PHYSICAL_ADDRESS ApMachineCheckHandlerBase;
195 //
196 // The size, in bytes, of the machine check handler that is used during an
197 // ACPI S3 Resume. If this field is 0, then a machine check handler is not
198 // provided.
199 //
200 UINT32 ApMachineCheckHandlerSize;
201 //
202 // CPU information which is required when set the register table.
203 //
204 CPU_STATUS_INFORMATION CpuStatus;
205 //
206 // Location info for each AP.
207 // It points to an array which saves all APs location info.
208 // The array count is the AP count in this CPU.
209 //
210 // If the platform does not support MSR setting at S3 resume, and
211 // therefore it doesn't need the dependency semaphores, it should set
212 // this field to 0.
213 //
214 EFI_PHYSICAL_ADDRESS ApLocation;
215 } ACPI_CPU_DATA;
216
217 #endif