2 Public include file for Local APIC library.
4 Local APIC library assumes local APIC is enabled. It does not
5 handles cases where local APIC is disabled.
7 Copyright (c) 2010 - 2013, Intel Corporation. All rights reserved.<BR>
8 This program and the accompanying materials
9 are licensed and made available under the terms and conditions of the BSD License
10 which accompanies this distribution. The full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #ifndef __LOCAL_APIC_LIB_H__
19 #define __LOCAL_APIC_LIB_H__
21 #define LOCAL_APIC_MODE_XAPIC 0x1 ///< xAPIC mode.
22 #define LOCAL_APIC_MODE_X2APIC 0x2 ///< x2APIC mode.
25 Retrieve the base address of local APIC.
27 @return The base address of local APIC.
32 GetLocalApicBaseAddress (
37 Set the base address of local APIC.
39 If BaseAddress is not aligned on a 4KB boundary, then ASSERT().
41 @param[in] BaseAddress Local APIC base address to be set.
46 SetLocalApicBaseAddress (
51 Get the current local APIC mode.
53 If local APIC is disabled, then ASSERT.
55 @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.
56 @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.
65 Set the current local APIC mode.
67 If the specified local APIC mode is not valid, then ASSERT.
68 If the specified local APIC mode can't be set as current, then ASSERT.
70 @param ApicMode APIC mode to be set.
79 Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
81 In xAPIC mode, the initial local APIC ID may be different from current APIC ID.
82 In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
83 the 32-bit local APIC ID is returned as initial APIC ID.
85 @return 32-bit initial local APIC ID of the executing processor.
94 Get the local APIC ID of the executing processor.
96 @return 32-bit local APIC ID of the executing processor.
105 Get the value of the local APIC version register.
107 @return the value of the local APIC version register.
116 Send a Fixed IPI to a specified target processor.
118 This function returns after the IPI has been accepted by the target processor.
120 @param ApicId The local APIC ID of the target processor.
121 @param Vector The vector number of the interrupt being sent.
131 Send a Fixed IPI to all processors excluding self.
133 This function returns after the IPI has been accepted by the target processors.
135 @param Vector The vector number of the interrupt being sent.
139 SendFixedIpiAllExcludingSelf (
144 Send a SMI IPI to a specified target processor.
146 This function returns after the IPI has been accepted by the target processor.
148 @param ApicId Specify the local APIC ID of the target processor.
157 Send a SMI IPI to all processors excluding self.
159 This function returns after the IPI has been accepted by the target processors.
163 SendSmiIpiAllExcludingSelf (
168 Send an INIT IPI to a specified target processor.
170 This function returns after the IPI has been accepted by the target processor.
172 @param ApicId Specify the local APIC ID of the target processor.
181 Send an INIT IPI to all processors excluding self.
183 This function returns after the IPI has been accepted by the target processors.
187 SendInitIpiAllExcludingSelf (
192 Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
194 This function returns after the IPI has been accepted by the target processor.
196 if StartupRoutine >= 1M, then ASSERT.
197 if StartupRoutine is not multiple of 4K, then ASSERT.
199 @param ApicId Specify the local APIC ID of the target processor.
200 @param StartupRoutine Points to a start-up routine which is below 1M physical
201 address and 4K aligned.
207 IN UINT32 StartupRoutine
211 Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
213 This function returns after the IPI has been accepted by the target processors.
215 if StartupRoutine >= 1M, then ASSERT.
216 if StartupRoutine is not multiple of 4K, then ASSERT.
218 @param StartupRoutine Points to a start-up routine which is below 1M physical
219 address and 4K aligned.
223 SendInitSipiSipiAllExcludingSelf (
224 IN UINT32 StartupRoutine
228 Programming Virtual Wire Mode.
230 This function programs the local APIC for virtual wire mode following
231 the example described in chapter A.3 of the MP 1.4 spec.
233 IOxAPIC is not involved in this type of virtual wire mode.
237 ProgramVirtualWireMode (
242 Disable LINT0 & LINT1 interrupts.
244 This function sets the mask flag in the LVT LINT0 & LINT1 registers.
248 DisableLvtInterrupts (
253 Read the initial count value from the init-count register.
255 @return The initial count value read from the init-count register.
259 GetApicTimerInitCount (
264 Read the current count value from the current-count register.
266 @return The current count value read from the current-count register.
270 GetApicTimerCurrentCount (
275 Initialize the local APIC timer.
277 The local APIC timer is initialized and enabled.
279 @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
280 If it is 0, then use the current divide value in the DCR.
281 @param InitCount The initial count value.
282 @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
283 @param Vector The timer interrupt vector number.
287 InitializeApicTimer (
288 IN UINTN DivideValue
,
290 IN BOOLEAN PeriodicMode
,
295 Get the state of the local APIC timer.
297 @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
298 @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
299 @param Vector Return the timer interrupt vector number.
304 OUT UINTN
*DivideValue OPTIONAL
,
305 OUT BOOLEAN
*PeriodicMode OPTIONAL
,
306 OUT UINT8
*Vector OPTIONAL
310 Enable the local APIC timer interrupt.
314 EnableApicTimerInterrupt (
319 Disable the local APIC timer interrupt.
323 DisableApicTimerInterrupt (
328 Get the local APIC timer interrupt state.
330 @retval TRUE The local APIC timer interrupt is enabled.
331 @retval FALSE The local APIC timer interrupt is disabled.
335 GetApicTimerInterruptState (
340 Send EOI to the local APIC.
349 Get the 32-bit address that a device should use to send a Message Signaled
350 Interrupt (MSI) to the Local APIC of the currently executing processor.
352 @return 32-bit address used to send an MSI to the Local APIC.
361 Get the 64-bit data value that a device should use to send a Message Signaled
362 Interrupt (MSI) to the Local APIC of the currently executing processor.
364 If Vector is not in range 0x10..0xFE, then ASSERT().
365 If DeliveryMode is not supported, then ASSERT().
367 @param Vector The 8-bit interrupt vector associated with the MSI.
368 Must be in the range 0x10..0xFE
369 @param DeliveryMode A 3-bit value that specifies how the recept of the MSI
370 is handled. The only supported values are:
371 0: LOCAL_APIC_DELIVERY_MODE_FIXED
372 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
373 2: LOCAL_APIC_DELIVERY_MODE_SMI
374 4: LOCAL_APIC_DELIVERY_MODE_NMI
375 5: LOCAL_APIC_DELIVERY_MODE_INIT
376 7: LOCAL_APIC_DELIVERY_MODE_EXTINT
378 @param LevelTriggered TRUE specifies a level triggered interrupt.
379 FALSE specifies an edge triggered interrupt.
380 @param AssertionLevel Ignored if LevelTriggered is FALSE.
381 TRUE specifies a level triggered interrupt that active
382 when the interrupt line is asserted.
383 FALSE specifies a level triggered interrupt that active
384 when the interrupt line is deasserted.
386 @return 64-bit data value used to send an MSI to the Local APIC.
392 IN UINTN DeliveryMode
,
393 IN BOOLEAN LevelTriggered
,
394 IN BOOLEAN AssertionLevel