2 Architectural MSR Definitions.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-1.
24 #ifndef __ARCHITECTURAL_MSR_H__
25 #define __ARCHITECTURAL_MSR_H__
28 See Section 35.20, "MSRs in Pentium Processors.". Pentium Processor (05_01H).
30 @param ECX MSR_IA32_P5_MC_ADDR (0x00000000)
31 @param EAX Lower 32-bits of MSR value.
32 @param EDX Upper 32-bits of MSR value.
38 Msr = AsmReadMsr64 (MSR_IA32_P5_MC_ADDR);
39 AsmWriteMsr64 (MSR_IA32_P5_MC_ADDR, Msr);
41 @note MSR_IA32_P5_MC_ADDR is defined as IA32_P5_MC_ADDR in SDM.
43 #define MSR_IA32_P5_MC_ADDR 0x00000000
47 See Section 35.20, "MSRs in Pentium Processors.". DF_DM = 05_01H.
49 @param ECX MSR_IA32_P5_MC_TYPE (0x00000001)
50 @param EAX Lower 32-bits of MSR value.
51 @param EDX Upper 32-bits of MSR value.
57 Msr = AsmReadMsr64 (MSR_IA32_P5_MC_TYPE);
58 AsmWriteMsr64 (MSR_IA32_P5_MC_TYPE, Msr);
60 @note MSR_IA32_P5_MC_TYPE is defined as IA32_P5_MC_TYPE in SDM.
62 #define MSR_IA32_P5_MC_TYPE 0x00000001
66 See Section 8.10.5, "Monitor/Mwait Address Range Determination.". Introduced
67 at Display Family / Display Model 0F_03H.
69 @param ECX MSR_IA32_MONITOR_FILTER_SIZE (0x00000006)
70 @param EAX Lower 32-bits of MSR value.
71 @param EDX Upper 32-bits of MSR value.
77 Msr = AsmReadMsr64 (MSR_IA32_MONITOR_FILTER_SIZE);
78 AsmWriteMsr64 (MSR_IA32_MONITOR_FILTER_SIZE, Msr);
80 @note MSR_IA32_MONITOR_FILTER_SIZE is defined as IA32_MONITOR_FILTER_SIZE in SDM.
82 #define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006
86 See Section 17.14, "Time-Stamp Counter.". Introduced at Display Family /
89 @param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010)
90 @param EAX Lower 32-bits of MSR value.
91 @param EDX Upper 32-bits of MSR value.
97 Msr = AsmReadMsr64 (MSR_IA32_TIME_STAMP_COUNTER);
98 AsmWriteMsr64 (MSR_IA32_TIME_STAMP_COUNTER, Msr);
100 @note MSR_IA32_TIME_STAMP_COUNTER is defined as IA32_TIME_STAMP_COUNTER in SDM.
102 #define MSR_IA32_TIME_STAMP_COUNTER 0x00000010
106 Platform ID (RO) The operating system can use this MSR to determine "slot"
107 information for the processor and the proper microcode update to load.
108 Introduced at Display Family / Display Model 06_01H.
110 @param ECX MSR_IA32_PLATFORM_ID (0x00000017)
111 @param EAX Lower 32-bits of MSR value.
112 Described by the type MSR_IA32_PLATFORM_ID_REGISTER.
113 @param EDX Upper 32-bits of MSR value.
114 Described by the type MSR_IA32_PLATFORM_ID_REGISTER.
118 MSR_IA32_PLATFORM_ID_REGISTER Msr;
120 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);
122 @note MSR_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.
124 #define MSR_IA32_PLATFORM_ID 0x00000017
127 MSR information returned for MSR index #MSR_IA32_PLATFORM_ID
131 /// Individual bit fields
137 /// [Bits 52:50] Platform Id (RO) Contains information concerning the
138 /// intended platform for the processor.
141 /// 0 0 0 Processor Flag 0.
142 /// 0 0 1 Processor Flag 1
143 /// 0 1 0 Processor Flag 2
144 /// 0 1 1 Processor Flag 3
145 /// 1 0 0 Processor Flag 4
146 /// 1 0 1 Processor Flag 5
147 /// 1 1 0 Processor Flag 6
148 /// 1 1 1 Processor Flag 7
154 /// All bit fields as a 64-bit value
157 } MSR_IA32_PLATFORM_ID_REGISTER
;
163 @param ECX MSR_IA32_APIC_BASE (0x0000001B)
164 @param EAX Lower 32-bits of MSR value.
165 Described by the type MSR_IA32_APIC_BASE_REGISTER.
166 @param EDX Upper 32-bits of MSR value.
167 Described by the type MSR_IA32_APIC_BASE_REGISTER.
171 MSR_IA32_APIC_BASE_REGISTER Msr;
173 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
174 AsmWriteMsr64 (MSR_IA32_APIC_BASE, Msr.Uint64);
176 @note MSR_IA32_APIC_BASE is defined as IA32_APIC_BASE in SDM.
178 #define MSR_IA32_APIC_BASE 0x0000001B
181 MSR information returned for MSR index #MSR_IA32_APIC_BASE
185 /// Individual bit fields
190 /// [Bit 8] BSP flag (R/W).
195 /// [Bit 10] Enable x2APIC mode. Introduced at Display Family / Display
200 /// [Bit 11] APIC Global Enable (R/W).
204 /// [Bits 31:12] APIC Base (R/W).
208 /// [Bits 63:32] APIC Base (R/W).
210 UINT32 ApicBaseHi
:32;
213 /// All bit fields as a 64-bit value
216 } MSR_IA32_APIC_BASE_REGISTER
;
220 Control Features in Intel 64 Processor (R/W). If any one enumeration
221 condition for defined bit field holds.
223 @param ECX MSR_IA32_FEATURE_CONTROL (0x0000003A)
224 @param EAX Lower 32-bits of MSR value.
225 Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.
226 @param EDX Upper 32-bits of MSR value.
227 Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.
231 MSR_IA32_FEATURE_CONTROL_REGISTER Msr;
233 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL);
234 AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, Msr.Uint64);
236 @note MSR_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.
238 #define MSR_IA32_FEATURE_CONTROL 0x0000003A
241 MSR information returned for MSR index #MSR_IA32_FEATURE_CONTROL
245 /// Individual bit fields
249 /// [Bit 0] Lock bit (R/WO): (1 = locked). When set, locks this MSR from
250 /// being written, writes to this bit will result in GP(0). Note: Once the
251 /// Lock bit is set, the contents of this register cannot be modified.
252 /// Therefore the lock bit must be set after configuring support for Intel
253 /// Virtualization Technology and prior to transferring control to an
254 /// option ROM or the OS. Hence, once the Lock bit is set, the entire
255 /// IA32_FEATURE_CONTROL contents are preserved across RESET when PWRGOOD
256 /// is not deasserted. If any one enumeration condition for defined bit
257 /// field position greater than bit 0 holds.
261 /// [Bit 1] Enable VMX inside SMX operation (R/WL): This bit enables a
262 /// system executive to use VMX in conjunction with SMX to support
263 /// Intel(R) Trusted Execution Technology. BIOS must set this bit only
264 /// when the CPUID function 1 returns VMX feature flag and SMX feature
265 /// flag set (ECX bits 5 and 6 respectively). If CPUID.01H:ECX[5] = 1 &&
266 /// CPUID.01H:ECX[6] = 1.
268 UINT32 EnableVmxInsideSmx
:1;
270 /// [Bit 2] Enable VMX outside SMX operation (R/WL): This bit enables VMX
271 /// for system executive that do not require SMX. BIOS must set this bit
272 /// only when the CPUID function 1 returns VMX feature flag set (ECX bit
273 /// 5). If CPUID.01H:ECX[5] = 1.
275 UINT32 EnableVmxOutsideSmx
:1;
278 /// [Bits 14:8] SENTER Local Function Enables (R/WL): When set, each bit
279 /// in the field represents an enable control for a corresponding SENTER
280 /// function. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If
281 /// CPUID.01H:ECX[6] = 1.
283 UINT32 SenterLocalFunctionEnables
:7;
285 /// [Bit 15] SENTER Global Enable (R/WL): This bit must be set to enable
286 /// SENTER leaf functions. This bit is supported only if CPUID.1:ECX.[bit
287 /// 6] is set. If CPUID.01H:ECX[6] = 1.
289 UINT32 SenterGlobalEnable
:1;
292 /// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX
293 /// leaf functions. This bit is supported only if CPUID.1:ECX.[bit 6] is
294 /// set. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.
299 /// [Bit 20] LMCE On (R/WL): When set, system software can program the
300 /// MSRs associated with LMCE to configure delivery of some machine check
301 /// exceptions to a single logical processor. If IA32_MCG_CAP[27] = 1.
308 /// All bit fields as a 32-bit value
312 /// All bit fields as a 64-bit value
315 } MSR_IA32_FEATURE_CONTROL_REGISTER
;
319 Per Logical Processor TSC Adjust (R/Write to clear). If CPUID.(EAX=07H,
320 ECX=0H): EBX[1] = 1. THREAD_ADJUST: Local offset value of the IA32_TSC for
321 a logical processor. Reset value is Zero. A write to IA32_TSC will modify
322 the local offset in IA32_TSC_ADJUST and the content of IA32_TSC, but does
323 not affect the internal invariant TSC hardware.
325 @param ECX MSR_IA32_TSC_ADJUST (0x0000003B)
326 @param EAX Lower 32-bits of MSR value.
327 @param EDX Upper 32-bits of MSR value.
333 Msr = AsmReadMsr64 (MSR_IA32_TSC_ADJUST);
334 AsmWriteMsr64 (MSR_IA32_TSC_ADJUST, Msr);
336 @note MSR_IA32_TSC_ADJUST is defined as IA32_TSC_ADJUST in SDM.
338 #define MSR_IA32_TSC_ADJUST 0x0000003B
342 BIOS Update Trigger (W) Executing a WRMSR instruction to this MSR causes a
343 microcode update to be loaded into the processor. See Section 9.11.6,
344 "Microcode Update Loader." A processor may prevent writing to this MSR when
345 loading guest states on VM entries or saving guest states on VM exits.
346 Introduced at Display Family / Display Model 06_01H.
348 @param ECX MSR_IA32_BIOS_UPDT_TRIG (0x00000079)
349 @param EAX Lower 32-bits of MSR value.
350 @param EDX Upper 32-bits of MSR value.
357 AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, Msr);
359 @note MSR_IA32_BIOS_UPDT_TRIG is defined as IA32_BIOS_UPDT_TRIG in SDM.
361 #define MSR_IA32_BIOS_UPDT_TRIG 0x00000079
365 BIOS Update Signature (RO) Returns the microcode update signature following
366 the execution of CPUID.01H. A processor may prevent writing to this MSR when
367 loading guest states on VM entries or saving guest states on VM exits.
368 Introduced at Display Family / Display Model 06_01H.
370 @param ECX MSR_IA32_BIOS_SIGN_ID (0x0000008B)
371 @param EAX Lower 32-bits of MSR value.
372 Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.
373 @param EDX Upper 32-bits of MSR value.
374 Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.
378 MSR_IA32_BIOS_SIGN_ID_REGISTER Msr;
380 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID);
382 @note MSR_IA32_BIOS_SIGN_ID is defined as IA32_BIOS_SIGN_ID in SDM.
384 #define MSR_IA32_BIOS_SIGN_ID 0x0000008B
387 MSR information returned for MSR index #MSR_IA32_BIOS_SIGN_ID
391 /// Individual bit fields
396 /// [Bits 63:32] Microcode update signature. This field contains the
397 /// signature of the currently loaded microcode update when read following
398 /// the execution of the CPUID instruction, function 1. It is required
399 /// that this register field be pre-loaded with zero prior to executing
400 /// the CPUID, function 1. If the field remains equal to zero, then there
401 /// is no microcode update loaded. Another nonzero value will be the
404 UINT32 MicrocodeUpdateSignature
:32;
407 /// All bit fields as a 64-bit value
410 } MSR_IA32_BIOS_SIGN_ID_REGISTER
;
414 SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1. CPUID.01H: ECX[6] =
417 @param ECX MSR_IA32_SMM_MONITOR_CTL (0x0000009B)
418 @param EAX Lower 32-bits of MSR value.
419 Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.
420 @param EDX Upper 32-bits of MSR value.
421 Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.
425 MSR_IA32_SMM_MONITOR_CTL_REGISTER Msr;
427 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);
428 AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, Msr.Uint64);
430 @note MSR_IA32_SMM_MONITOR_CTL is defined as IA32_SMM_MONITOR_CTL in SDM.
432 #define MSR_IA32_SMM_MONITOR_CTL 0x0000009B
435 MSR information returned for MSR index #MSR_IA32_SMM_MONITOR_CTL
439 /// Individual bit fields
443 /// [Bit 0] Valid (R/W). The STM may be invoked using VMCALL only if this
444 /// bit is 1. Because VMCALL is used to activate the dual-monitor treatment
445 /// (see Section 34.15.6), the dual-monitor treatment cannot be activated
446 /// if the bit is 0. This bit is cleared when the logical processor is
452 /// [Bit 2] Determines whether executions of VMXOFF unblock SMIs under the
453 /// default treatment of SMIs and SMM. Executions of VMXOFF unblock SMIs
454 /// unless bit 2 is 1 (the value of bit 0 is irrelevant).
459 /// [Bits 31:12] MSEG Base (R/W).
465 /// All bit fields as a 32-bit value
469 /// All bit fields as a 64-bit value
472 } MSR_IA32_SMM_MONITOR_CTL_REGISTER
;
476 Base address of the logical processor's SMRAM image (RO, SMM only). If
479 @param ECX MSR_IA32_SMBASE (0x0000009E)
480 @param EAX Lower 32-bits of MSR value.
481 @param EDX Upper 32-bits of MSR value.
487 Msr = AsmReadMsr64 (MSR_IA32_SMBASE);
489 @note MSR_IA32_SMBASE is defined as IA32_SMBASE in SDM.
491 #define MSR_IA32_SMBASE 0x0000009E
495 General Performance Counters (R/W).
496 MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n.
498 @param ECX MSR_IA32_PMCn
499 @param EAX Lower 32-bits of MSR value.
500 @param EDX Upper 32-bits of MSR value.
506 Msr = AsmReadMsr64 (MSR_IA32_PMC0);
507 AsmWriteMsr64 (MSR_IA32_PMC0, Msr);
509 @note MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM.
510 MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM.
511 MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM.
512 MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM.
513 MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM.
514 MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM.
515 MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM.
516 MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.
519 #define MSR_IA32_PMC0 0x000000C1
520 #define MSR_IA32_PMC1 0x000000C2
521 #define MSR_IA32_PMC2 0x000000C3
522 #define MSR_IA32_PMC3 0x000000C4
523 #define MSR_IA32_PMC4 0x000000C5
524 #define MSR_IA32_PMC5 0x000000C6
525 #define MSR_IA32_PMC6 0x000000C7
526 #define MSR_IA32_PMC7 0x000000C8
531 TSC Frequency Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 1.
532 C0_MCNT: C0 TSC Frequency Clock Count Increments at fixed interval (relative
533 to TSC freq.) when the logical processor is in C0. Cleared upon overflow /
534 wrap-around of IA32_APERF.
536 @param ECX MSR_IA32_MPERF (0x000000E7)
537 @param EAX Lower 32-bits of MSR value.
538 @param EDX Upper 32-bits of MSR value.
544 Msr = AsmReadMsr64 (MSR_IA32_MPERF);
545 AsmWriteMsr64 (MSR_IA32_MPERF, Msr);
547 @note MSR_IA32_MPERF is defined as IA32_MPERF in SDM.
549 #define MSR_IA32_MPERF 0x000000E7
553 Actual Performance Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] =
554 1. C0_ACNT: C0 Actual Frequency Clock Count Accumulates core clock counts at
555 the coordinated clock frequency, when the logical processor is in C0.
556 Cleared upon overflow / wrap-around of IA32_MPERF.
558 @param ECX MSR_IA32_APERF (0x000000E8)
559 @param EAX Lower 32-bits of MSR value.
560 @param EDX Upper 32-bits of MSR value.
566 Msr = AsmReadMsr64 (MSR_IA32_APERF);
567 AsmWriteMsr64 (MSR_IA32_APERF, Msr);
569 @note MSR_IA32_APERF is defined as IA32_APERF in SDM.
571 #define MSR_IA32_APERF 0x000000E8
575 MTRR Capability (RO) Section 11.11.2.1, "IA32_MTRR_DEF_TYPE MSR.".
576 Introduced at Display Family / Display Model 06_01H.
578 @param ECX MSR_IA32_MTRRCAP (0x000000FE)
579 @param EAX Lower 32-bits of MSR value.
580 Described by the type MSR_IA32_MTRRCAP_REGISTER.
581 @param EDX Upper 32-bits of MSR value.
582 Described by the type MSR_IA32_MTRRCAP_REGISTER.
586 MSR_IA32_MTRRCAP_REGISTER Msr;
588 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);
590 @note MSR_IA32_MTRRCAP is defined as IA32_MTRRCAP in SDM.
592 #define MSR_IA32_MTRRCAP 0x000000FE
595 MSR information returned for MSR index #MSR_IA32_MTRRCAP
599 /// Individual bit fields
603 /// [Bits 7:0] VCNT: The number of variable memory type ranges in the
608 /// [Bit 8] Fixed range MTRRs are supported when set.
613 /// [Bit 10] WC Supported when set.
617 /// [Bit 11] SMRR Supported when set.
624 /// All bit fields as a 32-bit value
628 /// All bit fields as a 64-bit value
631 } MSR_IA32_MTRRCAP_REGISTER
;
635 SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
637 @param ECX MSR_IA32_SYSENTER_CS (0x00000174)
638 @param EAX Lower 32-bits of MSR value.
639 Described by the type MSR_IA32_SYSENTER_CS_REGISTER.
640 @param EDX Upper 32-bits of MSR value.
641 Described by the type MSR_IA32_SYSENTER_CS_REGISTER.
645 MSR_IA32_SYSENTER_CS_REGISTER Msr;
647 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SYSENTER_CS);
648 AsmWriteMsr64 (MSR_IA32_SYSENTER_CS, Msr.Uint64);
650 @note MSR_IA32_SYSENTER_CS is defined as IA32_SYSENTER_CS in SDM.
652 #define MSR_IA32_SYSENTER_CS 0x00000174
655 MSR information returned for MSR index #MSR_IA32_SYSENTER_CS
659 /// Individual bit fields
663 /// [Bits 15:0] CS Selector.
670 /// All bit fields as a 32-bit value
674 /// All bit fields as a 64-bit value
677 } MSR_IA32_SYSENTER_CS_REGISTER
;
681 SYSENTER_ESP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
683 @param ECX MSR_IA32_SYSENTER_ESP (0x00000175)
684 @param EAX Lower 32-bits of MSR value.
685 @param EDX Upper 32-bits of MSR value.
691 Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_ESP);
692 AsmWriteMsr64 (MSR_IA32_SYSENTER_ESP, Msr);
694 @note MSR_IA32_SYSENTER_ESP is defined as IA32_SYSENTER_ESP in SDM.
696 #define MSR_IA32_SYSENTER_ESP 0x00000175
700 SYSENTER_EIP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
702 @param ECX MSR_IA32_SYSENTER_EIP (0x00000176)
703 @param EAX Lower 32-bits of MSR value.
704 @param EDX Upper 32-bits of MSR value.
710 Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_EIP);
711 AsmWriteMsr64 (MSR_IA32_SYSENTER_EIP, Msr);
713 @note MSR_IA32_SYSENTER_EIP is defined as IA32_SYSENTER_EIP in SDM.
715 #define MSR_IA32_SYSENTER_EIP 0x00000176
719 Global Machine Check Capability (RO). Introduced at Display Family / Display
722 @param ECX MSR_IA32_MCG_CAP (0x00000179)
723 @param EAX Lower 32-bits of MSR value.
724 Described by the type MSR_IA32_MCG_CAP_REGISTER.
725 @param EDX Upper 32-bits of MSR value.
726 Described by the type MSR_IA32_MCG_CAP_REGISTER.
730 MSR_IA32_MCG_CAP_REGISTER Msr;
732 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
734 @note MSR_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.
736 #define MSR_IA32_MCG_CAP 0x00000179
739 MSR information returned for MSR index #MSR_IA32_MCG_CAP
743 /// Individual bit fields
747 /// [Bits 7:0] Count: Number of reporting banks.
751 /// [Bit 8] MCG_CTL_P: IA32_MCG_CTL is present if this bit is set.
755 /// [Bit 9] MCG_EXT_P: Extended machine check state registers are present
756 /// if this bit is set.
760 /// [Bit 10] MCP_CMCI_P: Support for corrected MC error event is present.
761 /// Introduced at Display Family / Display Model 06_01H.
765 /// [Bit 11] MCG_TES_P: Threshold-based error status register are present
766 /// if this bit is set.
771 /// [Bits 23:16] MCG_EXT_CNT: Number of extended machine check state
772 /// registers present.
774 UINT32 MCG_EXT_CNT
:8;
776 /// [Bit 24] MCG_SER_P: The processor supports software error recovery if
782 /// [Bit 26] MCG_ELOG_P: Indicates that the processor allows platform
783 /// firmware to be invoked when an error is detected so that it may
784 /// provide additional platform specific information in an ACPI format
785 /// "Generic Error Data Entry" that augments the data included in machine
786 /// check bank registers. Introduced at Display Family / Display Model
791 /// [Bit 27] MCG_LMCE_P: Indicates that the processor support extended
792 /// state in IA32_MCG_STATUS and associated MSR necessary to configure
793 /// Local Machine Check Exception (LMCE). Introduced at Display Family /
794 /// Display Model 06_3EH.
801 /// All bit fields as a 32-bit value
805 /// All bit fields as a 64-bit value
808 } MSR_IA32_MCG_CAP_REGISTER
;
812 Global Machine Check Status (R/W0). Introduced at Display Family / Display
815 @param ECX MSR_IA32_MCG_STATUS (0x0000017A)
816 @param EAX Lower 32-bits of MSR value.
817 Described by the type MSR_IA32_MCG_STATUS_REGISTER.
818 @param EDX Upper 32-bits of MSR value.
819 Described by the type MSR_IA32_MCG_STATUS_REGISTER.
823 MSR_IA32_MCG_STATUS_REGISTER Msr;
825 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS);
826 AsmWriteMsr64 (MSR_IA32_MCG_STATUS, Msr.Uint64);
828 @note MSR_IA32_MCG_STATUS is defined as IA32_MCG_STATUS in SDM.
830 #define MSR_IA32_MCG_STATUS 0x0000017A
833 MSR information returned for MSR index #MSR_IA32_MCG_STATUS
837 /// Individual bit fields
841 /// [Bit 0] RIPV. Restart IP valid. Introduced at Display Family / Display
846 /// [Bit 1] EIPV. Error IP valid. Introduced at Display Family / Display
851 /// [Bit 2] MCIP. Machine check in progress. Introduced at Display Family
852 /// / Display Model 06_01H.
856 /// [Bit 3] LMCE_S. If IA32_MCG_CAP.LMCE_P[2 7] =1.
863 /// All bit fields as a 32-bit value
867 /// All bit fields as a 64-bit value
870 } MSR_IA32_MCG_STATUS_REGISTER
;
874 Global Machine Check Control (R/W). If IA32_MCG_CAP.CTL_P[8] =1.
876 @param ECX MSR_IA32_MCG_CTL (0x0000017B)
877 @param EAX Lower 32-bits of MSR value.
878 @param EDX Upper 32-bits of MSR value.
884 Msr = AsmReadMsr64 (MSR_IA32_MCG_CTL);
885 AsmWriteMsr64 (MSR_IA32_MCG_CTL, Msr);
887 @note MSR_IA32_MCG_CTL is defined as IA32_MCG_CTL in SDM.
889 #define MSR_IA32_MCG_CTL 0x0000017B
893 Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n.
895 @param ECX MSR_IA32_PERFEVTSELn
896 @param EAX Lower 32-bits of MSR value.
897 Described by the type MSR_IA32_PERFEVTSEL_REGISTER.
898 @param EDX Upper 32-bits of MSR value.
899 Described by the type MSR_IA32_PERFEVTSEL_REGISTER.
903 MSR_IA32_PERFEVTSEL_REGISTER Msr;
905 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0);
906 AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64);
908 @note MSR_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.
909 MSR_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.
910 MSR_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.
911 MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.
914 #define MSR_IA32_PERFEVTSEL0 0x00000186
915 #define MSR_IA32_PERFEVTSEL1 0x00000187
916 #define MSR_IA32_PERFEVTSEL2 0x00000188
917 #define MSR_IA32_PERFEVTSEL3 0x00000189
921 MSR information returned for MSR indexes #MSR_IA32_PERFEVTSEL0 to
922 #MSR_IA32_PERFEVTSEL3
926 /// Individual bit fields
930 /// [Bits 7:0] Event Select: Selects a performance event logic unit.
932 UINT32 EventSelect
:8;
934 /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to
935 /// detect on the selected event logic.
939 /// [Bit 16] USR: Counts while in privilege level is not ring 0.
943 /// [Bit 17] OS: Counts while in privilege level is ring 0.
947 /// [Bit 18] Edge: Enables edge detection if set.
951 /// [Bit 19] PC: enables pin control.
955 /// [Bit 20] INT: enables interrupt on counter overflow.
959 /// [Bit 21] AnyThread: When set to 1, it enables counting the associated
960 /// event conditions occurring across all logical processors sharing a
961 /// processor core. When set to 0, the counter only increments the
962 /// associated event conditions occurring in the logical processor which
963 /// programmed the MSR.
967 /// [Bit 22] EN: enables the corresponding performance counter to commence
968 /// counting when this bit is set.
972 /// [Bit 23] INV: invert the CMASK.
976 /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding
977 /// performance counter increments each cycle if the event count is
978 /// greater than or equal to the CMASK.
984 /// All bit fields as a 32-bit value
988 /// All bit fields as a 64-bit value
991 } MSR_IA32_PERFEVTSEL_REGISTER
;
995 Current performance state(P-State) operating point (RO). Introduced at
996 Display Family / Display Model 0F_03H.
998 @param ECX MSR_IA32_PERF_STATUS (0x00000198)
999 @param EAX Lower 32-bits of MSR value.
1000 Described by the type MSR_IA32_PERF_STATUS_REGISTER.
1001 @param EDX Upper 32-bits of MSR value.
1002 Described by the type MSR_IA32_PERF_STATUS_REGISTER.
1004 <b>Example usage</b>
1006 MSR_IA32_PERF_STATUS_REGISTER Msr;
1008 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_STATUS);
1010 @note MSR_IA32_PERF_STATUS is defined as IA32_PERF_STATUS in SDM.
1012 #define MSR_IA32_PERF_STATUS 0x00000198
1015 MSR information returned for MSR index #MSR_IA32_PERF_STATUS
1019 /// Individual bit fields
1023 /// [Bits 15:0] Current performance State Value.
1026 UINT32 Reserved1
:16;
1027 UINT32 Reserved2
:32;
1030 /// All bit fields as a 32-bit value
1034 /// All bit fields as a 64-bit value
1037 } MSR_IA32_PERF_STATUS_REGISTER
;
1041 (R/W). Introduced at Display Family / Display Model 0F_03H.
1043 @param ECX MSR_IA32_PERF_CTL (0x00000199)
1044 @param EAX Lower 32-bits of MSR value.
1045 Described by the type MSR_IA32_PERF_CTL_REGISTER.
1046 @param EDX Upper 32-bits of MSR value.
1047 Described by the type MSR_IA32_PERF_CTL_REGISTER.
1049 <b>Example usage</b>
1051 MSR_IA32_PERF_CTL_REGISTER Msr;
1053 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CTL);
1054 AsmWriteMsr64 (MSR_IA32_PERF_CTL, Msr.Uint64);
1056 @note MSR_IA32_PERF_CTL is defined as IA32_PERF_CTL in SDM.
1058 #define MSR_IA32_PERF_CTL 0x00000199
1061 MSR information returned for MSR index #MSR_IA32_PERF_CTL
1065 /// Individual bit fields
1069 /// [Bits 15:0] Target performance State Value.
1071 UINT32 TargetState
:16;
1072 UINT32 Reserved1
:16;
1074 /// [Bit 32] IDA Engage. (R/W) When set to 1: disengages IDA. 06_0FH
1078 UINT32 Reserved2
:31;
1081 /// All bit fields as a 64-bit value
1084 } MSR_IA32_PERF_CTL_REGISTER
;
1088 Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled
1089 Clock Modulation.". Introduced at Display Family / Display Model 0F_0H.
1091 @param ECX MSR_IA32_CLOCK_MODULATION (0x0000019A)
1092 @param EAX Lower 32-bits of MSR value.
1093 Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.
1094 @param EDX Upper 32-bits of MSR value.
1095 Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.
1097 <b>Example usage</b>
1099 MSR_IA32_CLOCK_MODULATION_REGISTER Msr;
1101 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION);
1102 AsmWriteMsr64 (MSR_IA32_CLOCK_MODULATION, Msr.Uint64);
1104 @note MSR_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.
1106 #define MSR_IA32_CLOCK_MODULATION 0x0000019A
1109 MSR information returned for MSR index #MSR_IA32_CLOCK_MODULATION
1113 /// Individual bit fields
1117 /// [Bit 0] Extended On-Demand Clock Modulation Duty Cycle:. If
1118 /// CPUID.06H:EAX[5] = 1.
1120 UINT32 ExtendedOnDemandClockModulationDutyCycle
:1;
1122 /// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded
1123 /// values for target duty cycle modulation.
1125 UINT32 OnDemandClockModulationDutyCycle
:3;
1127 /// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation.
1129 UINT32 OnDemandClockModulationEnable
:1;
1130 UINT32 Reserved1
:27;
1131 UINT32 Reserved2
:32;
1134 /// All bit fields as a 32-bit value
1138 /// All bit fields as a 64-bit value
1141 } MSR_IA32_CLOCK_MODULATION_REGISTER
;
1145 Thermal Interrupt Control (R/W) Enables and disables the generation of an
1146 interrupt on temperature transitions detected with the processor's thermal
1147 sensors and thermal monitor. See Section 14.7.2, "Thermal Monitor.".
1148 Introduced at Display Family / Display Model 0F_0H.
1150 @param ECX MSR_IA32_THERM_INTERRUPT (0x0000019B)
1151 @param EAX Lower 32-bits of MSR value.
1152 Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.
1153 @param EDX Upper 32-bits of MSR value.
1154 Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.
1156 <b>Example usage</b>
1158 MSR_IA32_THERM_INTERRUPT_REGISTER Msr;
1160 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_INTERRUPT);
1161 AsmWriteMsr64 (MSR_IA32_THERM_INTERRUPT, Msr.Uint64);
1163 @note MSR_IA32_THERM_INTERRUPT is defined as IA32_THERM_INTERRUPT in SDM.
1165 #define MSR_IA32_THERM_INTERRUPT 0x0000019B
1168 MSR information returned for MSR index #MSR_IA32_THERM_INTERRUPT
1172 /// Individual bit fields
1176 /// [Bit 0] High-Temperature Interrupt Enable.
1178 UINT32 HighTempEnable
:1;
1180 /// [Bit 1] Low-Temperature Interrupt Enable.
1182 UINT32 LowTempEnable
:1;
1184 /// [Bit 2] PROCHOT# Interrupt Enable.
1186 UINT32 PROCHOT_Enable
:1;
1188 /// [Bit 3] FORCEPR# Interrupt Enable.
1190 UINT32 FORCEPR_Enable
:1;
1192 /// [Bit 4] Critical Temperature Interrupt Enable.
1194 UINT32 CriticalTempEnable
:1;
1197 /// [Bits 14:8] Threshold #1 Value.
1199 UINT32 Threshold1
:7;
1201 /// [Bit 15] Threshold #1 Interrupt Enable.
1203 UINT32 Threshold1Enable
:1;
1205 /// [Bits 22:16] Threshold #2 Value.
1207 UINT32 Threshold2
:7;
1209 /// [Bit 23] Threshold #2 Interrupt Enable.
1211 UINT32 Threshold2Enable
:1;
1213 /// [Bit 24] Power Limit Notification Enable. If CPUID.06H:EAX[4] = 1.
1215 UINT32 PowerLimitNotificationEnable
:1;
1217 UINT32 Reserved3
:32;
1220 /// All bit fields as a 32-bit value
1224 /// All bit fields as a 64-bit value
1227 } MSR_IA32_THERM_INTERRUPT_REGISTER
;
1231 Thermal Status Information (RO) Contains status information about the
1232 processor's thermal sensor and automatic thermal monitoring facilities. See
1233 Section 14.7.2, "Thermal Monitor". Introduced at Display Family / Display
1236 @param ECX MSR_IA32_THERM_STATUS (0x0000019C)
1237 @param EAX Lower 32-bits of MSR value.
1238 Described by the type MSR_IA32_THERM_STATUS_REGISTER.
1239 @param EDX Upper 32-bits of MSR value.
1240 Described by the type MSR_IA32_THERM_STATUS_REGISTER.
1242 <b>Example usage</b>
1244 MSR_IA32_THERM_STATUS_REGISTER Msr;
1246 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_STATUS);
1248 @note MSR_IA32_THERM_STATUS is defined as IA32_THERM_STATUS in SDM.
1250 #define MSR_IA32_THERM_STATUS 0x0000019C
1253 MSR information returned for MSR index #MSR_IA32_THERM_STATUS
1257 /// Individual bit fields
1261 /// [Bit 0] Thermal Status (RO):.
1263 UINT32 ThermalStatus
:1;
1265 /// [Bit 1] Thermal Status Log (R/W):.
1267 UINT32 ThermalStatusLog
:1;
1269 /// [Bit 2] PROCHOT # or FORCEPR# event (RO).
1271 UINT32 PROCHOT_FORCEPR_Event
:1;
1273 /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0).
1275 UINT32 PROCHOT_FORCEPR_Log
:1;
1277 /// [Bit 4] Critical Temperature Status (RO).
1279 UINT32 CriticalTempStatus
:1;
1281 /// [Bit 5] Critical Temperature Status log (R/WC0).
1283 UINT32 CriticalTempStatusLog
:1;
1285 /// [Bit 6] Thermal Threshold #1 Status (RO). If CPUID.01H:ECX[8] = 1.
1287 UINT32 ThermalThreshold1Status
:1;
1289 /// [Bit 7] Thermal Threshold #1 log (R/WC0). If CPUID.01H:ECX[8] = 1.
1291 UINT32 ThermalThreshold1Log
:1;
1293 /// [Bit 8] Thermal Threshold #2 Status (RO). If CPUID.01H:ECX[8] = 1.
1295 UINT32 ThermalThreshold2Status
:1;
1297 /// [Bit 9] Thermal Threshold #2 log (R/WC0). If CPUID.01H:ECX[8] = 1.
1299 UINT32 ThermalThreshold2Log
:1;
1301 /// [Bit 10] Power Limitation Status (RO). If CPUID.06H:EAX[4] = 1.
1303 UINT32 PowerLimitStatus
:1;
1305 /// [Bit 11] Power Limitation log (R/WC0). If CPUID.06H:EAX[4] = 1.
1307 UINT32 PowerLimitLog
:1;
1309 /// [Bit 12] Current Limit Status (RO). If CPUID.06H:EAX[7] = 1.
1311 UINT32 CurrentLimitStatus
:1;
1313 /// [Bit 13] Current Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.
1315 UINT32 CurrentLimitLog
:1;
1317 /// [Bit 14] Cross Domain Limit Status (RO). If CPUID.06H:EAX[7] = 1.
1319 UINT32 CrossDomainLimitStatus
:1;
1321 /// [Bit 15] Cross Domain Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.
1323 UINT32 CrossDomainLimitLog
:1;
1325 /// [Bits 22:16] Digital Readout (RO). If CPUID.06H:EAX[0] = 1.
1327 UINT32 DigitalReadout
:7;
1330 /// [Bits 30:27] Resolution in Degrees Celsius (RO). If CPUID.06H:EAX[0] =
1333 UINT32 ResolutionInDegreesCelsius
:4;
1335 /// [Bit 31] Reading Valid (RO). If CPUID.06H:EAX[0] = 1.
1337 UINT32 ReadingValid
:1;
1338 UINT32 Reserved2
:32;
1341 /// All bit fields as a 32-bit value
1345 /// All bit fields as a 64-bit value
1348 } MSR_IA32_THERM_STATUS_REGISTER
;
1352 Enable Misc. Processor Features (R/W) Allows a variety of processor
1353 functions to be enabled and disabled.
1355 @param ECX MSR_IA32_MISC_ENABLE (0x000001A0)
1356 @param EAX Lower 32-bits of MSR value.
1357 Described by the type MSR_IA32_MISC_ENABLE_REGISTER.
1358 @param EDX Upper 32-bits of MSR value.
1359 Described by the type MSR_IA32_MISC_ENABLE_REGISTER.
1361 <b>Example usage</b>
1363 MSR_IA32_MISC_ENABLE_REGISTER Msr;
1365 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);
1366 AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, Msr.Uint64);
1368 @note MSR_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
1370 #define MSR_IA32_MISC_ENABLE 0x000001A0
1373 MSR information returned for MSR index #MSR_IA32_MISC_ENABLE
1377 /// Individual bit fields
1381 /// [Bit 0] Fast-Strings Enable When set, the fast-strings feature (for
1382 /// REP MOVS and REP STORS) is enabled (default); when clear, fast-strings
1383 /// are disabled. Introduced at Display Family / Display Model 0F_0H.
1385 UINT32 FastStrings
:1;
1388 /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting
1389 /// this bit enables the thermal control circuit (TCC) portion of the
1390 /// Intel Thermal Monitor feature. This allows the processor to
1391 /// automatically reduce power consumption in response to TCC activation.
1392 /// 0 = Disabled. Note: In some products clearing this bit might be
1393 /// ignored in critical thermal conditions, and TM1, TM2 and adaptive
1394 /// thermal throttling will still be activated. Introduced at Display
1395 /// Family / Display Model 0F_0H.
1397 UINT32 AutomaticThermalControlCircuit
:1;
1400 /// [Bit 7] Performance Monitoring Available (R) 1 = Performance
1401 /// monitoring enabled 0 = Performance monitoring disabled. Introduced at
1402 /// Display Family / Display Model 0F_0H.
1404 UINT32 PerformanceMonitoring
:1;
1407 /// [Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't
1408 /// support branch trace storage (BTS) 0 = BTS is supported. Introduced at
1409 /// Display Family / Display Model 0F_0H.
1413 /// [Bit 12] Precise Event Based Sampling (PEBS) Unavailable (RO) 1 =
1414 /// PEBS is not supported; 0 = PEBS is supported. Introduced at Display
1415 /// Family / Display Model 06_0FH.
1420 /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 0= Enhanced
1421 /// Intel SpeedStep Technology disabled 1 = Enhanced Intel SpeedStep
1422 /// Technology enabled. If CPUID.01H: ECX[7] =1.
1427 /// [Bit 18] ENABLE MONITOR FSM (R/W) When this bit is set to 0, the
1428 /// MONITOR feature flag is not set (CPUID.01H:ECX[bit 3] = 0). This
1429 /// indicates that MONITOR/MWAIT are not supported. Software attempts to
1430 /// execute MONITOR/MWAIT will cause #UD when this bit is 0. When this bit
1431 /// is set to 1 (default), MONITOR/MWAIT are supported (CPUID.01H:ECX[bit
1432 /// 3] = 1). If the SSE3 feature flag ECX[0] is not set (CPUID.01H:ECX[bit
1433 /// 0] = 0), the OS must not attempt to alter this bit. BIOS must leave it
1434 /// in the default state. Writing this bit when the SSE3 feature flag is
1435 /// set to 0 may generate a #GP exception. Introduced at Display Family /
1436 /// Display Model 0F_03H.
1441 /// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H
1442 /// returns a maximum value in EAX[7:0] of 3. BIOS should contain a setup
1443 /// question that allows users to specify when the installed OS does not
1444 /// support CPUID functions greater than 3. Before setting this bit, BIOS
1445 /// must execute the CPUID.0H and examine the maximum value returned in
1446 /// EAX[7:0]. If the maximum value is greater than 3, the bit is
1447 /// supported. Otherwise, the bit is not supported. Writing to this bit
1448 /// when the maximum value is greater than 3 may generate a #GP exception.
1449 /// Setting this bit may cause unexpected behavior in software that
1450 /// depends on the availability of CPUID leaves greater than 3. Introduced
1451 /// at Display Family / Display Model 0F_03H.
1453 UINT32 LimitCpuidMaxval
:1;
1455 /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are
1456 /// disabled. xTPR messages are optional messages that allow the processor
1457 /// to inform the chipset of its priority. if CPUID.01H:ECX[14] = 1.
1459 UINT32 xTPR_Message_Disable
:1;
1463 /// [Bit 34] XD Bit Disable (R/W) When set to 1, the Execute Disable Bit
1464 /// feature (XD Bit) is disabled and the XD Bit extended feature flag will
1465 /// be clear (CPUID.80000001H: EDX[20]=0). When set to a 0 (default), the
1466 /// Execute Disable Bit feature (if available) allows the OS to enable PAE
1467 /// paging and take advantage of data only pages. BIOS must not alter the
1468 /// contents of this bit location, if XD bit is not supported. Writing
1469 /// this bit to 1 when the XD Bit extended feature flag is set to 0 may
1470 /// generate a #GP exception. if CPUID.80000001H:EDX[2 0] = 1.
1473 UINT32 Reserved9
:29;
1476 /// All bit fields as a 64-bit value
1479 } MSR_IA32_MISC_ENABLE_REGISTER
;
1483 Performance Energy Bias Hint (R/W). if CPUID.6H:ECX[3] = 1.
1485 @param ECX MSR_IA32_ENERGY_PERF_BIAS (0x000001B0)
1486 @param EAX Lower 32-bits of MSR value.
1487 Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.
1488 @param EDX Upper 32-bits of MSR value.
1489 Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.
1491 <b>Example usage</b>
1493 MSR_IA32_ENERGY_PERF_BIAS_REGISTER Msr;
1495 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_ENERGY_PERF_BIAS);
1496 AsmWriteMsr64 (MSR_IA32_ENERGY_PERF_BIAS, Msr.Uint64);
1498 @note MSR_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.
1500 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0
1503 MSR information returned for MSR index #MSR_IA32_ENERGY_PERF_BIAS
1507 /// Individual bit fields
1511 /// [Bits 3:0] Power Policy Preference: 0 indicates preference to highest
1512 /// performance. 15 indicates preference to maximize energy saving.
1514 UINT32 PowerPolicyPreference
:4;
1515 UINT32 Reserved1
:28;
1516 UINT32 Reserved2
:32;
1519 /// All bit fields as a 32-bit value
1523 /// All bit fields as a 64-bit value
1526 } MSR_IA32_ENERGY_PERF_BIAS_REGISTER
;
1530 Package Thermal Status Information (RO) Contains status information about
1531 the package's thermal sensor. See Section 14.8, "Package Level Thermal
1532 Management.". If CPUID.06H: EAX[6] = 1.
1534 @param ECX MSR_IA32_PACKAGE_THERM_STATUS (0x000001B1)
1535 @param EAX Lower 32-bits of MSR value.
1536 Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.
1537 @param EDX Upper 32-bits of MSR value.
1538 Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.
1540 <b>Example usage</b>
1542 MSR_IA32_PACKAGE_THERM_STATUS_REGISTER Msr;
1544 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_STATUS);
1546 @note MSR_IA32_PACKAGE_THERM_STATUS is defined as IA32_PACKAGE_THERM_STATUS in SDM.
1548 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1
1551 MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_STATUS
1555 /// Individual bit fields
1559 /// [Bit 0] Pkg Thermal Status (RO):.
1561 UINT32 ThermalStatus
:1;
1563 /// [Bit 1] Pkg Thermal Status Log (R/W):.
1565 UINT32 ThermalStatusLog
:1;
1567 /// [Bit 2] Pkg PROCHOT # event (RO).
1569 UINT32 PROCHOT_Event
:1;
1571 /// [Bit 3] Pkg PROCHOT # log (R/WC0).
1573 UINT32 PROCHOT_Log
:1;
1575 /// [Bit 4] Pkg Critical Temperature Status (RO).
1577 UINT32 CriticalTempStatus
:1;
1579 /// [Bit 5] Pkg Critical Temperature Status log (R/WC0).
1581 UINT32 CriticalTempStatusLog
:1;
1583 /// [Bit 6] Pkg Thermal Threshold #1 Status (RO).
1585 UINT32 ThermalThreshold1Status
:1;
1587 /// [Bit 7] Pkg Thermal Threshold #1 log (R/WC0).
1589 UINT32 ThermalThreshold1Log
:1;
1591 /// [Bit 8] Pkg Thermal Threshold #2 Status (RO).
1593 UINT32 ThermalThreshold2Status
:1;
1595 /// [Bit 9] Pkg Thermal Threshold #1 log (R/WC0).
1597 UINT32 ThermalThreshold2Log
:1;
1599 /// [Bit 10] Pkg Power Limitation Status (RO).
1601 UINT32 PowerLimitStatus
:1;
1603 /// [Bit 11] Pkg Power Limitation log (R/WC0).
1605 UINT32 PowerLimitLog
:1;
1608 /// [Bits 22:16] Pkg Digital Readout (RO).
1610 UINT32 DigitalReadout
:7;
1612 UINT32 Reserved3
:32;
1615 /// All bit fields as a 32-bit value
1619 /// All bit fields as a 64-bit value
1622 } MSR_IA32_PACKAGE_THERM_STATUS_REGISTER
;
1626 Pkg Thermal Interrupt Control (R/W) Enables and disables the generation of
1627 an interrupt on temperature transitions detected with the package's thermal
1628 sensor. See Section 14.8, "Package Level Thermal Management.". If CPUID.06H:
1631 @param ECX MSR_IA32_PACKAGE_THERM_INTERRUPT (0x000001B2)
1632 @param EAX Lower 32-bits of MSR value.
1633 Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.
1634 @param EDX Upper 32-bits of MSR value.
1635 Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.
1637 <b>Example usage</b>
1639 MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER Msr;
1641 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT);
1642 AsmWriteMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT, Msr.Uint64);
1644 @note MSR_IA32_PACKAGE_THERM_INTERRUPT is defined as IA32_PACKAGE_THERM_INTERRUPT in SDM.
1646 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2
1649 MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_INTERRUPT
1653 /// Individual bit fields
1657 /// [Bit 0] Pkg High-Temperature Interrupt Enable.
1659 UINT32 HighTempEnable
:1;
1661 /// [Bit 1] Pkg Low-Temperature Interrupt Enable.
1663 UINT32 LowTempEnable
:1;
1665 /// [Bit 2] Pkg PROCHOT# Interrupt Enable.
1667 UINT32 PROCHOT_Enable
:1;
1670 /// [Bit 4] Pkg Overheat Interrupt Enable.
1672 UINT32 OverheatEnable
:1;
1675 /// [Bits 14:8] Pkg Threshold #1 Value.
1677 UINT32 Threshold1
:7;
1679 /// [Bit 15] Pkg Threshold #1 Interrupt Enable.
1681 UINT32 Threshold1Enable
:1;
1683 /// [Bits 22:16] Pkg Threshold #2 Value.
1685 UINT32 Threshold2
:7;
1687 /// [Bit 23] Pkg Threshold #2 Interrupt Enable.
1689 UINT32 Threshold2Enable
:1;
1691 /// [Bit 24] Pkg Power Limit Notification Enable.
1693 UINT32 PowerLimitNotificationEnable
:1;
1695 UINT32 Reserved4
:32;
1698 /// All bit fields as a 32-bit value
1702 /// All bit fields as a 64-bit value
1705 } MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER
;
1709 Trace/Profile Resource Control (R/W). Introduced at Display Family / Display
1712 @param ECX MSR_IA32_DEBUGCTL (0x000001D9)
1713 @param EAX Lower 32-bits of MSR value.
1714 Described by the type MSR_IA32_DEBUGCTL_REGISTER.
1715 @param EDX Upper 32-bits of MSR value.
1716 Described by the type MSR_IA32_DEBUGCTL_REGISTER.
1718 <b>Example usage</b>
1720 MSR_IA32_DEBUGCTL_REGISTER Msr;
1722 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUGCTL);
1723 AsmWriteMsr64 (MSR_IA32_DEBUGCTL, Msr.Uint64);
1725 @note MSR_IA32_DEBUGCTL is defined as IA32_DEBUGCTL in SDM.
1727 #define MSR_IA32_DEBUGCTL 0x000001D9
1730 MSR information returned for MSR index #MSR_IA32_DEBUGCTL
1734 /// Individual bit fields
1738 /// [Bit 0] LBR: Setting this bit to 1 enables the processor to record a
1739 /// running trace of the most recent branches taken by the processor in
1740 /// the LBR stack. Introduced at Display Family / Display Model 06_01H.
1744 /// [Bit 1] BTF: Setting this bit to 1 enables the processor to treat
1745 /// EFLAGS.TF as single-step on branches instead of single-step on
1746 /// instructions. Introduced at Display Family / Display Model 06_01H.
1751 /// [Bit 6] TR: Setting this bit to 1 enables branch trace messages to be
1752 /// sent. Introduced at Display Family / Display Model 06_0EH.
1756 /// [Bit 7] BTS: Setting this bit enables branch trace messages (BTMs) to
1757 /// be logged in a BTS buffer. Introduced at Display Family / Display
1762 /// [Bit 8] BTINT: When clear, BTMs are logged in a BTS buffer in circular
1763 /// fashion. When this bit is set, an interrupt is generated by the BTS
1764 /// facility when the BTS buffer is full. Introduced at Display Family /
1765 /// Display Model 06_0EH.
1769 /// [Bit 9] BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0.
1770 /// Introduced at Display Family / Display Model 06_0FH.
1772 UINT32 BTS_OFF_OS
:1;
1774 /// [Bit 10] BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0.
1775 /// Introduced at Display Family / Display Model 06_0FH.
1777 UINT32 BTS_OFF_USR
:1;
1779 /// [Bit 11] FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a
1780 /// PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.
1782 UINT32 FREEZE_LBRS_ON_PMI
:1;
1784 /// [Bit 12] FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the
1785 /// global counter control MSR are frozen (address 38FH) on a PMI request.
1786 /// If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.
1788 UINT32 FREEZE_PERFMON_ON_PMI
:1;
1790 /// [Bit 13] ENABLE_UNCORE_PMI: When set, enables the logical processor to
1791 /// receive and generate PMI on behalf of the uncore. Introduced at
1792 /// Display Family / Display Model 06_1AH.
1794 UINT32 ENABLE_UNCORE_PMI
:1;
1796 /// [Bit 14] FREEZE_WHILE_SMM: When set, freezes perfmon and trace
1797 /// messages while in SMM. If IA32_PERF_CAPABILITIES[ 12] = 1.
1799 UINT32 FREEZE_WHILE_SMM
:1;
1801 /// [Bit 15] RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If
1802 /// (CPUID.(EAX=07H, ECX=0):EBX[11] = 1).
1805 UINT32 Reserved2
:16;
1806 UINT32 Reserved3
:32;
1809 /// All bit fields as a 32-bit value
1813 /// All bit fields as a 64-bit value
1816 } MSR_IA32_DEBUGCTL_REGISTER
;
1820 SMRR Base Address (Writeable only in SMM) Base address of SMM memory range.
1821 If IA32_MTRRCAP.SMRR[11] = 1.
1823 @param ECX MSR_IA32_SMRR_PHYSBASE (0x000001F2)
1824 @param EAX Lower 32-bits of MSR value.
1825 Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.
1826 @param EDX Upper 32-bits of MSR value.
1827 Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.
1829 <b>Example usage</b>
1831 MSR_IA32_SMRR_PHYSBASE_REGISTER Msr;
1833 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSBASE);
1834 AsmWriteMsr64 (MSR_IA32_SMRR_PHYSBASE, Msr.Uint64);
1836 @note MSR_IA32_SMRR_PHYSBASE is defined as IA32_SMRR_PHYSBASE in SDM.
1838 #define MSR_IA32_SMRR_PHYSBASE 0x000001F2
1841 MSR information returned for MSR index #MSR_IA32_SMRR_PHYSBASE
1845 /// Individual bit fields
1849 /// [Bits 7:0] Type. Specifies memory type of the range.
1854 /// [Bits 31:12] PhysBase. SMRR physical Base Address.
1857 UINT32 Reserved2
:32;
1860 /// All bit fields as a 32-bit value
1864 /// All bit fields as a 64-bit value
1867 } MSR_IA32_SMRR_PHYSBASE_REGISTER
;
1871 SMRR Range Mask. (Writeable only in SMM) Range Mask of SMM memory range. If
1872 IA32_MTRRCAP[SMRR] = 1.
1874 @param ECX MSR_IA32_SMRR_PHYSMASK (0x000001F3)
1875 @param EAX Lower 32-bits of MSR value.
1876 Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.
1877 @param EDX Upper 32-bits of MSR value.
1878 Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.
1880 <b>Example usage</b>
1882 MSR_IA32_SMRR_PHYSMASK_REGISTER Msr;
1884 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSMASK);
1885 AsmWriteMsr64 (MSR_IA32_SMRR_PHYSMASK, Msr.Uint64);
1887 @note MSR_IA32_SMRR_PHYSMASK is defined as IA32_SMRR_PHYSMASK in SDM.
1889 #define MSR_IA32_SMRR_PHYSMASK 0x000001F3
1892 MSR information returned for MSR index #MSR_IA32_SMRR_PHYSMASK
1896 /// Individual bit fields
1899 UINT32 Reserved1
:11;
1901 /// [Bit 11] Valid Enable range mask.
1905 /// [Bits 31:12] PhysMask SMRR address range mask.
1908 UINT32 Reserved2
:32;
1911 /// All bit fields as a 32-bit value
1915 /// All bit fields as a 64-bit value
1918 } MSR_IA32_SMRR_PHYSMASK_REGISTER
;
1922 DCA Capability (R). If CPUID.01H: ECX[18] = 1.
1924 @param ECX MSR_IA32_PLATFORM_DCA_CAP (0x000001F8)
1925 @param EAX Lower 32-bits of MSR value.
1926 @param EDX Upper 32-bits of MSR value.
1928 <b>Example usage</b>
1932 Msr = AsmReadMsr64 (MSR_IA32_PLATFORM_DCA_CAP);
1934 @note MSR_IA32_PLATFORM_DCA_CAP is defined as IA32_PLATFORM_DCA_CAP in SDM.
1936 #define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8
1940 If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1.
1942 @param ECX MSR_IA32_CPU_DCA_CAP (0x000001F9)
1943 @param EAX Lower 32-bits of MSR value.
1944 @param EDX Upper 32-bits of MSR value.
1946 <b>Example usage</b>
1950 Msr = AsmReadMsr64 (MSR_IA32_CPU_DCA_CAP);
1951 AsmWriteMsr64 (MSR_IA32_CPU_DCA_CAP, Msr);
1953 @note MSR_IA32_CPU_DCA_CAP is defined as IA32_CPU_DCA_CAP in SDM.
1955 #define MSR_IA32_CPU_DCA_CAP 0x000001F9
1959 DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1.
1961 @param ECX MSR_IA32_DCA_0_CAP (0x000001FA)
1962 @param EAX Lower 32-bits of MSR value.
1963 Described by the type MSR_IA32_DCA_0_CAP_REGISTER.
1964 @param EDX Upper 32-bits of MSR value.
1965 Described by the type MSR_IA32_DCA_0_CAP_REGISTER.
1967 <b>Example usage</b>
1969 MSR_IA32_DCA_0_CAP_REGISTER Msr;
1971 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DCA_0_CAP);
1972 AsmWriteMsr64 (MSR_IA32_DCA_0_CAP, Msr.Uint64);
1974 @note MSR_IA32_DCA_0_CAP is defined as IA32_DCA_0_CAP in SDM.
1976 #define MSR_IA32_DCA_0_CAP 0x000001FA
1979 MSR information returned for MSR index #MSR_IA32_DCA_0_CAP
1983 /// Individual bit fields
1987 /// [Bit 0] DCA_ACTIVE: Set by HW when DCA is fuseenabled and no
1988 /// defeatures are set.
1990 UINT32 DCA_ACTIVE
:1;
1992 /// [Bits 2:1] TRANSACTION.
1994 UINT32 TRANSACTION
:2;
1996 /// [Bits 6:3] DCA_TYPE.
2000 /// [Bits 10:7] DCA_QUEUE_SIZE.
2002 UINT32 DCA_QUEUE_SIZE
:4;
2005 /// [Bits 16:13] DCA_DELAY: Writes will update the register but have no HW
2011 /// [Bit 24] SW_BLOCK: SW can request DCA block by setting this bit.
2016 /// [Bit 26] HW_BLOCK: Set when DCA is blocked by HW (e.g. CR0.CD = 1).
2020 UINT32 Reserved5
:32;
2023 /// All bit fields as a 32-bit value
2027 /// All bit fields as a 64-bit value
2030 } MSR_IA32_DCA_0_CAP_REGISTER
;
2034 MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs".
2035 If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.
2037 @param ECX MSR_IA32_MTRR_PHYSBASEn
2038 @param EAX Lower 32-bits of MSR value.
2039 Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.
2040 @param EDX Upper 32-bits of MSR value.
2041 Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.
2043 <b>Example usage</b>
2045 MSR_IA32_MTRR_PHYSBASE_REGISTER Msr;
2047 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);
2048 AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);
2050 @note MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM.
2051 MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM.
2052 MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM.
2053 MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM.
2054 MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM.
2055 MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM.
2056 MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM.
2057 MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM.
2058 MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM.
2059 MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.
2062 #define MSR_IA32_MTRR_PHYSBASE0 0x00000200
2063 #define MSR_IA32_MTRR_PHYSBASE1 0x00000202
2064 #define MSR_IA32_MTRR_PHYSBASE2 0x00000204
2065 #define MSR_IA32_MTRR_PHYSBASE3 0x00000206
2066 #define MSR_IA32_MTRR_PHYSBASE4 0x00000208
2067 #define MSR_IA32_MTRR_PHYSBASE5 0x0000020A
2068 #define MSR_IA32_MTRR_PHYSBASE6 0x0000020C
2069 #define MSR_IA32_MTRR_PHYSBASE7 0x0000020E
2070 #define MSR_IA32_MTRR_PHYSBASE8 0x00000210
2071 #define MSR_IA32_MTRR_PHYSBASE9 0x00000212
2075 MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSBASE0 to
2076 #MSR_IA32_MTRR_PHYSBASE9
2080 /// Individual bit fields
2084 /// [Bits 7:0] Type. Specifies memory type of the range.
2089 /// [Bits 31:12] PhysBase. MTRR physical Base Address.
2093 /// [Bits MAXPHYSADDR:32] PhysBase. Upper bits of MTRR physical Base Address.
2094 /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the
2095 /// maximum physical address range supported by the processor. It is
2096 /// reported by CPUID leaf function 80000008H. If CPUID does not support
2097 /// leaf 80000008H, the processor supports 36-bit physical address size,
2098 /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.
2100 UINT32 PhysBaseHi
:32;
2103 /// All bit fields as a 64-bit value
2106 } MSR_IA32_MTRR_PHYSBASE_REGISTER
;
2110 MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs".
2111 If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.
2113 @param ECX MSR_IA32_MTRR_PHYSMASKn
2114 @param EAX Lower 32-bits of MSR value.
2115 Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.
2116 @param EDX Upper 32-bits of MSR value.
2117 Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.
2119 <b>Example usage</b>
2121 MSR_IA32_MTRR_PHYSMASK_REGISTER Msr;
2123 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);
2124 AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);
2126 @note MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM.
2127 MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM.
2128 MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM.
2129 MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM.
2130 MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM.
2131 MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM.
2132 MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM.
2133 MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM.
2134 MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM.
2135 MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.
2138 #define MSR_IA32_MTRR_PHYSMASK0 0x00000201
2139 #define MSR_IA32_MTRR_PHYSMASK1 0x00000203
2140 #define MSR_IA32_MTRR_PHYSMASK2 0x00000205
2141 #define MSR_IA32_MTRR_PHYSMASK3 0x00000207
2142 #define MSR_IA32_MTRR_PHYSMASK4 0x00000209
2143 #define MSR_IA32_MTRR_PHYSMASK5 0x0000020B
2144 #define MSR_IA32_MTRR_PHYSMASK6 0x0000020D
2145 #define MSR_IA32_MTRR_PHYSMASK7 0x0000020F
2146 #define MSR_IA32_MTRR_PHYSMASK8 0x00000211
2147 #define MSR_IA32_MTRR_PHYSMASK9 0x00000213
2151 MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSMASK0 to
2152 #MSR_IA32_MTRR_PHYSMASK9
2156 /// Individual bit fields
2159 UINT32 Reserved1
:11;
2161 /// [Bit 11] Valid Enable range mask.
2165 /// [Bits 31:12] PhysMask. MTRR address range mask.
2169 /// [Bits MAXPHYSADDR:32] PhysMask. Upper bits of MTRR address range mask.
2170 /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the
2171 /// maximum physical address range supported by the processor. It is
2172 /// reported by CPUID leaf function 80000008H. If CPUID does not support
2173 /// leaf 80000008H, the processor supports 36-bit physical address size,
2174 /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.
2176 UINT32 PhysMaskHi
:32;
2179 /// All bit fields as a 64-bit value
2182 } MSR_IA32_MTRR_PHYSMASK_REGISTER
;
2186 MTRRfix64K_00000. If CPUID.01H: EDX.MTRR[12] =1.
2188 @param ECX MSR_IA32_MTRR_FIX64K_00000 (0x00000250)
2189 @param EAX Lower 32-bits of MSR value.
2190 @param EDX Upper 32-bits of MSR value.
2192 <b>Example usage</b>
2196 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX64K_00000);
2197 AsmWriteMsr64 (MSR_IA32_MTRR_FIX64K_00000, Msr);
2199 @note MSR_IA32_MTRR_FIX64K_00000 is defined as IA32_MTRR_FIX64K_00000 in SDM.
2201 #define MSR_IA32_MTRR_FIX64K_00000 0x00000250
2205 MTRRfix16K_80000. If CPUID.01H: EDX.MTRR[12] =1.
2207 @param ECX MSR_IA32_MTRR_FIX16K_80000 (0x00000258)
2208 @param EAX Lower 32-bits of MSR value.
2209 @param EDX Upper 32-bits of MSR value.
2211 <b>Example usage</b>
2215 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_80000);
2216 AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_80000, Msr);
2218 @note MSR_IA32_MTRR_FIX16K_80000 is defined as IA32_MTRR_FIX16K_80000 in SDM.
2220 #define MSR_IA32_MTRR_FIX16K_80000 0x00000258
2224 MTRRfix16K_A0000. If CPUID.01H: EDX.MTRR[12] =1.
2226 @param ECX MSR_IA32_MTRR_FIX16K_A0000 (0x00000259)
2227 @param EAX Lower 32-bits of MSR value.
2228 @param EDX Upper 32-bits of MSR value.
2230 <b>Example usage</b>
2234 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_A0000);
2235 AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_A0000, Msr);
2237 @note MSR_IA32_MTRR_FIX16K_A0000 is defined as IA32_MTRR_FIX16K_A0000 in SDM.
2239 #define MSR_IA32_MTRR_FIX16K_A0000 0x00000259
2243 See Section 11.11.2.2, "Fixed Range MTRRs.". If CPUID.01H: EDX.MTRR[12] =1.
2245 @param ECX MSR_IA32_MTRR_FIX4K_C0000 (0x00000268)
2246 @param EAX Lower 32-bits of MSR value.
2247 @param EDX Upper 32-bits of MSR value.
2249 <b>Example usage</b>
2253 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C0000);
2254 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C0000, Msr);
2256 @note MSR_IA32_MTRR_FIX4K_C0000 is defined as IA32_MTRR_FIX4K_C0000 in SDM.
2258 #define MSR_IA32_MTRR_FIX4K_C0000 0x00000268
2262 MTRRfix4K_C8000. If CPUID.01H: EDX.MTRR[12] =1.
2264 @param ECX MSR_IA32_MTRR_FIX4K_C8000 (0x00000269)
2265 @param EAX Lower 32-bits of MSR value.
2266 @param EDX Upper 32-bits of MSR value.
2268 <b>Example usage</b>
2272 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C8000);
2273 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C8000, Msr);
2275 @note MSR_IA32_MTRR_FIX4K_C8000 is defined as IA32_MTRR_FIX4K_C8000 in SDM.
2277 #define MSR_IA32_MTRR_FIX4K_C8000 0x00000269
2281 MTRRfix4K_D0000. If CPUID.01H: EDX.MTRR[12] =1.
2283 @param ECX MSR_IA32_MTRR_FIX4K_D0000 (0x0000026A)
2284 @param EAX Lower 32-bits of MSR value.
2285 @param EDX Upper 32-bits of MSR value.
2287 <b>Example usage</b>
2291 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D0000);
2292 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D0000, Msr);
2294 @note MSR_IA32_MTRR_FIX4K_D0000 is defined as IA32_MTRR_FIX4K_D0000 in SDM.
2296 #define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A
2300 MTRRfix4K_D8000. If CPUID.01H: EDX.MTRR[12] =1.
2302 @param ECX MSR_IA32_MTRR_FIX4K_D8000 (0x0000026B)
2303 @param EAX Lower 32-bits of MSR value.
2304 @param EDX Upper 32-bits of MSR value.
2306 <b>Example usage</b>
2310 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D8000);
2311 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D8000, Msr);
2313 @note MSR_IA32_MTRR_FIX4K_D8000 is defined as IA32_MTRR_FIX4K_D8000 in SDM.
2315 #define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B
2319 MTRRfix4K_E0000. If CPUID.01H: EDX.MTRR[12] =1.
2321 @param ECX MSR_IA32_MTRR_FIX4K_E0000 (0x0000026C)
2322 @param EAX Lower 32-bits of MSR value.
2323 @param EDX Upper 32-bits of MSR value.
2325 <b>Example usage</b>
2329 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E0000);
2330 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E0000, Msr);
2332 @note MSR_IA32_MTRR_FIX4K_E0000 is defined as IA32_MTRR_FIX4K_E0000 in SDM.
2334 #define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C
2338 MTRRfix4K_E8000. If CPUID.01H: EDX.MTRR[12] =1.
2340 @param ECX MSR_IA32_MTRR_FIX4K_E8000 (0x0000026D)
2341 @param EAX Lower 32-bits of MSR value.
2342 @param EDX Upper 32-bits of MSR value.
2344 <b>Example usage</b>
2348 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E8000);
2349 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E8000, Msr);
2351 @note MSR_IA32_MTRR_FIX4K_E8000 is defined as IA32_MTRR_FIX4K_E8000 in SDM.
2353 #define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D
2357 MTRRfix4K_F0000. If CPUID.01H: EDX.MTRR[12] =1.
2359 @param ECX MSR_IA32_MTRR_FIX4K_F0000 (0x0000026E)
2360 @param EAX Lower 32-bits of MSR value.
2361 @param EDX Upper 32-bits of MSR value.
2363 <b>Example usage</b>
2367 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F0000);
2368 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F0000, Msr);
2370 @note MSR_IA32_MTRR_FIX4K_F0000 is defined as IA32_MTRR_FIX4K_F0000 in SDM.
2372 #define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E
2376 MTRRfix4K_F8000. If CPUID.01H: EDX.MTRR[12] =1.
2378 @param ECX MSR_IA32_MTRR_FIX4K_F8000 (0x0000026F)
2379 @param EAX Lower 32-bits of MSR value.
2380 @param EDX Upper 32-bits of MSR value.
2382 <b>Example usage</b>
2386 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F8000);
2387 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F8000, Msr);
2389 @note MSR_IA32_MTRR_FIX4K_F8000 is defined as IA32_MTRR_FIX4K_F8000 in SDM.
2391 #define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F
2395 IA32_PAT (R/W). If CPUID.01H: EDX.MTRR[16] =1.
2397 @param ECX MSR_IA32_PAT (0x00000277)
2398 @param EAX Lower 32-bits of MSR value.
2399 Described by the type MSR_IA32_PAT_REGISTER.
2400 @param EDX Upper 32-bits of MSR value.
2401 Described by the type MSR_IA32_PAT_REGISTER.
2403 <b>Example usage</b>
2405 MSR_IA32_PAT_REGISTER Msr;
2407 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PAT);
2408 AsmWriteMsr64 (MSR_IA32_PAT, Msr.Uint64);
2410 @note MSR_IA32_PAT is defined as IA32_PAT in SDM.
2412 #define MSR_IA32_PAT 0x00000277
2415 MSR information returned for MSR index #MSR_IA32_PAT
2419 /// Individual bit fields
2428 /// [Bits 10:8] PA1.
2433 /// [Bits 18:16] PA2.
2438 /// [Bits 26:24] PA3.
2443 /// [Bits 34:32] PA4.
2448 /// [Bits 42:40] PA5.
2453 /// [Bits 50:48] PA6.
2458 /// [Bits 58:56] PA7.
2464 /// All bit fields as a 64-bit value
2467 } MSR_IA32_PAT_REGISTER
;
2471 Provides the programming interface to use corrected MC error signaling
2472 capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.
2474 @param ECX MSR_IA32_MCn_CTL2
2475 @param EAX Lower 32-bits of MSR value.
2476 Described by the type MSR_IA32_MC_CTL2_REGISTER.
2477 @param EDX Upper 32-bits of MSR value.
2478 Described by the type MSR_IA32_MC_CTL2_REGISTER.
2480 <b>Example usage</b>
2482 MSR_IA32_MC_CTL2_REGISTER Msr;
2484 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
2485 AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);
2487 @note MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM.
2488 MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM.
2489 MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM.
2490 MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM.
2491 MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM.
2492 MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM.
2493 MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM.
2494 MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM.
2495 MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM.
2496 MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM.
2497 MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM.
2498 MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM.
2499 MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM.
2500 MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM.
2501 MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM.
2502 MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM.
2503 MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM.
2504 MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM.
2505 MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM.
2506 MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM.
2507 MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM.
2508 MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM.
2509 MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM.
2510 MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM.
2511 MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM.
2512 MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM.
2513 MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM.
2514 MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM.
2515 MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM.
2516 MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM.
2517 MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM.
2518 MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.
2521 #define MSR_IA32_MC0_CTL2 0x00000280
2522 #define MSR_IA32_MC1_CTL2 0x00000281
2523 #define MSR_IA32_MC2_CTL2 0x00000282
2524 #define MSR_IA32_MC3_CTL2 0x00000283
2525 #define MSR_IA32_MC4_CTL2 0x00000284
2526 #define MSR_IA32_MC5_CTL2 0x00000285
2527 #define MSR_IA32_MC6_CTL2 0x00000286
2528 #define MSR_IA32_MC7_CTL2 0x00000287
2529 #define MSR_IA32_MC8_CTL2 0x00000288
2530 #define MSR_IA32_MC9_CTL2 0x00000289
2531 #define MSR_IA32_MC10_CTL2 0x0000028A
2532 #define MSR_IA32_MC11_CTL2 0x0000028B
2533 #define MSR_IA32_MC12_CTL2 0x0000028C
2534 #define MSR_IA32_MC13_CTL2 0x0000028D
2535 #define MSR_IA32_MC14_CTL2 0x0000028E
2536 #define MSR_IA32_MC15_CTL2 0x0000028F
2537 #define MSR_IA32_MC16_CTL2 0x00000290
2538 #define MSR_IA32_MC17_CTL2 0x00000291
2539 #define MSR_IA32_MC18_CTL2 0x00000292
2540 #define MSR_IA32_MC19_CTL2 0x00000293
2541 #define MSR_IA32_MC20_CTL2 0x00000294
2542 #define MSR_IA32_MC21_CTL2 0x00000295
2543 #define MSR_IA32_MC22_CTL2 0x00000296
2544 #define MSR_IA32_MC23_CTL2 0x00000297
2545 #define MSR_IA32_MC24_CTL2 0x00000298
2546 #define MSR_IA32_MC25_CTL2 0x00000299
2547 #define MSR_IA32_MC26_CTL2 0x0000029A
2548 #define MSR_IA32_MC27_CTL2 0x0000029B
2549 #define MSR_IA32_MC28_CTL2 0x0000029C
2550 #define MSR_IA32_MC29_CTL2 0x0000029D
2551 #define MSR_IA32_MC30_CTL2 0x0000029E
2552 #define MSR_IA32_MC31_CTL2 0x0000029F
2556 MSR information returned for MSR indexes #MSR_IA32_MC0_CTL2
2557 to #MSR_IA32_MC31_CTL2
2561 /// Individual bit fields
2565 /// [Bits 14:0] Corrected error count threshold.
2567 UINT32 CorrectedErrorCountThreshold
:15;
2568 UINT32 Reserved1
:15;
2570 /// [Bit 30] CMCI_EN.
2574 UINT32 Reserved3
:32;
2577 /// All bit fields as a 32-bit value
2581 /// All bit fields as a 64-bit value
2584 } MSR_IA32_MC_CTL2_REGISTER
;
2588 MTRRdefType (R/W). If CPUID.01H: EDX.MTRR[12] =1.
2590 @param ECX MSR_IA32_MTRR_DEF_TYPE (0x000002FF)
2591 @param EAX Lower 32-bits of MSR value.
2592 Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.
2593 @param EDX Upper 32-bits of MSR value.
2594 Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.
2596 <b>Example usage</b>
2598 MSR_IA32_MTRR_DEF_TYPE_REGISTER Msr;
2600 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);
2601 AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, Msr.Uint64);
2603 @note MSR_IA32_MTRR_DEF_TYPE is defined as IA32_MTRR_DEF_TYPE in SDM.
2605 #define MSR_IA32_MTRR_DEF_TYPE 0x000002FF
2608 MSR information returned for MSR index #MSR_IA32_MTRR_DEF_TYPE
2612 /// Individual bit fields
2616 /// [Bits 2:0] Default Memory Type.
2621 /// [Bit 10] Fixed Range MTRR Enable.
2625 /// [Bit 11] MTRR Enable.
2628 UINT32 Reserved2
:20;
2629 UINT32 Reserved3
:32;
2632 /// All bit fields as a 32-bit value
2636 /// All bit fields as a 64-bit value
2639 } MSR_IA32_MTRR_DEF_TYPE_REGISTER
;
2643 Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any. If
2644 CPUID.0AH: EDX[4:0] > 0.
2646 @param ECX MSR_IA32_FIXED_CTR0 (0x00000309)
2647 @param EAX Lower 32-bits of MSR value.
2648 @param EDX Upper 32-bits of MSR value.
2650 <b>Example usage</b>
2654 Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR0);
2655 AsmWriteMsr64 (MSR_IA32_FIXED_CTR0, Msr);
2657 @note MSR_IA32_FIXED_CTR0 is defined as IA32_FIXED_CTR0 in SDM.
2659 #define MSR_IA32_FIXED_CTR0 0x00000309
2663 Fixed-Function Performance Counter 1 0 (R/W): Counts CPU_CLK_Unhalted.Core.
2664 If CPUID.0AH: EDX[4:0] > 1.
2666 @param ECX MSR_IA32_FIXED_CTR1 (0x0000030A)
2667 @param EAX Lower 32-bits of MSR value.
2668 @param EDX Upper 32-bits of MSR value.
2670 <b>Example usage</b>
2674 Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR1);
2675 AsmWriteMsr64 (MSR_IA32_FIXED_CTR1, Msr);
2677 @note MSR_IA32_FIXED_CTR1 is defined as IA32_FIXED_CTR1 in SDM.
2679 #define MSR_IA32_FIXED_CTR1 0x0000030A
2683 Fixed-Function Performance Counter 0 0 (R/W): Counts CPU_CLK_Unhalted.Ref.
2684 If CPUID.0AH: EDX[4:0] > 2.
2686 @param ECX MSR_IA32_FIXED_CTR2 (0x0000030B)
2687 @param EAX Lower 32-bits of MSR value.
2688 @param EDX Upper 32-bits of MSR value.
2690 <b>Example usage</b>
2694 Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR2);
2695 AsmWriteMsr64 (MSR_IA32_FIXED_CTR2, Msr);
2697 @note MSR_IA32_FIXED_CTR2 is defined as IA32_FIXED_CTR2 in SDM.
2699 #define MSR_IA32_FIXED_CTR2 0x0000030B
2703 RO. If CPUID.01H: ECX[15] = 1.
2705 @param ECX MSR_IA32_PERF_CAPABILITIES (0x00000345)
2706 @param EAX Lower 32-bits of MSR value.
2707 Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.
2708 @param EDX Upper 32-bits of MSR value.
2709 Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.
2711 <b>Example usage</b>
2713 MSR_IA32_PERF_CAPABILITIES_REGISTER Msr;
2715 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CAPABILITIES);
2716 AsmWriteMsr64 (MSR_IA32_PERF_CAPABILITIES, Msr.Uint64);
2718 @note MSR_IA32_PERF_CAPABILITIES is defined as IA32_PERF_CAPABILITIES in SDM.
2720 #define MSR_IA32_PERF_CAPABILITIES 0x00000345
2723 MSR information returned for MSR index #MSR_IA32_PERF_CAPABILITIES
2727 /// Individual bit fields
2731 /// [Bits 5:0] LBR format.
2735 /// [Bit 6] PEBS Trap.
2739 /// [Bit 7] PEBSSaveArchRegs.
2741 UINT32 PEBS_ARCH_REG
:1;
2743 /// [Bits 11:8] PEBS Record Format.
2745 UINT32 PEBS_REC_FMT
:4;
2747 /// [Bit 12] 1: Freeze while SMM is supported.
2749 UINT32 SMM_FREEZE
:1;
2751 /// [Bit 13] 1: Full width of counter writable via IA32_A_PMCx.
2754 UINT32 Reserved1
:18;
2755 UINT32 Reserved2
:32;
2758 /// All bit fields as a 32-bit value
2762 /// All bit fields as a 64-bit value
2765 } MSR_IA32_PERF_CAPABILITIES_REGISTER
;
2769 Fixed-Function Performance Counter Control (R/W) Counter increments while
2770 the results of ANDing respective enable bit in IA32_PERF_GLOBAL_CTRL with
2771 the corresponding OS or USR bits in this MSR is true. If CPUID.0AH: EAX[7:0]
2774 @param ECX MSR_IA32_FIXED_CTR_CTRL (0x0000038D)
2775 @param EAX Lower 32-bits of MSR value.
2776 Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.
2777 @param EDX Upper 32-bits of MSR value.
2778 Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.
2780 <b>Example usage</b>
2782 MSR_IA32_FIXED_CTR_CTRL_REGISTER Msr;
2784 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FIXED_CTR_CTRL);
2785 AsmWriteMsr64 (MSR_IA32_FIXED_CTR_CTRL, Msr.Uint64);
2787 @note MSR_IA32_FIXED_CTR_CTRL is defined as IA32_FIXED_CTR_CTRL in SDM.
2789 #define MSR_IA32_FIXED_CTR_CTRL 0x0000038D
2792 MSR information returned for MSR index #MSR_IA32_FIXED_CTR_CTRL
2796 /// Individual bit fields
2800 /// [Bit 0] EN0_OS: Enable Fixed Counter 0 to count while CPL = 0.
2804 /// [Bit 1] EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0.
2808 /// [Bit 2] AnyThread: When set to 1, it enables counting the associated
2809 /// event conditions occurring across all logical processors sharing a
2810 /// processor core. When set to 0, the counter only increments the
2811 /// associated event conditions occurring in the logical processor which
2812 /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
2814 UINT32 AnyThread0
:1;
2816 /// [Bit 3] EN0_PMI: Enable PMI when fixed counter 0 overflows.
2820 /// [Bit 4] EN1_OS: Enable Fixed Counter 1 to count while CPL = 0.
2824 /// [Bit 5] EN1_Usr: Enable Fixed Counter 1 to count while CPL > 0.
2828 /// [Bit 6] AnyThread: When set to 1, it enables counting the associated
2829 /// event conditions occurring across all logical processors sharing a
2830 /// processor core. When set to 0, the counter only increments the
2831 /// associated event conditions occurring in the logical processor which
2832 /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
2834 UINT32 AnyThread1
:1;
2836 /// [Bit 7] EN1_PMI: Enable PMI when fixed counter 1 overflows.
2840 /// [Bit 8] EN2_OS: Enable Fixed Counter 2 to count while CPL = 0.
2844 /// [Bit 9] EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0.
2848 /// [Bit 10] AnyThread: When set to 1, it enables counting the associated
2849 /// event conditions occurring across all logical processors sharing a
2850 /// processor core. When set to 0, the counter only increments the
2851 /// associated event conditions occurring in the logical processor which
2852 /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
2854 UINT32 AnyThread2
:1;
2856 /// [Bit 11] EN2_PMI: Enable PMI when fixed counter 2 overflows.
2859 UINT32 Reserved1
:20;
2860 UINT32 Reserved2
:32;
2863 /// All bit fields as a 32-bit value
2867 /// All bit fields as a 64-bit value
2870 } MSR_IA32_FIXED_CTR_CTRL_REGISTER
;
2874 Global Performance Counter Status (RO). If CPUID.0AH: EAX[7:0] > 0.
2876 @param ECX MSR_IA32_PERF_GLOBAL_STATUS (0x0000038E)
2877 @param EAX Lower 32-bits of MSR value.
2878 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.
2879 @param EDX Upper 32-bits of MSR value.
2880 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.
2882 <b>Example usage</b>
2884 MSR_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;
2886 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS);
2888 @note MSR_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
2890 #define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E
2893 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS
2897 /// Individual bit fields
2901 /// [Bit 0] Ovf_PMC0: Overflow status of IA32_PMC0. If CPUID.0AH:
2906 /// [Bit 1] Ovf_PMC1: Overflow status of IA32_PMC1. If CPUID.0AH:
2911 /// [Bit 2] Ovf_PMC2: Overflow status of IA32_PMC2. If CPUID.0AH:
2916 /// [Bit 3] Ovf_PMC3: Overflow status of IA32_PMC3. If CPUID.0AH:
2920 UINT32 Reserved1
:28;
2922 /// [Bit 32] Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0. If
2923 /// CPUID.0AH: EAX[7:0] > 1.
2925 UINT32 Ovf_FixedCtr0
:1;
2927 /// [Bit 33] Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1. If
2928 /// CPUID.0AH: EAX[7:0] > 1.
2930 UINT32 Ovf_FixedCtr1
:1;
2932 /// [Bit 34] Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2. If
2933 /// CPUID.0AH: EAX[7:0] > 1.
2935 UINT32 Ovf_FixedCtr2
:1;
2936 UINT32 Reserved2
:20;
2938 /// [Bit 55] Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory
2939 /// buffer was completely filled. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1)
2940 /// && IA32_RTIT_CTL.ToPA = 1.
2942 UINT32 Trace_ToPA_PMI
:1;
2945 /// [Bit 58] LBR_Frz: LBRs are frozen due to -
2946 /// IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1, - The LBR stack overflowed. If
2947 /// CPUID.0AH: EAX[7:0] > 3.
2951 /// [Bit 59] CTR_Frz: Performance counters in the core PMU are frozen due
2952 /// to - IA32_DEBUGCTL.FREEZE_PERFMON_ON_ PMI=1, - one or more core PMU
2953 /// counters overflowed. If CPUID.0AH: EAX[7:0] > 3.
2957 /// [Bit 60] ASCI: Data in the performance counters in the core PMU may
2958 /// include contributions from the direct or indirect operation intel SGX
2959 /// to protect an enclave. If CPUID.(EAX=07H, ECX=0):EBX[2] = 1.
2963 /// [Bit 61] Ovf_Uncore: Uncore counter overflow status. If CPUID.0AH:
2966 UINT32 Ovf_Uncore
:1;
2968 /// [Bit 62] OvfBuf: DS SAVE area Buffer overflow status. If CPUID.0AH:
2973 /// [Bit 63] CondChgd: status bits of this register has changed. If
2974 /// CPUID.0AH: EAX[7:0] > 0.
2979 /// All bit fields as a 64-bit value
2982 } MSR_IA32_PERF_GLOBAL_STATUS_REGISTER
;
2986 Global Performance Counter Control (R/W) Counter increments while the result
2987 of ANDing respective enable bit in this MSR with the corresponding OS or USR
2988 bits in the general-purpose or fixed counter control MSR is true. If
2989 CPUID.0AH: EAX[7:0] > 0.
2991 @param ECX MSR_IA32_PERF_GLOBAL_CTRL (0x0000038F)
2992 @param EAX Lower 32-bits of MSR value.
2993 Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.
2994 @param EDX Upper 32-bits of MSR value.
2995 Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.
2997 <b>Example usage</b>
2999 MSR_IA32_PERF_GLOBAL_CTRL_REGISTER Msr;
3001 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_CTRL);
3002 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);
3004 @note MSR_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.
3006 #define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F
3009 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_CTRL
3013 /// Individual bit fields
3017 /// [Bits 31:0] EN_PMCn. If CPUID.0AH: EAX[15:8] > n.
3018 /// Enable bitmask. Only the first n-1 bits are valid.
3019 /// Bits n..31 are reserved.
3023 /// [Bits 63:32] EN_FIXED_CTRn. If CPUID.0AH: EDX[4:0] > n.
3024 /// Enable bitmask. Only the first n-1 bits are valid.
3025 /// Bits 31:n are reserved.
3027 UINT32 EN_FIXED_CTRn
:32;
3030 /// All bit fields as a 64-bit value
3033 } MSR_IA32_PERF_GLOBAL_CTRL_REGISTER
;
3037 Global Performance Counter Overflow Control (R/W). If CPUID.0AH: EAX[7:0] >
3038 0 && CPUID.0AH: EAX[7:0] <= 3.
3040 @param ECX MSR_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)
3041 @param EAX Lower 32-bits of MSR value.
3042 Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
3043 @param EDX Upper 32-bits of MSR value.
3044 Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
3046 <b>Example usage</b>
3048 MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;
3050 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL);
3051 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);
3053 @note MSR_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.
3055 #define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390
3058 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_OVF_CTRL
3062 /// Individual bit fields
3066 /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.
3067 /// Clear bitmask. Only the first n-1 bits are valid.
3068 /// Bits 31:n are reserved.
3072 /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.
3073 /// If CPUID.0AH: EDX[4:0] > n.
3074 /// Clear bitmask. Only the first n-1 bits are valid.
3075 /// Bits 22:n are reserved.
3077 UINT32 Ovf_FIXED_CTRn
:23;
3079 /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,
3080 /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1.
3082 UINT32 Trace_ToPA_PMI
:1;
3085 /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /
3086 /// Display Model 06_2EH.
3088 UINT32 Ovf_Uncore
:1;
3090 /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.
3094 /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.
3099 /// All bit fields as a 64-bit value
3102 } MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER
;
3106 Global Performance Counter Overflow Reset Control (R/W). If CPUID.0AH:
3109 @param ECX MSR_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)
3110 @param EAX Lower 32-bits of MSR value.
3111 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
3112 @param EDX Upper 32-bits of MSR value.
3113 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
3115 <b>Example usage</b>
3117 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;
3119 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET);
3120 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);
3122 @note MSR_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.
3124 #define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
3127 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_RESET
3131 /// Individual bit fields
3135 /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.
3136 /// Clear bitmask. Only the first n-1 bits are valid.
3137 /// Bits 31:n are reserved.
3141 /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.
3142 /// If CPUID.0AH: EDX[4:0] > n.
3143 /// Clear bitmask. Only the first n-1 bits are valid.
3144 /// Bits 22:n are reserved.
3146 UINT32 Ovf_FIXED_CTRn
:23;
3148 /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,
3149 /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1.
3151 UINT32 Trace_ToPA_PMI
:1;
3154 /// [Bit 58] Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.
3158 /// [Bit 59] Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.
3162 /// [Bit 60] Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3.
3166 /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /
3167 /// Display Model 06_2EH.
3169 UINT32 Ovf_Uncore
:1;
3171 /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.
3175 /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.
3180 /// All bit fields as a 64-bit value
3183 } MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER
;
3187 Global Performance Counter Overflow Set Control (R/W). If CPUID.0AH:
3190 @param ECX MSR_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)
3191 @param EAX Lower 32-bits of MSR value.
3192 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
3193 @param EDX Upper 32-bits of MSR value.
3194 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
3196 <b>Example usage</b>
3198 MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;
3200 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET);
3201 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);
3203 @note MSR_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.
3205 #define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391
3208 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_SET
3212 /// Individual bit fields
3216 /// [Bits 31:0] Set 1 to cause Ovf_PMCn = 1. If CPUID.0AH: EAX[7:0] > n.
3217 /// Set bitmask. Only the first n-1 bits are valid.
3218 /// Bits 31:n are reserved.
3222 /// [Bits 54:32] Set 1 to cause Ovf_FIXED_CTRn = 1.
3223 /// If CPUID.0AH: EAX[7:0] > n.
3224 /// Set bitmask. Only the first n-1 bits are valid.
3225 /// Bits 22:n are reserved.
3227 UINT32 Ovf_FIXED_CTRn
:23;
3229 /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1. If CPUID.0AH: EAX[7:0] > 3.
3231 UINT32 Trace_ToPA_PMI
:1;
3234 /// [Bit 58] Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.
3238 /// [Bit 59] Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.
3242 /// [Bit 60] Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3.
3246 /// [Bit 61] Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3.
3248 UINT32 Ovf_Uncore
:1;
3250 /// [Bit 62] Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 3.
3256 /// All bit fields as a 64-bit value
3259 } MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
;
3263 Indicator of core perfmon interface is in use (RO). If CPUID.0AH: EAX[7:0] >
3266 @param ECX MSR_IA32_PERF_GLOBAL_INUSE (0x00000392)
3267 @param EAX Lower 32-bits of MSR value.
3268 Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.
3269 @param EDX Upper 32-bits of MSR value.
3270 Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.
3272 <b>Example usage</b>
3274 MSR_IA32_PERF_GLOBAL_INUSE_REGISTER Msr;
3276 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_INUSE);
3278 @note MSR_IA32_PERF_GLOBAL_INUSE is defined as IA32_PERF_GLOBAL_INUSE in SDM.
3280 #define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392
3283 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_INUSE
3287 /// Individual bit fields
3291 /// [Bits 31:0] IA32_PERFEVTSELn in use. If CPUID.0AH: EAX[7:0] > n.
3292 /// Status bitmask. Only the first n-1 bits are valid.
3293 /// Bits 31:n are reserved.
3295 UINT32 IA32_PERFEVTSELn
:32;
3297 /// [Bits 62:32] IA32_FIXED_CTRn in use.
3298 /// If CPUID.0AH: EAX[7:0] > n.
3299 /// Status bitmask. Only the first n-1 bits are valid.
3300 /// Bits 30:n are reserved.
3302 UINT32 IA32_FIXED_CTRn
:31;
3304 /// [Bit 63] PMI in use.
3309 /// All bit fields as a 64-bit value
3312 } MSR_IA32_PERF_GLOBAL_INUSE_REGISTER
;
3318 @param ECX MSR_IA32_PEBS_ENABLE (0x000003F1)
3319 @param EAX Lower 32-bits of MSR value.
3320 Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.
3321 @param EDX Upper 32-bits of MSR value.
3322 Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.
3324 <b>Example usage</b>
3326 MSR_IA32_PEBS_ENABLE_REGISTER Msr;
3328 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PEBS_ENABLE);
3329 AsmWriteMsr64 (MSR_IA32_PEBS_ENABLE, Msr.Uint64);
3331 @note MSR_IA32_PEBS_ENABLE is defined as IA32_PEBS_ENABLE in SDM.
3333 #define MSR_IA32_PEBS_ENABLE 0x000003F1
3336 MSR information returned for MSR index #MSR_IA32_PEBS_ENABLE
3340 /// Individual bit fields
3344 /// [Bit 0] Enable PEBS on IA32_PMC0. Introduced at Display Family /
3345 /// Display Model 06_0FH.
3349 /// [Bits 3:1] Reserved or Model specific.
3352 UINT32 Reserved2
:28;
3354 /// [Bits 35:32] Reserved or Model specific.
3357 UINT32 Reserved4
:28;
3360 /// All bit fields as a 64-bit value
3363 } MSR_IA32_PEBS_ENABLE_REGISTER
;
3367 MCn_CTL. If IA32_MCG_CAP.CNT > n.
3369 @param ECX MSR_IA32_MCn_CTL
3370 @param EAX Lower 32-bits of MSR value.
3371 @param EDX Upper 32-bits of MSR value.
3373 <b>Example usage</b>
3377 Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
3378 AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);
3380 @note MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM.
3381 MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM.
3382 MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM.
3383 MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM.
3384 MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM.
3385 MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM.
3386 MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM.
3387 MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM.
3388 MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM.
3389 MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM.
3390 MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM.
3391 MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM.
3392 MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM.
3393 MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM.
3394 MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM.
3395 MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM.
3396 MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM.
3397 MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM.
3398 MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM.
3399 MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM.
3400 MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM.
3401 MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM.
3402 MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM.
3403 MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM.
3404 MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM.
3405 MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM.
3406 MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM.
3407 MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM.
3408 MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.
3411 #define MSR_IA32_MC0_CTL 0x00000400
3412 #define MSR_IA32_MC1_CTL 0x00000404
3413 #define MSR_IA32_MC2_CTL 0x00000408
3414 #define MSR_IA32_MC3_CTL 0x0000040C
3415 #define MSR_IA32_MC4_CTL 0x00000410
3416 #define MSR_IA32_MC5_CTL 0x00000414
3417 #define MSR_IA32_MC6_CTL 0x00000418
3418 #define MSR_IA32_MC7_CTL 0x0000041C
3419 #define MSR_IA32_MC8_CTL 0x00000420
3420 #define MSR_IA32_MC9_CTL 0x00000424
3421 #define MSR_IA32_MC10_CTL 0x00000428
3422 #define MSR_IA32_MC11_CTL 0x0000042C
3423 #define MSR_IA32_MC12_CTL 0x00000430
3424 #define MSR_IA32_MC13_CTL 0x00000434
3425 #define MSR_IA32_MC14_CTL 0x00000438
3426 #define MSR_IA32_MC15_CTL 0x0000043C
3427 #define MSR_IA32_MC16_CTL 0x00000440
3428 #define MSR_IA32_MC17_CTL 0x00000444
3429 #define MSR_IA32_MC18_CTL 0x00000448
3430 #define MSR_IA32_MC19_CTL 0x0000044C
3431 #define MSR_IA32_MC20_CTL 0x00000450
3432 #define MSR_IA32_MC21_CTL 0x00000454
3433 #define MSR_IA32_MC22_CTL 0x00000458
3434 #define MSR_IA32_MC23_CTL 0x0000045C
3435 #define MSR_IA32_MC24_CTL 0x00000460
3436 #define MSR_IA32_MC25_CTL 0x00000464
3437 #define MSR_IA32_MC26_CTL 0x00000468
3438 #define MSR_IA32_MC27_CTL 0x0000046C
3439 #define MSR_IA32_MC28_CTL 0x00000470
3444 MCn_STATUS. If IA32_MCG_CAP.CNT > n.
3446 @param ECX MSR_IA32_MCn_STATUS
3447 @param EAX Lower 32-bits of MSR value.
3448 @param EDX Upper 32-bits of MSR value.
3450 <b>Example usage</b>
3454 Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
3455 AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);
3457 @note MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM.
3458 MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM.
3459 MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM.
3460 MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM.
3461 MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM.
3462 MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM.
3463 MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM.
3464 MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM.
3465 MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM.
3466 MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM.
3467 MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM.
3468 MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM.
3469 MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM.
3470 MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM.
3471 MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM.
3472 MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM.
3473 MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM.
3474 MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM.
3475 MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM.
3476 MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM.
3477 MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM.
3478 MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM.
3479 MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM.
3480 MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM.
3481 MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM.
3482 MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM.
3483 MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM.
3484 MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM.
3485 MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.
3488 #define MSR_IA32_MC0_STATUS 0x00000401
3489 #define MSR_IA32_MC1_STATUS 0x00000405
3490 #define MSR_IA32_MC2_STATUS 0x00000409
3491 #define MSR_IA32_MC3_STATUS 0x0000040D
3492 #define MSR_IA32_MC4_STATUS 0x00000411
3493 #define MSR_IA32_MC5_STATUS 0x00000415
3494 #define MSR_IA32_MC6_STATUS 0x00000419
3495 #define MSR_IA32_MC7_STATUS 0x0000041D
3496 #define MSR_IA32_MC8_STATUS 0x00000421
3497 #define MSR_IA32_MC9_STATUS 0x00000425
3498 #define MSR_IA32_MC10_STATUS 0x00000429
3499 #define MSR_IA32_MC11_STATUS 0x0000042D
3500 #define MSR_IA32_MC12_STATUS 0x00000431
3501 #define MSR_IA32_MC13_STATUS 0x00000435
3502 #define MSR_IA32_MC14_STATUS 0x00000439
3503 #define MSR_IA32_MC15_STATUS 0x0000043D
3504 #define MSR_IA32_MC16_STATUS 0x00000441
3505 #define MSR_IA32_MC17_STATUS 0x00000445
3506 #define MSR_IA32_MC18_STATUS 0x00000449
3507 #define MSR_IA32_MC19_STATUS 0x0000044D
3508 #define MSR_IA32_MC20_STATUS 0x00000451
3509 #define MSR_IA32_MC21_STATUS 0x00000455
3510 #define MSR_IA32_MC22_STATUS 0x00000459
3511 #define MSR_IA32_MC23_STATUS 0x0000045D
3512 #define MSR_IA32_MC24_STATUS 0x00000461
3513 #define MSR_IA32_MC25_STATUS 0x00000465
3514 #define MSR_IA32_MC26_STATUS 0x00000469
3515 #define MSR_IA32_MC27_STATUS 0x0000046D
3516 #define MSR_IA32_MC28_STATUS 0x00000471
3521 MCn_ADDR. If IA32_MCG_CAP.CNT > n.
3523 @param ECX MSR_IA32_MCn_ADDR
3524 @param EAX Lower 32-bits of MSR value.
3525 @param EDX Upper 32-bits of MSR value.
3527 <b>Example usage</b>
3531 Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
3532 AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);
3534 @note MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM.
3535 MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM.
3536 MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM.
3537 MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM.
3538 MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM.
3539 MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM.
3540 MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM.
3541 MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM.
3542 MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM.
3543 MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM.
3544 MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM.
3545 MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM.
3546 MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM.
3547 MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM.
3548 MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM.
3549 MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM.
3550 MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM.
3551 MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM.
3552 MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM.
3553 MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM.
3554 MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM.
3555 MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM.
3556 MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM.
3557 MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM.
3558 MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM.
3559 MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM.
3560 MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM.
3561 MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM.
3562 MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.
3565 #define MSR_IA32_MC0_ADDR 0x00000402
3566 #define MSR_IA32_MC1_ADDR 0x00000406
3567 #define MSR_IA32_MC2_ADDR 0x0000040A
3568 #define MSR_IA32_MC3_ADDR 0x0000040E
3569 #define MSR_IA32_MC4_ADDR 0x00000412
3570 #define MSR_IA32_MC5_ADDR 0x00000416
3571 #define MSR_IA32_MC6_ADDR 0x0000041A
3572 #define MSR_IA32_MC7_ADDR 0x0000041E
3573 #define MSR_IA32_MC8_ADDR 0x00000422
3574 #define MSR_IA32_MC9_ADDR 0x00000426
3575 #define MSR_IA32_MC10_ADDR 0x0000042A
3576 #define MSR_IA32_MC11_ADDR 0x0000042E
3577 #define MSR_IA32_MC12_ADDR 0x00000432
3578 #define MSR_IA32_MC13_ADDR 0x00000436
3579 #define MSR_IA32_MC14_ADDR 0x0000043A
3580 #define MSR_IA32_MC15_ADDR 0x0000043E
3581 #define MSR_IA32_MC16_ADDR 0x00000442
3582 #define MSR_IA32_MC17_ADDR 0x00000446
3583 #define MSR_IA32_MC18_ADDR 0x0000044A
3584 #define MSR_IA32_MC19_ADDR 0x0000044E
3585 #define MSR_IA32_MC20_ADDR 0x00000452
3586 #define MSR_IA32_MC21_ADDR 0x00000456
3587 #define MSR_IA32_MC22_ADDR 0x0000045A
3588 #define MSR_IA32_MC23_ADDR 0x0000045E
3589 #define MSR_IA32_MC24_ADDR 0x00000462
3590 #define MSR_IA32_MC25_ADDR 0x00000466
3591 #define MSR_IA32_MC26_ADDR 0x0000046A
3592 #define MSR_IA32_MC27_ADDR 0x0000046E
3593 #define MSR_IA32_MC28_ADDR 0x00000472
3598 MCn_MISC. If IA32_MCG_CAP.CNT > n.
3600 @param ECX MSR_IA32_MCn_MISC
3601 @param EAX Lower 32-bits of MSR value.
3602 @param EDX Upper 32-bits of MSR value.
3604 <b>Example usage</b>
3608 Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
3609 AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);
3611 @note MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM.
3612 MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM.
3613 MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM.
3614 MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM.
3615 MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM.
3616 MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM.
3617 MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.
3618 MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM.
3619 MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM.
3620 MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM.
3621 MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM.
3622 MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM.
3623 MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM.
3624 MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM.
3625 MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM.
3626 MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM.
3627 MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM.
3628 MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM.
3629 MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM.
3630 MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM.
3631 MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM.
3632 MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM.
3633 MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM.
3634 MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM.
3635 MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM.
3636 MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM.
3637 MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM.
3638 MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM.
3639 MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.
3642 #define MSR_IA32_MC0_MISC 0x00000403
3643 #define MSR_IA32_MC1_MISC 0x00000407
3644 #define MSR_IA32_MC2_MISC 0x0000040B
3645 #define MSR_IA32_MC3_MISC 0x0000040F
3646 #define MSR_IA32_MC4_MISC 0x00000413
3647 #define MSR_IA32_MC5_MISC 0x00000417
3648 #define MSR_IA32_MC6_MISC 0x0000041B
3649 #define MSR_IA32_MC7_MISC 0x0000041F
3650 #define MSR_IA32_MC8_MISC 0x00000423
3651 #define MSR_IA32_MC9_MISC 0x00000427
3652 #define MSR_IA32_MC10_MISC 0x0000042B
3653 #define MSR_IA32_MC11_MISC 0x0000042F
3654 #define MSR_IA32_MC12_MISC 0x00000433
3655 #define MSR_IA32_MC13_MISC 0x00000437
3656 #define MSR_IA32_MC14_MISC 0x0000043B
3657 #define MSR_IA32_MC15_MISC 0x0000043F
3658 #define MSR_IA32_MC16_MISC 0x00000443
3659 #define MSR_IA32_MC17_MISC 0x00000447
3660 #define MSR_IA32_MC18_MISC 0x0000044B
3661 #define MSR_IA32_MC19_MISC 0x0000044F
3662 #define MSR_IA32_MC20_MISC 0x00000453
3663 #define MSR_IA32_MC21_MISC 0x00000457
3664 #define MSR_IA32_MC22_MISC 0x0000045B
3665 #define MSR_IA32_MC23_MISC 0x0000045F
3666 #define MSR_IA32_MC24_MISC 0x00000463
3667 #define MSR_IA32_MC25_MISC 0x00000467
3668 #define MSR_IA32_MC26_MISC 0x0000046B
3669 #define MSR_IA32_MC27_MISC 0x0000046F
3670 #define MSR_IA32_MC28_MISC 0x00000473
3675 Reporting Register of Basic VMX Capabilities (R/O) See Appendix A.1, "Basic
3676 VMX Information.". If CPUID.01H:ECX.[5] = 1.
3678 @param ECX MSR_IA32_VMX_BASIC (0x00000480)
3679 @param EAX Lower 32-bits of MSR value.
3680 @param EDX Upper 32-bits of MSR value.
3682 <b>Example usage</b>
3686 Msr = AsmReadMsr64 (MSR_IA32_VMX_BASIC);
3688 @note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM.
3690 #define MSR_IA32_VMX_BASIC 0x00000480
3694 Capability Reporting Register of Pinbased VM-execution Controls (R/O) See
3695 Appendix A.3.1, "Pin-Based VMExecution Controls.". If CPUID.01H:ECX.[5] = 1.
3697 @param ECX MSR_IA32_VMX_PINBASED_CTLS (0x00000481)
3698 @param EAX Lower 32-bits of MSR value.
3699 @param EDX Upper 32-bits of MSR value.
3701 <b>Example usage</b>
3705 Msr = AsmReadMsr64 (MSR_IA32_VMX_PINBASED_CTLS);
3707 @note MSR_IA32_VMX_PINBASED_CTLS is defined as IA32_VMX_PINBASED_CTLS in SDM.
3709 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
3713 Capability Reporting Register of Primary Processor-based VM-execution
3714 Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution
3715 Controls.". If CPUID.01H:ECX.[5] = 1.
3717 @param ECX MSR_IA32_VMX_PROCBASED_CTLS (0x00000482)
3718 @param EAX Lower 32-bits of MSR value.
3719 @param EDX Upper 32-bits of MSR value.
3721 <b>Example usage</b>
3725 Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS);
3727 @note MSR_IA32_VMX_PROCBASED_CTLS is defined as IA32_VMX_PROCBASED_CTLS in SDM.
3729 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
3733 Capability Reporting Register of VM-exit Controls (R/O) See Appendix A.4,
3734 "VM-Exit Controls.". If CPUID.01H:ECX.[5] = 1.
3736 @param ECX MSR_IA32_VMX_EXIT_CTLS (0x00000483)
3737 @param EAX Lower 32-bits of MSR value.
3738 @param EDX Upper 32-bits of MSR value.
3740 <b>Example usage</b>
3744 Msr = AsmReadMsr64 (MSR_IA32_VMX_EXIT_CTLS);
3746 @note MSR_IA32_VMX_EXIT_CTLS is defined as IA32_VMX_EXIT_CTLS in SDM.
3748 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
3752 Capability Reporting Register of VMentry Controls (R/O) See Appendix A.5,
3753 "VM-Entry Controls.". If CPUID.01H:ECX.[5] = 1.
3755 @param ECX MSR_IA32_VMX_ENTRY_CTLS (0x00000484)
3756 @param EAX Lower 32-bits of MSR value.
3757 @param EDX Upper 32-bits of MSR value.
3759 <b>Example usage</b>
3763 Msr = AsmReadMsr64 (MSR_IA32_VMX_ENTRY_CTLS);
3765 @note MSR_IA32_VMX_ENTRY_CTLS is defined as IA32_VMX_ENTRY_CTLS in SDM.
3767 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
3771 Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6,
3772 "Miscellaneous Data.". If CPUID.01H:ECX.[5] = 1.
3774 @param ECX MSR_IA32_VMX_MISC (0x00000485)
3775 @param EAX Lower 32-bits of MSR value.
3776 @param EDX Upper 32-bits of MSR value.
3778 <b>Example usage</b>
3782 Msr = AsmReadMsr64 (MSR_IA32_VMX_MISC);
3784 @note MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM.
3786 #define MSR_IA32_VMX_MISC 0x00000485
3790 Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7,
3791 "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.
3793 @param ECX MSR_IA32_VMX_CR0_FIXED0 (0x00000486)
3794 @param EAX Lower 32-bits of MSR value.
3795 @param EDX Upper 32-bits of MSR value.
3797 <b>Example usage</b>
3801 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED0);
3803 @note MSR_IA32_VMX_CR0_FIXED0 is defined as IA32_VMX_CR0_FIXED0 in SDM.
3805 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
3809 Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7,
3810 "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.
3812 @param ECX MSR_IA32_VMX_CR0_FIXED1 (0x00000487)
3813 @param EAX Lower 32-bits of MSR value.
3814 @param EDX Upper 32-bits of MSR value.
3816 <b>Example usage</b>
3820 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED1);
3822 @note MSR_IA32_VMX_CR0_FIXED1 is defined as IA32_VMX_CR0_FIXED1 in SDM.
3824 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
3828 Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8,
3829 "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.
3831 @param ECX MSR_IA32_VMX_CR4_FIXED0 (0x00000488)
3832 @param EAX Lower 32-bits of MSR value.
3833 @param EDX Upper 32-bits of MSR value.
3835 <b>Example usage</b>
3839 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED0);
3841 @note MSR_IA32_VMX_CR4_FIXED0 is defined as IA32_VMX_CR4_FIXED0 in SDM.
3843 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
3847 Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Appendix A.8,
3848 "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.
3850 @param ECX MSR_IA32_VMX_CR4_FIXED1 (0x00000489)
3851 @param EAX Lower 32-bits of MSR value.
3852 @param EDX Upper 32-bits of MSR value.
3854 <b>Example usage</b>
3858 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED1);
3860 @note MSR_IA32_VMX_CR4_FIXED1 is defined as IA32_VMX_CR4_FIXED1 in SDM.
3862 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
3866 Capability Reporting Register of VMCS Field Enumeration (R/O) See Appendix
3867 A.9, "VMCS Enumeration.". If CPUID.01H:ECX.[5] = 1.
3869 @param ECX MSR_IA32_VMX_VMCS_ENUM (0x0000048A)
3870 @param EAX Lower 32-bits of MSR value.
3871 @param EDX Upper 32-bits of MSR value.
3873 <b>Example usage</b>
3877 Msr = AsmReadMsr64 (MSR_IA32_VMX_VMCS_ENUM);
3879 @note MSR_IA32_VMX_VMCS_ENUM is defined as IA32_VMX_VMCS_ENUM in SDM.
3881 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048A
3885 Capability Reporting Register of Secondary Processor-based VM-execution
3886 Controls (R/O) See Appendix A.3.3, "Secondary Processor- Based VM-Execution
3887 Controls.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C TLS[63]).
3889 @param ECX MSR_IA32_VMX_PROCBASED_CTLS2 (0x0000048B)
3890 @param EAX Lower 32-bits of MSR value.
3891 @param EDX Upper 32-bits of MSR value.
3893 <b>Example usage</b>
3897 Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS2);
3899 @note MSR_IA32_VMX_PROCBASED_CTLS2 is defined as IA32_VMX_PROCBASED_CTLS2 in SDM.
3901 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B
3905 Capability Reporting Register of EPT and VPID (R/O) See Appendix A.10,
3906 "VPID and EPT Capabilities.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C
3907 TLS[63] && ( IA32_VMX_PROCBASED_C TLS2[33] IA32_VMX_PROCBASED_C TLS2[37]) ).
3909 @param ECX MSR_IA32_VMX_EPT_VPID_CAP (0x0000048C)
3910 @param EAX Lower 32-bits of MSR value.
3911 @param EDX Upper 32-bits of MSR value.
3913 <b>Example usage</b>
3917 Msr = AsmReadMsr64 (MSR_IA32_VMX_EPT_VPID_CAP);
3919 @note MSR_IA32_VMX_EPT_VPID_CAP is defined as IA32_VMX_EPT_VPID_CAP in SDM.
3921 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C
3925 Capability Reporting Register of Pinbased VM-execution Flex Controls (R/O)
3926 See Appendix A.3.1, "Pin-Based VMExecution Controls.". If (
3927 CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
3929 @param ECX MSR_IA32_VMX_TRUE_PINBASED_CTLS (0x0000048D)
3930 @param EAX Lower 32-bits of MSR value.
3931 @param EDX Upper 32-bits of MSR value.
3933 <b>Example usage</b>
3937 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PINBASED_CTLS);
3939 @note MSR_IA32_VMX_TRUE_PINBASED_CTLS is defined as IA32_VMX_TRUE_PINBASED_CTLS in SDM.
3941 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D
3945 Capability Reporting Register of Primary Processor-based VM-execution Flex
3946 Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution
3947 Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
3949 @param ECX MSR_IA32_VMX_TRUE_PROCBASED_CTLS (0x0000048E)
3950 @param EAX Lower 32-bits of MSR value.
3951 @param EDX Upper 32-bits of MSR value.
3953 <b>Example usage</b>
3957 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PROCBASED_CTLS);
3959 @note MSR_IA32_VMX_TRUE_PROCBASED_CTLS is defined as IA32_VMX_TRUE_PROCBASED_CTLS in SDM.
3961 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E
3965 Capability Reporting Register of VM-exit Flex Controls (R/O) See Appendix
3966 A.4, "VM-Exit Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
3968 @param ECX MSR_IA32_VMX_TRUE_EXIT_CTLS (0x0000048F)
3969 @param EAX Lower 32-bits of MSR value.
3970 @param EDX Upper 32-bits of MSR value.
3972 <b>Example usage</b>
3976 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_EXIT_CTLS);
3978 @note MSR_IA32_VMX_TRUE_EXIT_CTLS is defined as IA32_VMX_TRUE_EXIT_CTLS in SDM.
3980 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F
3984 Capability Reporting Register of VMentry Flex Controls (R/O) See Appendix
3985 A.5, "VM-Entry Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
3987 @param ECX MSR_IA32_VMX_TRUE_ENTRY_CTLS (0x00000490)
3988 @param EAX Lower 32-bits of MSR value.
3989 @param EDX Upper 32-bits of MSR value.
3991 <b>Example usage</b>
3995 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_ENTRY_CTLS);
3997 @note MSR_IA32_VMX_TRUE_ENTRY_CTLS is defined as IA32_VMX_TRUE_ENTRY_CTLS in SDM.
3999 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
4003 Capability Reporting Register of VMfunction Controls (R/O). If(
4004 CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
4006 @param ECX MSR_IA32_VMX_VMFUNC (0x00000491)
4007 @param EAX Lower 32-bits of MSR value.
4008 @param EDX Upper 32-bits of MSR value.
4010 <b>Example usage</b>
4014 Msr = AsmReadMsr64 (MSR_IA32_VMX_VMFUNC);
4016 @note MSR_IA32_VMX_VMFUNC is defined as IA32_VMX_VMFUNC in SDM.
4018 #define MSR_IA32_VMX_VMFUNC 0x00000491
4022 Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) &&
4023 IA32_PERF_CAPABILITIES[ 13] = 1.
4025 @param ECX MSR_IA32_A_PMCn
4026 @param EAX Lower 32-bits of MSR value.
4027 @param EDX Upper 32-bits of MSR value.
4029 <b>Example usage</b>
4033 Msr = AsmReadMsr64 (MSR_IA32_A_PMC0);
4034 AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr);
4036 @note MSR_IA32_A_PMC0 is defined as IA32_A_PMC0 in SDM.
4037 MSR_IA32_A_PMC1 is defined as IA32_A_PMC1 in SDM.
4038 MSR_IA32_A_PMC2 is defined as IA32_A_PMC2 in SDM.
4039 MSR_IA32_A_PMC3 is defined as IA32_A_PMC3 in SDM.
4040 MSR_IA32_A_PMC4 is defined as IA32_A_PMC4 in SDM.
4041 MSR_IA32_A_PMC5 is defined as IA32_A_PMC5 in SDM.
4042 MSR_IA32_A_PMC6 is defined as IA32_A_PMC6 in SDM.
4043 MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM.
4046 #define MSR_IA32_A_PMC0 0x000004C1
4047 #define MSR_IA32_A_PMC1 0x000004C2
4048 #define MSR_IA32_A_PMC2 0x000004C3
4049 #define MSR_IA32_A_PMC3 0x000004C4
4050 #define MSR_IA32_A_PMC4 0x000004C5
4051 #define MSR_IA32_A_PMC5 0x000004C6
4052 #define MSR_IA32_A_PMC6 0x000004C7
4053 #define MSR_IA32_A_PMC7 0x000004C8
4058 (R/W). If IA32_MCG_CAP.LMCE_P =1.
4060 @param ECX MSR_IA32_MCG_EXT_CTL (0x000004D0)
4061 @param EAX Lower 32-bits of MSR value.
4062 Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.
4063 @param EDX Upper 32-bits of MSR value.
4064 Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.
4066 <b>Example usage</b>
4068 MSR_IA32_MCG_EXT_CTL_REGISTER Msr;
4070 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL);
4071 AsmWriteMsr64 (MSR_IA32_MCG_EXT_CTL, Msr.Uint64);
4073 @note MSR_IA32_MCG_EXT_CTL is defined as IA32_MCG_EXT_CTL in SDM.
4075 #define MSR_IA32_MCG_EXT_CTL 0x000004D0
4078 MSR information returned for MSR index #MSR_IA32_MCG_EXT_CTL
4082 /// Individual bit fields
4086 /// [Bit 0] LMCE_EN.
4089 UINT32 Reserved1
:31;
4090 UINT32 Reserved2
:32;
4093 /// All bit fields as a 32-bit value
4097 /// All bit fields as a 64-bit value
4100 } MSR_IA32_MCG_EXT_CTL_REGISTER
;
4104 Status and SVN Threshold of SGX Support for ACM (RO). If CPUID.(EAX=07H,
4105 ECX=0H): EBX[2] = 1.
4107 @param ECX MSR_IA32_SGX_SVN_STATUS (0x00000500)
4108 @param EAX Lower 32-bits of MSR value.
4109 Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.
4110 @param EDX Upper 32-bits of MSR value.
4111 Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.
4113 <b>Example usage</b>
4115 MSR_IA32_SGX_SVN_STATUS_REGISTER Msr;
4117 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SGX_SVN_STATUS);
4119 @note MSR_IA32_SGX_SVN_STATUS is defined as IA32_SGX_SVN_STATUS in SDM.
4121 #define MSR_IA32_SGX_SVN_STATUS 0x00000500
4124 MSR information returned for MSR index #MSR_IA32_SGX_SVN_STATUS
4128 /// Individual bit fields
4132 /// [Bit 0] Lock. See Section 42.12.3, "Interactions with Authenticated
4133 /// Code Modules (ACMs)".
4136 UINT32 Reserved1
:15;
4138 /// [Bits 23:16] SGX_SVN_SINIT. See Section 42.12.3, "Interactions with
4139 /// Authenticated Code Modules (ACMs)".
4141 UINT32 SGX_SVN_SINIT
:8;
4143 UINT32 Reserved3
:32;
4146 /// All bit fields as a 32-bit value
4150 /// All bit fields as a 64-bit value
4153 } MSR_IA32_SGX_SVN_STATUS_REGISTER
;
4157 Trace Output Base Register (R/W). If ((CPUID.(EAX=07H, ECX=0):EBX[25] = 1)
4158 && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) (CPUID.(EAX=14H,ECX=0): ECX[2] = 1)
4161 @param ECX MSR_IA32_RTIT_OUTPUT_BASE (0x00000560)
4162 @param EAX Lower 32-bits of MSR value.
4163 Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.
4164 @param EDX Upper 32-bits of MSR value.
4165 Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.
4167 <b>Example usage</b>
4169 MSR_IA32_RTIT_OUTPUT_BASE_REGISTER Msr;
4171 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);
4172 AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_BASE, Msr.Uint64);
4174 @note MSR_IA32_RTIT_OUTPUT_BASE is defined as IA32_RTIT_OUTPUT_BASE in SDM.
4176 #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
4179 MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_BASE
4183 /// Individual bit fields
4188 /// [Bits 31:7] Base physical address.
4192 /// [Bits 63:32] Base physical address.
4197 /// All bit fields as a 64-bit value
4200 } MSR_IA32_RTIT_OUTPUT_BASE_REGISTER
;
4204 Trace Output Mask Pointers Register (R/W). If ((CPUID.(EAX=07H,
4205 ECX=0):EBX[25] = 1) && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1)
4206 (CPUID.(EAX=14H,ECX=0): ECX[2] = 1) ) ).
4208 @param ECX MSR_IA32_RTIT_OUTPUT_MASK_PTRS (0x00000561)
4209 @param EAX Lower 32-bits of MSR value.
4210 Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.
4211 @param EDX Upper 32-bits of MSR value.
4212 Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.
4214 <b>Example usage</b>
4216 MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER Msr;
4218 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS);
4219 AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS, Msr.Uint64);
4221 @note MSR_IA32_RTIT_OUTPUT_MASK_PTRS is defined as IA32_RTIT_OUTPUT_MASK_PTRS in SDM.
4223 #define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561
4226 MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_MASK_PTRS
4230 /// Individual bit fields
4235 /// [Bits 31:7] MaskOrTableOffset.
4237 UINT32 MaskOrTableOffset
:25;
4239 /// [Bits 63:32] Output Offset.
4241 UINT32 OutputOffset
:32;
4244 /// All bit fields as a 64-bit value
4247 } MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER
;
4251 Trace Control Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
4253 @param ECX MSR_IA32_RTIT_CTL (0x00000570)
4254 @param EAX Lower 32-bits of MSR value.
4255 Described by the type MSR_IA32_RTIT_CTL_REGISTER.
4256 @param EDX Upper 32-bits of MSR value.
4257 Described by the type MSR_IA32_RTIT_CTL_REGISTER.
4259 <b>Example usage</b>
4261 MSR_IA32_RTIT_CTL_REGISTER Msr;
4263 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
4264 AsmWriteMsr64 (MSR_IA32_RTIT_CTL, Msr.Uint64);
4266 @note MSR_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.
4268 #define MSR_IA32_RTIT_CTL 0x00000570
4271 MSR information returned for MSR index #MSR_IA32_RTIT_CTL
4275 /// Individual bit fields
4279 /// [Bit 0] TraceEn.
4283 /// [Bit 1] CYCEn. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
4296 /// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1).
4300 /// [Bit 7] CR3 filter.
4308 /// [Bit 9] MTCEn. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).
4316 /// [Bit 11] DisRETC.
4321 /// [Bit 13] BranchEn.
4325 /// [Bits 17:14] MTCFreq. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).
4330 /// [Bits 22:19] CYCThresh. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
4335 /// [Bits 27:24] PSBFreq. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
4340 /// [Bits 35:32] ADDR0_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0).
4344 /// [Bits 39:36] ADDR1_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 1).
4348 /// [Bits 43:40] ADDR2_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 2).
4352 /// [Bits 47:44] ADDR3_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3).
4355 UINT32 Reserved6
:16;
4358 /// All bit fields as a 64-bit value
4361 } MSR_IA32_RTIT_CTL_REGISTER
;
4365 Tracing Status Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
4367 @param ECX MSR_IA32_RTIT_STATUS (0x00000571)
4368 @param EAX Lower 32-bits of MSR value.
4369 Described by the type MSR_IA32_RTIT_STATUS_REGISTER.
4370 @param EDX Upper 32-bits of MSR value.
4371 Described by the type MSR_IA32_RTIT_STATUS_REGISTER.
4373 <b>Example usage</b>
4375 MSR_IA32_RTIT_STATUS_REGISTER Msr;
4377 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_STATUS);
4378 AsmWriteMsr64 (MSR_IA32_RTIT_STATUS, Msr.Uint64);
4380 @note MSR_IA32_RTIT_STATUS is defined as IA32_RTIT_STATUS in SDM.
4382 #define MSR_IA32_RTIT_STATUS 0x00000571
4385 MSR information returned for MSR index #MSR_IA32_RTIT_STATUS
4389 /// Individual bit fields
4393 /// [Bit 0] FilterEn, (writes ignored).
4394 /// If (CPUID.(EAX=07H, ECX=0):EBX[2] = 1).
4398 /// [Bit 1] ContexEn, (writes ignored).
4402 /// [Bit 2] TriggerEn, (writes ignored).
4411 /// [Bit 5] Stopped.
4414 UINT32 Reserved2
:26;
4416 /// [Bits 48:32] PacketByteCnt. If (CPUID.(EAX=07H, ECX=0):EBX[1] > 3).
4418 UINT32 PacketByteCnt
:17;
4419 UINT32 Reserved3
:15;
4422 /// All bit fields as a 64-bit value
4425 } MSR_IA32_RTIT_STATUS_REGISTER
;
4429 Trace Filter CR3 Match Register (R/W).
4430 If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
4432 @param ECX MSR_IA32_RTIT_CR3_MATCH (0x00000572)
4433 @param EAX Lower 32-bits of MSR value.
4434 Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.
4435 @param EDX Upper 32-bits of MSR value.
4436 Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.
4438 <b>Example usage</b>
4440 MSR_IA32_RTIT_CR3_MATCH_REGISTER Msr;
4442 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CR3_MATCH);
4443 AsmWriteMsr64 (MSR_IA32_RTIT_CR3_MATCH, Msr.Uint64);
4445 @note MSR_IA32_RTIT_CR3_MATCH is defined as IA32_RTIT_CR3_MATCH in SDM.
4447 #define MSR_IA32_RTIT_CR3_MATCH 0x00000572
4450 MSR information returned for MSR index #MSR_IA32_RTIT_CR3_MATCH
4454 /// Individual bit fields
4459 /// [Bits 31:5] CR3[63:5] value to match.
4463 /// [Bits 63:32] CR3[63:5] value to match.
4468 /// All bit fields as a 64-bit value
4471 } MSR_IA32_RTIT_CR3_MATCH_REGISTER
;
4475 Region n Start Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).
4477 @param ECX MSR_IA32_RTIT_ADDRn_A
4478 @param EAX Lower 32-bits of MSR value.
4479 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
4480 @param EDX Upper 32-bits of MSR value.
4481 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
4483 <b>Example usage</b>
4485 MSR_IA32_RTIT_ADDR_REGISTER Msr;
4487 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_A);
4488 AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_A, Msr.Uint64);
4490 @note MSR_IA32_RTIT_ADDR0_A is defined as IA32_RTIT_ADDR0_A in SDM.
4491 MSR_IA32_RTIT_ADDR1_A is defined as IA32_RTIT_ADDR1_A in SDM.
4492 MSR_IA32_RTIT_ADDR2_A is defined as IA32_RTIT_ADDR2_A in SDM.
4493 MSR_IA32_RTIT_ADDR3_A is defined as IA32_RTIT_ADDR3_A in SDM.
4496 #define MSR_IA32_RTIT_ADDR0_A 0x00000580
4497 #define MSR_IA32_RTIT_ADDR1_A 0x00000582
4498 #define MSR_IA32_RTIT_ADDR2_A 0x00000584
4499 #define MSR_IA32_RTIT_ADDR3_A 0x00000586
4504 Region n End Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).
4506 @param ECX MSR_IA32_RTIT_ADDRn_B
4507 @param EAX Lower 32-bits of MSR value.
4508 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
4509 @param EDX Upper 32-bits of MSR value.
4510 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
4512 <b>Example usage</b>
4514 MSR_IA32_RTIT_ADDR_REGISTER Msr;
4516 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_B);
4517 AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_B, Msr.Uint64);
4519 @note MSR_IA32_RTIT_ADDR0_B is defined as IA32_RTIT_ADDR0_B in SDM.
4520 MSR_IA32_RTIT_ADDR1_B is defined as IA32_RTIT_ADDR1_B in SDM.
4521 MSR_IA32_RTIT_ADDR2_B is defined as IA32_RTIT_ADDR2_B in SDM.
4522 MSR_IA32_RTIT_ADDR3_B is defined as IA32_RTIT_ADDR3_B in SDM.
4525 #define MSR_IA32_RTIT_ADDR0_B 0x00000581
4526 #define MSR_IA32_RTIT_ADDR1_B 0x00000583
4527 #define MSR_IA32_RTIT_ADDR2_B 0x00000585
4528 #define MSR_IA32_RTIT_ADDR3_B 0x00000587
4533 MSR information returned for MSR indexes
4534 #MSR_IA32_RTIT_ADDR0_A to #MSR_IA32_RTIT_ADDR3_A and
4535 #MSR_IA32_RTIT_ADDR0_B to #MSR_IA32_RTIT_ADDR3_B
4539 /// Individual bit fields
4543 /// [Bits 31:0] Virtual Address.
4545 UINT32 VirtualAddress
:32;
4547 /// [Bits 47:32] Virtual Address.
4549 UINT32 VirtualAddressHi
:16;
4551 /// [Bits 63:48] SignExt_VA.
4553 UINT32 SignExt_VA
:16;
4556 /// All bit fields as a 64-bit value
4559 } MSR_IA32_RTIT_ADDR_REGISTER
;
4563 DS Save Area (R/W) Points to the linear address of the first byte of the DS
4564 buffer management area, which is used to manage the BTS and PEBS buffers.
4565 See Section 18.12.4, "Debug Store (DS) Mechanism.". If( CPUID.01H:EDX.DS[21]
4568 [Bits 31..0] The linear address of the first byte of the DS buffer
4569 management area, if not in IA-32e mode.
4571 [Bits 63..0] The linear address of the first byte of the DS buffer
4572 management area, if IA-32e mode is active.
4574 @param ECX MSR_IA32_DS_AREA (0x00000600)
4575 @param EAX Lower 32-bits of MSR value.
4576 Described by the type MSR_IA32_DS_AREA_REGISTER.
4577 @param EDX Upper 32-bits of MSR value.
4578 Described by the type MSR_IA32_DS_AREA_REGISTER.
4580 <b>Example usage</b>
4584 Msr = AsmReadMsr64 (MSR_IA32_DS_AREA);
4585 AsmWriteMsr64 (MSR_IA32_DS_AREA, Msr);
4587 @note MSR_IA32_DS_AREA is defined as IA32_DS_AREA in SDM.
4589 #define MSR_IA32_DS_AREA 0x00000600
4593 TSC Target of Local APIC's TSC Deadline Mode (R/W). If CPUID.01H:ECX.[24] =
4596 @param ECX MSR_IA32_TSC_DEADLINE (0x000006E0)
4597 @param EAX Lower 32-bits of MSR value.
4598 @param EDX Upper 32-bits of MSR value.
4600 <b>Example usage</b>
4604 Msr = AsmReadMsr64 (MSR_IA32_TSC_DEADLINE);
4605 AsmWriteMsr64 (MSR_IA32_TSC_DEADLINE, Msr);
4607 @note MSR_IA32_TSC_DEADLINE is defined as IA32_TSC_DEADLINE in SDM.
4609 #define MSR_IA32_TSC_DEADLINE 0x000006E0
4613 Enable/disable HWP (R/W). If CPUID.06H:EAX.[7] = 1.
4615 @param ECX MSR_IA32_PM_ENABLE (0x00000770)
4616 @param EAX Lower 32-bits of MSR value.
4617 Described by the type MSR_IA32_PM_ENABLE_REGISTER.
4618 @param EDX Upper 32-bits of MSR value.
4619 Described by the type MSR_IA32_PM_ENABLE_REGISTER.
4621 <b>Example usage</b>
4623 MSR_IA32_PM_ENABLE_REGISTER Msr;
4625 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_ENABLE);
4626 AsmWriteMsr64 (MSR_IA32_PM_ENABLE, Msr.Uint64);
4628 @note MSR_IA32_PM_ENABLE is defined as IA32_PM_ENABLE in SDM.
4630 #define MSR_IA32_PM_ENABLE 0x00000770
4633 MSR information returned for MSR index #MSR_IA32_PM_ENABLE
4637 /// Individual bit fields
4641 /// [Bit 0] HWP_ENABLE (R/W1-Once). See Section 14.4.2, "Enabling HWP". If
4642 /// CPUID.06H:EAX.[7] = 1.
4644 UINT32 HWP_ENABLE
:1;
4645 UINT32 Reserved1
:31;
4646 UINT32 Reserved2
:32;
4649 /// All bit fields as a 32-bit value
4653 /// All bit fields as a 64-bit value
4656 } MSR_IA32_PM_ENABLE_REGISTER
;
4660 HWP Performance Range Enumeration (RO). If CPUID.06H:EAX.[7] = 1.
4662 @param ECX MSR_IA32_HWP_CAPABILITIES (0x00000771)
4663 @param EAX Lower 32-bits of MSR value.
4664 Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.
4665 @param EDX Upper 32-bits of MSR value.
4666 Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.
4668 <b>Example usage</b>
4670 MSR_IA32_HWP_CAPABILITIES_REGISTER Msr;
4672 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_CAPABILITIES);
4674 @note MSR_IA32_HWP_CAPABILITIES is defined as IA32_HWP_CAPABILITIES in SDM.
4676 #define MSR_IA32_HWP_CAPABILITIES 0x00000771
4679 MSR information returned for MSR index #MSR_IA32_HWP_CAPABILITIES
4683 /// Individual bit fields
4687 /// [Bits 7:0] Highest_Performance See Section 14.4.3, "HWP Performance
4688 /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
4690 UINT32 Highest_Performance
:8;
4692 /// [Bits 15:8] Guaranteed_Performance See Section 14.4.3, "HWP
4693 /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
4695 UINT32 Guaranteed_Performance
:8;
4697 /// [Bits 23:16] Most_Efficient_Performance See Section 14.4.3, "HWP
4698 /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
4700 UINT32 Most_Efficient_Performance
:8;
4702 /// [Bits 31:24] Lowest_Performance See Section 14.4.3, "HWP Performance
4703 /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
4705 UINT32 Lowest_Performance
:8;
4709 /// All bit fields as a 32-bit value
4713 /// All bit fields as a 64-bit value
4716 } MSR_IA32_HWP_CAPABILITIES_REGISTER
;
4720 Power Management Control Hints for All Logical Processors in a Package
4721 (R/W). If CPUID.06H:EAX.[11] = 1.
4723 @param ECX MSR_IA32_HWP_REQUEST_PKG (0x00000772)
4724 @param EAX Lower 32-bits of MSR value.
4725 Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.
4726 @param EDX Upper 32-bits of MSR value.
4727 Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.
4729 <b>Example usage</b>
4731 MSR_IA32_HWP_REQUEST_PKG_REGISTER Msr;
4733 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST_PKG);
4734 AsmWriteMsr64 (MSR_IA32_HWP_REQUEST_PKG, Msr.Uint64);
4736 @note MSR_IA32_HWP_REQUEST_PKG is defined as IA32_HWP_REQUEST_PKG in SDM.
4738 #define MSR_IA32_HWP_REQUEST_PKG 0x00000772
4741 MSR information returned for MSR index #MSR_IA32_HWP_REQUEST_PKG
4745 /// Individual bit fields
4749 /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If
4750 /// CPUID.06H:EAX.[11] = 1.
4752 UINT32 Minimum_Performance
:8;
4754 /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If
4755 /// CPUID.06H:EAX.[11] = 1.
4757 UINT32 Maximum_Performance
:8;
4759 /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".
4760 /// If CPUID.06H:EAX.[11] = 1.
4762 UINT32 Desired_Performance
:8;
4764 /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,
4765 /// "Managing HWP". If CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[10] = 1.
4767 UINT32 Energy_Performance_Preference
:8;
4769 /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If
4770 /// CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[9] = 1.
4772 UINT32 Activity_Window
:10;
4776 /// All bit fields as a 64-bit value
4779 } MSR_IA32_HWP_REQUEST_PKG_REGISTER
;
4783 Control HWP Native Interrupts (R/W). If CPUID.06H:EAX.[8] = 1.
4785 @param ECX MSR_IA32_HWP_INTERRUPT (0x00000773)
4786 @param EAX Lower 32-bits of MSR value.
4787 Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.
4788 @param EDX Upper 32-bits of MSR value.
4789 Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.
4791 <b>Example usage</b>
4793 MSR_IA32_HWP_INTERRUPT_REGISTER Msr;
4795 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_INTERRUPT);
4796 AsmWriteMsr64 (MSR_IA32_HWP_INTERRUPT, Msr.Uint64);
4798 @note MSR_IA32_HWP_INTERRUPT is defined as IA32_HWP_INTERRUPT in SDM.
4800 #define MSR_IA32_HWP_INTERRUPT 0x00000773
4803 MSR information returned for MSR index #MSR_IA32_HWP_INTERRUPT
4807 /// Individual bit fields
4811 /// [Bit 0] EN_Guaranteed_Performance_Change. See Section 14.4.6, "HWP
4812 /// Notifications". If CPUID.06H:EAX.[8] = 1.
4814 UINT32 EN_Guaranteed_Performance_Change
:1;
4816 /// [Bit 1] EN_Excursion_Minimum. See Section 14.4.6, "HWP Notifications".
4817 /// If CPUID.06H:EAX.[8] = 1.
4819 UINT32 EN_Excursion_Minimum
:1;
4820 UINT32 Reserved1
:30;
4821 UINT32 Reserved2
:32;
4824 /// All bit fields as a 32-bit value
4828 /// All bit fields as a 64-bit value
4831 } MSR_IA32_HWP_INTERRUPT_REGISTER
;
4835 Power Management Control Hints to a Logical Processor (R/W). If
4836 CPUID.06H:EAX.[7] = 1.
4838 @param ECX MSR_IA32_HWP_REQUEST (0x00000774)
4839 @param EAX Lower 32-bits of MSR value.
4840 Described by the type MSR_IA32_HWP_REQUEST_REGISTER.
4841 @param EDX Upper 32-bits of MSR value.
4842 Described by the type MSR_IA32_HWP_REQUEST_REGISTER.
4844 <b>Example usage</b>
4846 MSR_IA32_HWP_REQUEST_REGISTER Msr;
4848 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST);
4849 AsmWriteMsr64 (MSR_IA32_HWP_REQUEST, Msr.Uint64);
4851 @note MSR_IA32_HWP_REQUEST is defined as IA32_HWP_REQUEST in SDM.
4853 #define MSR_IA32_HWP_REQUEST 0x00000774
4856 MSR information returned for MSR index #MSR_IA32_HWP_REQUEST
4860 /// Individual bit fields
4864 /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If
4865 /// CPUID.06H:EAX.[7] = 1.
4867 UINT32 Minimum_Performance
:8;
4869 /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If
4870 /// CPUID.06H:EAX.[7] = 1.
4872 UINT32 Maximum_Performance
:8;
4874 /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".
4875 /// If CPUID.06H:EAX.[7] = 1.
4877 UINT32 Desired_Performance
:8;
4879 /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,
4880 /// "Managing HWP". If CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[10] = 1.
4882 UINT32 Energy_Performance_Preference
:8;
4884 /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If
4885 /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[9] = 1.
4887 UINT32 Activity_Window
:10;
4889 /// [Bit 42] Package_Control See Section 14.4.4, "Managing HWP". If
4890 /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[11] = 1.
4892 UINT32 Package_Control
:1;
4896 /// All bit fields as a 64-bit value
4899 } MSR_IA32_HWP_REQUEST_REGISTER
;
4903 Log bits indicating changes to Guaranteed & excursions to Minimum (R/W). If
4904 CPUID.06H:EAX.[7] = 1.
4906 @param ECX MSR_IA32_HWP_STATUS (0x00000777)
4907 @param EAX Lower 32-bits of MSR value.
4908 Described by the type MSR_IA32_HWP_STATUS_REGISTER.
4909 @param EDX Upper 32-bits of MSR value.
4910 Described by the type MSR_IA32_HWP_STATUS_REGISTER.
4912 <b>Example usage</b>
4914 MSR_IA32_HWP_STATUS_REGISTER Msr;
4916 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_STATUS);
4917 AsmWriteMsr64 (MSR_IA32_HWP_STATUS, Msr.Uint64);
4919 @note MSR_IA32_HWP_STATUS is defined as IA32_HWP_STATUS in SDM.
4921 #define MSR_IA32_HWP_STATUS 0x00000777
4924 MSR information returned for MSR index #MSR_IA32_HWP_STATUS
4928 /// Individual bit fields
4932 /// [Bit 0] Guaranteed_Performance_Change (R/WC0). See Section 14.4.5,
4933 /// "HWP Feedback". If CPUID.06H:EAX.[7] = 1.
4935 UINT32 Guaranteed_Performance_Change
:1;
4938 /// [Bit 2] Excursion_To_Minimum (R/WC0). See Section 14.4.5, "HWP
4939 /// Feedback". If CPUID.06H:EAX.[7] = 1.
4941 UINT32 Excursion_To_Minimum
:1;
4942 UINT32 Reserved2
:29;
4943 UINT32 Reserved3
:32;
4946 /// All bit fields as a 32-bit value
4950 /// All bit fields as a 64-bit value
4953 } MSR_IA32_HWP_STATUS_REGISTER
;
4957 x2APIC ID Register (R/O) See x2APIC Specification. If CPUID.01H:ECX[21] = 1
4958 && IA32_APIC_BASE.[10] = 1.
4960 @param ECX MSR_IA32_X2APIC_APICID (0x00000802)
4961 @param EAX Lower 32-bits of MSR value.
4962 @param EDX Upper 32-bits of MSR value.
4964 <b>Example usage</b>
4968 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_APICID);
4970 @note MSR_IA32_X2APIC_APICID is defined as IA32_X2APIC_APICID in SDM.
4972 #define MSR_IA32_X2APIC_APICID 0x00000802
4976 x2APIC Version Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
4977 IA32_APIC_BASE.[10] = 1.
4979 @param ECX MSR_IA32_X2APIC_VERSION (0x00000803)
4980 @param EAX Lower 32-bits of MSR value.
4981 @param EDX Upper 32-bits of MSR value.
4983 <b>Example usage</b>
4987 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_VERSION);
4989 @note MSR_IA32_X2APIC_VERSION is defined as IA32_X2APIC_VERSION in SDM.
4991 #define MSR_IA32_X2APIC_VERSION 0x00000803
4995 x2APIC Task Priority Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
4996 IA32_APIC_BASE.[10] = 1.
4998 @param ECX MSR_IA32_X2APIC_TPR (0x00000808)
4999 @param EAX Lower 32-bits of MSR value.
5000 @param EDX Upper 32-bits of MSR value.
5002 <b>Example usage</b>
5006 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TPR);
5007 AsmWriteMsr64 (MSR_IA32_X2APIC_TPR, Msr);
5009 @note MSR_IA32_X2APIC_TPR is defined as IA32_X2APIC_TPR in SDM.
5011 #define MSR_IA32_X2APIC_TPR 0x00000808
5015 x2APIC Processor Priority Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
5016 IA32_APIC_BASE.[10] = 1.
5018 @param ECX MSR_IA32_X2APIC_PPR (0x0000080A)
5019 @param EAX Lower 32-bits of MSR value.
5020 @param EDX Upper 32-bits of MSR value.
5022 <b>Example usage</b>
5026 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_PPR);
5028 @note MSR_IA32_X2APIC_PPR is defined as IA32_X2APIC_PPR in SDM.
5030 #define MSR_IA32_X2APIC_PPR 0x0000080A
5034 x2APIC EOI Register (W/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10]
5037 @param ECX MSR_IA32_X2APIC_EOI (0x0000080B)
5038 @param EAX Lower 32-bits of MSR value.
5039 @param EDX Upper 32-bits of MSR value.
5041 <b>Example usage</b>
5046 AsmWriteMsr64 (MSR_IA32_X2APIC_EOI, Msr);
5048 @note MSR_IA32_X2APIC_EOI is defined as IA32_X2APIC_EOI in SDM.
5050 #define MSR_IA32_X2APIC_EOI 0x0000080B
5054 x2APIC Logical Destination Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
5055 IA32_APIC_BASE.[10] = 1.
5057 @param ECX MSR_IA32_X2APIC_LDR (0x0000080D)
5058 @param EAX Lower 32-bits of MSR value.
5059 @param EDX Upper 32-bits of MSR value.
5061 <b>Example usage</b>
5065 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LDR);
5067 @note MSR_IA32_X2APIC_LDR is defined as IA32_X2APIC_LDR in SDM.
5069 #define MSR_IA32_X2APIC_LDR 0x0000080D
5073 x2APIC Spurious Interrupt Vector Register (R/W). If CPUID.01H:ECX.[21] = 1
5074 && IA32_APIC_BASE.[10] = 1.
5076 @param ECX MSR_IA32_X2APIC_SIVR (0x0000080F)
5077 @param EAX Lower 32-bits of MSR value.
5078 @param EDX Upper 32-bits of MSR value.
5080 <b>Example usage</b>
5084 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_SIVR);
5085 AsmWriteMsr64 (MSR_IA32_X2APIC_SIVR, Msr);
5087 @note MSR_IA32_X2APIC_SIVR is defined as IA32_X2APIC_SIVR in SDM.
5089 #define MSR_IA32_X2APIC_SIVR 0x0000080F
5093 x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O).
5094 If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
5096 @param ECX MSR_IA32_X2APIC_ISRn
5097 @param EAX Lower 32-bits of MSR value.
5098 @param EDX Upper 32-bits of MSR value.
5100 <b>Example usage</b>
5104 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0);
5106 @note MSR_IA32_X2APIC_ISR0 is defined as IA32_X2APIC_ISR0 in SDM.
5107 MSR_IA32_X2APIC_ISR1 is defined as IA32_X2APIC_ISR1 in SDM.
5108 MSR_IA32_X2APIC_ISR2 is defined as IA32_X2APIC_ISR2 in SDM.
5109 MSR_IA32_X2APIC_ISR3 is defined as IA32_X2APIC_ISR3 in SDM.
5110 MSR_IA32_X2APIC_ISR4 is defined as IA32_X2APIC_ISR4 in SDM.
5111 MSR_IA32_X2APIC_ISR5 is defined as IA32_X2APIC_ISR5 in SDM.
5112 MSR_IA32_X2APIC_ISR6 is defined as IA32_X2APIC_ISR6 in SDM.
5113 MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM.
5116 #define MSR_IA32_X2APIC_ISR0 0x00000810
5117 #define MSR_IA32_X2APIC_ISR1 0x00000811
5118 #define MSR_IA32_X2APIC_ISR2 0x00000812
5119 #define MSR_IA32_X2APIC_ISR3 0x00000813
5120 #define MSR_IA32_X2APIC_ISR4 0x00000814
5121 #define MSR_IA32_X2APIC_ISR5 0x00000815
5122 #define MSR_IA32_X2APIC_ISR6 0x00000816
5123 #define MSR_IA32_X2APIC_ISR7 0x00000817
5128 x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O).
5129 If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
5131 @param ECX MSR_IA32_X2APIC_TMRn
5132 @param EAX Lower 32-bits of MSR value.
5133 @param EDX Upper 32-bits of MSR value.
5135 <b>Example usage</b>
5139 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0);
5141 @note MSR_IA32_X2APIC_TMR0 is defined as IA32_X2APIC_TMR0 in SDM.
5142 MSR_IA32_X2APIC_TMR1 is defined as IA32_X2APIC_TMR1 in SDM.
5143 MSR_IA32_X2APIC_TMR2 is defined as IA32_X2APIC_TMR2 in SDM.
5144 MSR_IA32_X2APIC_TMR3 is defined as IA32_X2APIC_TMR3 in SDM.
5145 MSR_IA32_X2APIC_TMR4 is defined as IA32_X2APIC_TMR4 in SDM.
5146 MSR_IA32_X2APIC_TMR5 is defined as IA32_X2APIC_TMR5 in SDM.
5147 MSR_IA32_X2APIC_TMR6 is defined as IA32_X2APIC_TMR6 in SDM.
5148 MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM.
5151 #define MSR_IA32_X2APIC_TMR0 0x00000818
5152 #define MSR_IA32_X2APIC_TMR1 0x00000819
5153 #define MSR_IA32_X2APIC_TMR2 0x0000081A
5154 #define MSR_IA32_X2APIC_TMR3 0x0000081B
5155 #define MSR_IA32_X2APIC_TMR4 0x0000081C
5156 #define MSR_IA32_X2APIC_TMR5 0x0000081D
5157 #define MSR_IA32_X2APIC_TMR6 0x0000081E
5158 #define MSR_IA32_X2APIC_TMR7 0x0000081F
5163 x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O).
5164 If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
5166 @param ECX MSR_IA32_X2APIC_IRRn
5167 @param EAX Lower 32-bits of MSR value.
5168 @param EDX Upper 32-bits of MSR value.
5170 <b>Example usage</b>
5174 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0);
5176 @note MSR_IA32_X2APIC_IRR0 is defined as IA32_X2APIC_IRR0 in SDM.
5177 MSR_IA32_X2APIC_IRR1 is defined as IA32_X2APIC_IRR1 in SDM.
5178 MSR_IA32_X2APIC_IRR2 is defined as IA32_X2APIC_IRR2 in SDM.
5179 MSR_IA32_X2APIC_IRR3 is defined as IA32_X2APIC_IRR3 in SDM.
5180 MSR_IA32_X2APIC_IRR4 is defined as IA32_X2APIC_IRR4 in SDM.
5181 MSR_IA32_X2APIC_IRR5 is defined as IA32_X2APIC_IRR5 in SDM.
5182 MSR_IA32_X2APIC_IRR6 is defined as IA32_X2APIC_IRR6 in SDM.
5183 MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM.
5186 #define MSR_IA32_X2APIC_IRR0 0x00000820
5187 #define MSR_IA32_X2APIC_IRR1 0x00000821
5188 #define MSR_IA32_X2APIC_IRR2 0x00000822
5189 #define MSR_IA32_X2APIC_IRR3 0x00000823
5190 #define MSR_IA32_X2APIC_IRR4 0x00000824
5191 #define MSR_IA32_X2APIC_IRR5 0x00000825
5192 #define MSR_IA32_X2APIC_IRR6 0x00000826
5193 #define MSR_IA32_X2APIC_IRR7 0x00000827
5198 x2APIC Error Status Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5199 IA32_APIC_BASE.[10] = 1.
5201 @param ECX MSR_IA32_X2APIC_ESR (0x00000828)
5202 @param EAX Lower 32-bits of MSR value.
5203 @param EDX Upper 32-bits of MSR value.
5205 <b>Example usage</b>
5209 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ESR);
5210 AsmWriteMsr64 (MSR_IA32_X2APIC_ESR, Msr);
5212 @note MSR_IA32_X2APIC_ESR is defined as IA32_X2APIC_ESR in SDM.
5214 #define MSR_IA32_X2APIC_ESR 0x00000828
5218 x2APIC LVT Corrected Machine Check Interrupt Register (R/W). If
5219 CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
5221 @param ECX MSR_IA32_X2APIC_LVT_CMCI (0x0000082F)
5222 @param EAX Lower 32-bits of MSR value.
5223 @param EDX Upper 32-bits of MSR value.
5225 <b>Example usage</b>
5229 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_CMCI);
5230 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_CMCI, Msr);
5232 @note MSR_IA32_X2APIC_LVT_CMCI is defined as IA32_X2APIC_LVT_CMCI in SDM.
5234 #define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F
5238 x2APIC Interrupt Command Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5239 IA32_APIC_BASE.[10] = 1.
5241 @param ECX MSR_IA32_X2APIC_ICR (0x00000830)
5242 @param EAX Lower 32-bits of MSR value.
5243 @param EDX Upper 32-bits of MSR value.
5245 <b>Example usage</b>
5249 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ICR);
5250 AsmWriteMsr64 (MSR_IA32_X2APIC_ICR, Msr);
5252 @note MSR_IA32_X2APIC_ICR is defined as IA32_X2APIC_ICR in SDM.
5254 #define MSR_IA32_X2APIC_ICR 0x00000830
5258 x2APIC LVT Timer Interrupt Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5259 IA32_APIC_BASE.[10] = 1.
5261 @param ECX MSR_IA32_X2APIC_LVT_TIMER (0x00000832)
5262 @param EAX Lower 32-bits of MSR value.
5263 @param EDX Upper 32-bits of MSR value.
5265 <b>Example usage</b>
5269 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_TIMER);
5270 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_TIMER, Msr);
5272 @note MSR_IA32_X2APIC_LVT_TIMER is defined as IA32_X2APIC_LVT_TIMER in SDM.
5274 #define MSR_IA32_X2APIC_LVT_TIMER 0x00000832
5278 x2APIC LVT Thermal Sensor Interrupt Register (R/W). If CPUID.01H:ECX.[21] =
5279 1 && IA32_APIC_BASE.[10] = 1.
5281 @param ECX MSR_IA32_X2APIC_LVT_THERMAL (0x00000833)
5282 @param EAX Lower 32-bits of MSR value.
5283 @param EDX Upper 32-bits of MSR value.
5285 <b>Example usage</b>
5289 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_THERMAL);
5290 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_THERMAL, Msr);
5292 @note MSR_IA32_X2APIC_LVT_THERMAL is defined as IA32_X2APIC_LVT_THERMAL in SDM.
5294 #define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833
5298 x2APIC LVT Performance Monitor Interrupt Register (R/W). If
5299 CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
5301 @param ECX MSR_IA32_X2APIC_LVT_PMI (0x00000834)
5302 @param EAX Lower 32-bits of MSR value.
5303 @param EDX Upper 32-bits of MSR value.
5305 <b>Example usage</b>
5309 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_PMI);
5310 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_PMI, Msr);
5312 @note MSR_IA32_X2APIC_LVT_PMI is defined as IA32_X2APIC_LVT_PMI in SDM.
5314 #define MSR_IA32_X2APIC_LVT_PMI 0x00000834
5318 x2APIC LVT LINT0 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5319 IA32_APIC_BASE.[10] = 1.
5321 @param ECX MSR_IA32_X2APIC_LVT_LINT0 (0x00000835)
5322 @param EAX Lower 32-bits of MSR value.
5323 @param EDX Upper 32-bits of MSR value.
5325 <b>Example usage</b>
5329 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT0);
5330 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT0, Msr);
5332 @note MSR_IA32_X2APIC_LVT_LINT0 is defined as IA32_X2APIC_LVT_LINT0 in SDM.
5334 #define MSR_IA32_X2APIC_LVT_LINT0 0x00000835
5338 x2APIC LVT LINT1 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5339 IA32_APIC_BASE.[10] = 1.
5341 @param ECX MSR_IA32_X2APIC_LVT_LINT1 (0x00000836)
5342 @param EAX Lower 32-bits of MSR value.
5343 @param EDX Upper 32-bits of MSR value.
5345 <b>Example usage</b>
5349 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT1);
5350 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT1, Msr);
5352 @note MSR_IA32_X2APIC_LVT_LINT1 is defined as IA32_X2APIC_LVT_LINT1 in SDM.
5354 #define MSR_IA32_X2APIC_LVT_LINT1 0x00000836
5358 x2APIC LVT Error Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5359 IA32_APIC_BASE.[10] = 1.
5361 @param ECX MSR_IA32_X2APIC_LVT_ERROR (0x00000837)
5362 @param EAX Lower 32-bits of MSR value.
5363 @param EDX Upper 32-bits of MSR value.
5365 <b>Example usage</b>
5369 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_ERROR);
5370 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_ERROR, Msr);
5372 @note MSR_IA32_X2APIC_LVT_ERROR is defined as IA32_X2APIC_LVT_ERROR in SDM.
5374 #define MSR_IA32_X2APIC_LVT_ERROR 0x00000837
5378 x2APIC Initial Count Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5379 IA32_APIC_BASE.[10] = 1.
5381 @param ECX MSR_IA32_X2APIC_INIT_COUNT (0x00000838)
5382 @param EAX Lower 32-bits of MSR value.
5383 @param EDX Upper 32-bits of MSR value.
5385 <b>Example usage</b>
5389 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_INIT_COUNT);
5390 AsmWriteMsr64 (MSR_IA32_X2APIC_INIT_COUNT, Msr);
5392 @note MSR_IA32_X2APIC_INIT_COUNT is defined as IA32_X2APIC_INIT_COUNT in SDM.
5394 #define MSR_IA32_X2APIC_INIT_COUNT 0x00000838
5398 x2APIC Current Count Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
5399 IA32_APIC_BASE.[10] = 1.
5401 @param ECX MSR_IA32_X2APIC_CUR_COUNT (0x00000839)
5402 @param EAX Lower 32-bits of MSR value.
5403 @param EDX Upper 32-bits of MSR value.
5405 <b>Example usage</b>
5409 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_CUR_COUNT);
5411 @note MSR_IA32_X2APIC_CUR_COUNT is defined as IA32_X2APIC_CUR_COUNT in SDM.
5413 #define MSR_IA32_X2APIC_CUR_COUNT 0x00000839
5417 x2APIC Divide Configuration Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5418 IA32_APIC_BASE.[10] = 1.
5420 @param ECX MSR_IA32_X2APIC_DIV_CONF (0x0000083E)
5421 @param EAX Lower 32-bits of MSR value.
5422 @param EDX Upper 32-bits of MSR value.
5424 <b>Example usage</b>
5428 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_DIV_CONF);
5429 AsmWriteMsr64 (MSR_IA32_X2APIC_DIV_CONF, Msr);
5431 @note MSR_IA32_X2APIC_DIV_CONF is defined as IA32_X2APIC_DIV_CONF in SDM.
5433 #define MSR_IA32_X2APIC_DIV_CONF 0x0000083E
5437 x2APIC Self IPI Register (W/O). If CPUID.01H:ECX.[21] = 1 &&
5438 IA32_APIC_BASE.[10] = 1.
5440 @param ECX MSR_IA32_X2APIC_SELF_IPI (0x0000083F)
5441 @param EAX Lower 32-bits of MSR value.
5442 @param EDX Upper 32-bits of MSR value.
5444 <b>Example usage</b>
5449 AsmWriteMsr64 (MSR_IA32_X2APIC_SELF_IPI, Msr);
5451 @note MSR_IA32_X2APIC_SELF_IPI is defined as IA32_X2APIC_SELF_IPI in SDM.
5453 #define MSR_IA32_X2APIC_SELF_IPI 0x0000083F
5457 Silicon Debug Feature Control (R/W). If CPUID.01H:ECX.[11] = 1.
5459 @param ECX MSR_IA32_DEBUG_INTERFACE (0x00000C80)
5460 @param EAX Lower 32-bits of MSR value.
5461 Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.
5462 @param EDX Upper 32-bits of MSR value.
5463 Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.
5465 <b>Example usage</b>
5467 MSR_IA32_DEBUG_INTERFACE_REGISTER Msr;
5469 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUG_INTERFACE);
5470 AsmWriteMsr64 (MSR_IA32_DEBUG_INTERFACE, Msr.Uint64);
5472 @note MSR_IA32_DEBUG_INTERFACE is defined as IA32_DEBUG_INTERFACE in SDM.
5474 #define MSR_IA32_DEBUG_INTERFACE 0x00000C80
5477 MSR information returned for MSR index #MSR_IA32_DEBUG_INTERFACE
5481 /// Individual bit fields
5485 /// [Bit 0] Enable (R/W) BIOS set 1 to enable Silicon debug features.
5486 /// Default is 0. If CPUID.01H:ECX.[11] = 1.
5489 UINT32 Reserved1
:29;
5491 /// [Bit 30] Lock (R/W): If 1, locks any further change to the MSR. The
5492 /// lock bit is set automatically on the first SMI assertion even if not
5493 /// explicitly set by BIOS. Default is 0. If CPUID.01H:ECX.[11] = 1.
5497 /// [Bit 31] Debug Occurred (R/O): This "sticky bit" is set by hardware to
5498 /// indicate the status of bit 0. Default is 0. If CPUID.01H:ECX.[11] = 1.
5500 UINT32 DebugOccurred
:1;
5501 UINT32 Reserved2
:32;
5504 /// All bit fields as a 32-bit value
5508 /// All bit fields as a 64-bit value
5511 } MSR_IA32_DEBUG_INTERFACE_REGISTER
;
5515 L3 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=1):ECX.[2] = 1 ).
5517 @param ECX MSR_IA32_L3_QOS_CFG (0x00000C81)
5518 @param EAX Lower 32-bits of MSR value.
5519 Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.
5520 @param EDX Upper 32-bits of MSR value.
5521 Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.
5523 <b>Example usage</b>
5525 MSR_IA32_L3_QOS_CFG_REGISTER Msr;
5527 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L3_QOS_CFG);
5528 AsmWriteMsr64 (MSR_IA32_L3_QOS_CFG, Msr.Uint64);
5530 @note MSR_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.
5532 #define MSR_IA32_L3_QOS_CFG 0x00000C81
5535 MSR information returned for MSR index #MSR_IA32_L3_QOS_CFG
5539 /// Individual bit fields
5543 /// [Bit 0] Enable (R/W) Set 1 to enable L3 CAT masks and COS to operate
5544 /// in Code and Data Prioritization (CDP) mode.
5547 UINT32 Reserved1
:31;
5548 UINT32 Reserved2
:32;
5551 /// All bit fields as a 32-bit value
5555 /// All bit fields as a 64-bit value
5558 } MSR_IA32_L3_QOS_CFG_REGISTER
;
5562 Monitoring Event Select Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12]
5565 @param ECX MSR_IA32_QM_EVTSEL (0x00000C8D)
5566 @param EAX Lower 32-bits of MSR value.
5567 Described by the type MSR_IA32_QM_EVTSEL_REGISTER.
5568 @param EDX Upper 32-bits of MSR value.
5569 Described by the type MSR_IA32_QM_EVTSEL_REGISTER.
5571 <b>Example usage</b>
5573 MSR_IA32_QM_EVTSEL_REGISTER Msr;
5575 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_EVTSEL);
5576 AsmWriteMsr64 (MSR_IA32_QM_EVTSEL, Msr.Uint64);
5578 @note MSR_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.
5580 #define MSR_IA32_QM_EVTSEL 0x00000C8D
5583 MSR information returned for MSR index #MSR_IA32_QM_EVTSEL
5587 /// Individual bit fields
5591 /// [Bits 7:0] Event ID: ID of a supported monitoring event to report via
5597 /// [Bits 63:32] Resource Monitoring ID: ID for monitoring hardware to
5598 /// report monitored data via IA32_QM_CTR. N = Ceil (Log:sub:`2` (
5599 /// CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).
5601 UINT32 ResourceMonitoringID
:32;
5604 /// All bit fields as a 64-bit value
5607 } MSR_IA32_QM_EVTSEL_REGISTER
;
5611 Monitoring Counter Register (R/O). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] = 1
5614 @param ECX MSR_IA32_QM_CTR (0x00000C8E)
5615 @param EAX Lower 32-bits of MSR value.
5616 Described by the type MSR_IA32_QM_CTR_REGISTER.
5617 @param EDX Upper 32-bits of MSR value.
5618 Described by the type MSR_IA32_QM_CTR_REGISTER.
5620 <b>Example usage</b>
5622 MSR_IA32_QM_CTR_REGISTER Msr;
5624 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_CTR);
5626 @note MSR_IA32_QM_CTR is defined as IA32_QM_CTR in SDM.
5628 #define MSR_IA32_QM_CTR 0x00000C8E
5631 MSR information returned for MSR index #MSR_IA32_QM_CTR
5635 /// Individual bit fields
5639 /// [Bits 31:0] Resource Monitored Data.
5641 UINT32 ResourceMonitoredData
:32;
5643 /// [Bits 61:32] Resource Monitored Data.
5645 UINT32 ResourceMonitoredDataHi
:30;
5647 /// [Bit 62] Unavailable: If 1, indicates data for this RMID is not
5648 /// available or not monitored for this resource or RMID.
5650 UINT32 Unavailable
:1;
5652 /// [Bit 63] Error: If 1, indicates and unsupported RMID or event type was
5653 /// written to IA32_PQR_QM_EVTSEL.
5658 /// All bit fields as a 64-bit value
5661 } MSR_IA32_QM_CTR_REGISTER
;
5665 Resource Association Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] =
5668 @param ECX MSR_IA32_PQR_ASSOC (0x00000C8F)
5669 @param EAX Lower 32-bits of MSR value.
5670 Described by the type MSR_IA32_PQR_ASSOC_REGISTER.
5671 @param EDX Upper 32-bits of MSR value.
5672 Described by the type MSR_IA32_PQR_ASSOC_REGISTER.
5674 <b>Example usage</b>
5676 MSR_IA32_PQR_ASSOC_REGISTER Msr;
5678 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PQR_ASSOC);
5679 AsmWriteMsr64 (MSR_IA32_PQR_ASSOC, Msr.Uint64);
5681 @note MSR_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
5683 #define MSR_IA32_PQR_ASSOC 0x00000C8F
5686 MSR information returned for MSR index #MSR_IA32_PQR_ASSOC
5690 /// Individual bit fields
5694 /// [Bits 31:0] Resource Monitoring ID (R/W): ID for monitoring hardware
5695 /// to track internal operation, e.g. memory access. N = Ceil (Log:sub:`2`
5696 /// ( CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).
5698 UINT32 ResourceMonitoringID
:32;
5700 /// [Bits 63:32] COS (R/W). The class of service (COS) to enforce (on
5701 /// writes); returns the current COS when read. If ( CPUID.(EAX=07H,
5702 /// ECX=0):EBX.[15] = 1 ).
5707 /// All bit fields as a 64-bit value
5710 } MSR_IA32_PQR_ASSOC_REGISTER
;
5714 Supervisor State of MPX Configuration. (R/W). If (CPUID.(EAX=07H,
5715 ECX=0H):EBX[14] = 1).
5717 @param ECX MSR_IA32_BNDCFGS (0x00000D90)
5718 @param EAX Lower 32-bits of MSR value.
5719 Described by the type MSR_IA32_BNDCFGS_REGISTER.
5720 @param EDX Upper 32-bits of MSR value.
5721 Described by the type MSR_IA32_BNDCFGS_REGISTER.
5723 <b>Example usage</b>
5725 MSR_IA32_BNDCFGS_REGISTER Msr;
5727 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BNDCFGS);
5728 AsmWriteMsr64 (MSR_IA32_BNDCFGS, Msr.Uint64);
5730 @note MSR_IA32_BNDCFGS is defined as IA32_BNDCFGS in SDM.
5732 #define MSR_IA32_BNDCFGS 0x00000D90
5735 MSR information returned for MSR index #MSR_IA32_BNDCFGS
5739 /// Individual bit fields
5743 /// [Bit 0] EN: Enable Intel MPX in supervisor mode.
5747 /// [Bit 1] BNDPRESERVE: Preserve the bounds registers for near branch
5748 /// instructions in the absence of the BND prefix.
5750 UINT32 BNDPRESERVE
:1;
5753 /// [Bits 31:12] Base Address of Bound Directory.
5757 /// [Bits 63:32] Base Address of Bound Directory.
5762 /// All bit fields as a 64-bit value
5765 } MSR_IA32_BNDCFGS_REGISTER
;
5769 Extended Supervisor State Mask (R/W). If( CPUID.(0DH, 1):EAX.[3] = 1.
5771 @param ECX MSR_IA32_XSS (0x00000DA0)
5772 @param EAX Lower 32-bits of MSR value.
5773 Described by the type MSR_IA32_XSS_REGISTER.
5774 @param EDX Upper 32-bits of MSR value.
5775 Described by the type MSR_IA32_XSS_REGISTER.
5777 <b>Example usage</b>
5779 MSR_IA32_XSS_REGISTER Msr;
5781 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_XSS);
5782 AsmWriteMsr64 (MSR_IA32_XSS, Msr.Uint64);
5784 @note MSR_IA32_XSS is defined as IA32_XSS in SDM.
5786 #define MSR_IA32_XSS 0x00000DA0
5789 MSR information returned for MSR index #MSR_IA32_XSS
5793 /// Individual bit fields
5798 /// [Bit 8] Trace Packet Configuration State (R/W).
5800 UINT32 TracePacketConfigurationState
:1;
5801 UINT32 Reserved2
:23;
5802 UINT32 Reserved3
:32;
5805 /// All bit fields as a 32-bit value
5809 /// All bit fields as a 64-bit value
5812 } MSR_IA32_XSS_REGISTER
;
5816 Package Level Enable/disable HDC (R/W). If CPUID.06H:EAX.[13] = 1.
5818 @param ECX MSR_IA32_PKG_HDC_CTL (0x00000DB0)
5819 @param EAX Lower 32-bits of MSR value.
5820 Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.
5821 @param EDX Upper 32-bits of MSR value.
5822 Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.
5824 <b>Example usage</b>
5826 MSR_IA32_PKG_HDC_CTL_REGISTER Msr;
5828 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PKG_HDC_CTL);
5829 AsmWriteMsr64 (MSR_IA32_PKG_HDC_CTL, Msr.Uint64);
5831 @note MSR_IA32_PKG_HDC_CTL is defined as IA32_PKG_HDC_CTL in SDM.
5833 #define MSR_IA32_PKG_HDC_CTL 0x00000DB0
5836 MSR information returned for MSR index #MSR_IA32_PKG_HDC_CTL
5840 /// Individual bit fields
5844 /// [Bit 0] HDC_Pkg_Enable (R/W) Force HDC idling or wake up HDC-idled
5845 /// logical processors in the package. See Section 14.5.2, "Package level
5846 /// Enabling HDC". If CPUID.06H:EAX.[13] = 1.
5848 UINT32 HDC_Pkg_Enable
:1;
5849 UINT32 Reserved1
:31;
5850 UINT32 Reserved2
:32;
5853 /// All bit fields as a 32-bit value
5857 /// All bit fields as a 64-bit value
5860 } MSR_IA32_PKG_HDC_CTL_REGISTER
;
5864 Enable/disable HWP (R/W). If CPUID.06H:EAX.[13] = 1.
5866 @param ECX MSR_IA32_PM_CTL1 (0x00000DB1)
5867 @param EAX Lower 32-bits of MSR value.
5868 Described by the type MSR_IA32_PM_CTL1_REGISTER.
5869 @param EDX Upper 32-bits of MSR value.
5870 Described by the type MSR_IA32_PM_CTL1_REGISTER.
5872 <b>Example usage</b>
5874 MSR_IA32_PM_CTL1_REGISTER Msr;
5876 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_CTL1);
5877 AsmWriteMsr64 (MSR_IA32_PM_CTL1, Msr.Uint64);
5879 @note MSR_IA32_PM_CTL1 is defined as IA32_PM_CTL1 in SDM.
5881 #define MSR_IA32_PM_CTL1 0x00000DB1
5884 MSR information returned for MSR index #MSR_IA32_PM_CTL1
5888 /// Individual bit fields
5892 /// [Bit 0] HDC_Allow_Block (R/W) Allow/Block this logical processor for
5893 /// package level HDC control. See Section 14.5.3.
5894 /// If CPUID.06H:EAX.[13] = 1.
5896 UINT32 HDC_Allow_Block
:1;
5897 UINT32 Reserved1
:31;
5898 UINT32 Reserved2
:32;
5901 /// All bit fields as a 32-bit value
5905 /// All bit fields as a 64-bit value
5908 } MSR_IA32_PM_CTL1_REGISTER
;
5912 Per-Logical_Processor HDC Idle Residency (R/0). If CPUID.06H:EAX.[13] = 1.
5913 Stall_Cycle_Cnt (R/W) Stalled cycles due to HDC forced idle on this logical
5914 processor. See Section 14.5.4.1. If CPUID.06H:EAX.[13] = 1.
5916 @param ECX MSR_IA32_THREAD_STALL (0x00000DB2)
5917 @param EAX Lower 32-bits of MSR value.
5918 @param EDX Upper 32-bits of MSR value.
5920 <b>Example usage</b>
5924 Msr = AsmReadMsr64 (MSR_IA32_THREAD_STALL);
5926 @note MSR_IA32_THREAD_STALL is defined as IA32_THREAD_STALL in SDM.
5928 #define MSR_IA32_THREAD_STALL 0x00000DB2
5932 Extended Feature Enables. If ( CPUID.80000001H:EDX.[2 0]
5933 CPUID.80000001H:EDX.[2 9]).
5935 @param ECX MSR_IA32_EFER (0xC0000080)
5936 @param EAX Lower 32-bits of MSR value.
5937 Described by the type MSR_IA32_EFER_REGISTER.
5938 @param EDX Upper 32-bits of MSR value.
5939 Described by the type MSR_IA32_EFER_REGISTER.
5941 <b>Example usage</b>
5943 MSR_IA32_EFER_REGISTER Msr;
5945 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);
5946 AsmWriteMsr64 (MSR_IA32_EFER, Msr.Uint64);
5948 @note MSR_IA32_EFER is defined as IA32_EFER in SDM.
5950 #define MSR_IA32_EFER 0xC0000080
5953 MSR information returned for MSR index #MSR_IA32_EFER
5957 /// Individual bit fields
5961 /// [Bit 0] SYSCALL Enable: IA32_EFER.SCE (R/W) Enables SYSCALL/SYSRET
5962 /// instructions in 64-bit mode.
5967 /// [Bit 8] IA-32e Mode Enable: IA32_EFER.LME (R/W) Enables IA-32e mode
5973 /// [Bit 10] IA-32e Mode Active: IA32_EFER.LMA (R) Indicates IA-32e mode
5974 /// is active when set.
5978 /// [Bit 11] Execute Disable Bit Enable: IA32_EFER.NXE (R/W).
5981 UINT32 Reserved3
:20;
5982 UINT32 Reserved4
:32;
5985 /// All bit fields as a 32-bit value
5989 /// All bit fields as a 64-bit value
5992 } MSR_IA32_EFER_REGISTER
;
5996 System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.
5998 @param ECX MSR_IA32_STAR (0xC0000081)
5999 @param EAX Lower 32-bits of MSR value.
6000 @param EDX Upper 32-bits of MSR value.
6002 <b>Example usage</b>
6006 Msr = AsmReadMsr64 (MSR_IA32_STAR);
6007 AsmWriteMsr64 (MSR_IA32_STAR, Msr);
6009 @note MSR_IA32_STAR is defined as IA32_STAR in SDM.
6011 #define MSR_IA32_STAR 0xC0000081
6015 IA-32e Mode System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.
6017 @param ECX MSR_IA32_LSTAR (0xC0000082)
6018 @param EAX Lower 32-bits of MSR value.
6019 @param EDX Upper 32-bits of MSR value.
6021 <b>Example usage</b>
6025 Msr = AsmReadMsr64 (MSR_IA32_LSTAR);
6026 AsmWriteMsr64 (MSR_IA32_LSTAR, Msr);
6028 @note MSR_IA32_LSTAR is defined as IA32_LSTAR in SDM.
6030 #define MSR_IA32_LSTAR 0xC0000082
6034 System Call Flag Mask (R/W). If CPUID.80000001:EDX.[29] = 1.
6036 @param ECX MSR_IA32_FMASK (0xC0000084)
6037 @param EAX Lower 32-bits of MSR value.
6038 @param EDX Upper 32-bits of MSR value.
6040 <b>Example usage</b>
6044 Msr = AsmReadMsr64 (MSR_IA32_FMASK);
6045 AsmWriteMsr64 (MSR_IA32_FMASK, Msr);
6047 @note MSR_IA32_FMASK is defined as IA32_FMASK in SDM.
6049 #define MSR_IA32_FMASK 0xC0000084
6053 Map of BASE Address of FS (R/W). If CPUID.80000001:EDX.[29] = 1.
6055 @param ECX MSR_IA32_FS_BASE (0xC0000100)
6056 @param EAX Lower 32-bits of MSR value.
6057 @param EDX Upper 32-bits of MSR value.
6059 <b>Example usage</b>
6063 Msr = AsmReadMsr64 (MSR_IA32_FS_BASE);
6064 AsmWriteMsr64 (MSR_IA32_FS_BASE, Msr);
6066 @note MSR_IA32_FS_BASE is defined as IA32_FS_BASE in SDM.
6068 #define MSR_IA32_FS_BASE 0xC0000100
6072 Map of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.
6074 @param ECX MSR_IA32_GS_BASE (0xC0000101)
6075 @param EAX Lower 32-bits of MSR value.
6076 @param EDX Upper 32-bits of MSR value.
6078 <b>Example usage</b>
6082 Msr = AsmReadMsr64 (MSR_IA32_GS_BASE);
6083 AsmWriteMsr64 (MSR_IA32_GS_BASE, Msr);
6085 @note MSR_IA32_GS_BASE is defined as IA32_GS_BASE in SDM.
6087 #define MSR_IA32_GS_BASE 0xC0000101
6091 Swap Target of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.
6093 @param ECX MSR_IA32_KERNEL_GS_BASE (0xC0000102)
6094 @param EAX Lower 32-bits of MSR value.
6095 @param EDX Upper 32-bits of MSR value.
6097 <b>Example usage</b>
6101 Msr = AsmReadMsr64 (MSR_IA32_KERNEL_GS_BASE);
6102 AsmWriteMsr64 (MSR_IA32_KERNEL_GS_BASE, Msr);
6104 @note MSR_IA32_KERNEL_GS_BASE is defined as IA32_KERNEL_GS_BASE in SDM.
6106 #define MSR_IA32_KERNEL_GS_BASE 0xC0000102
6110 Auxiliary TSC (RW). If CPUID.80000001H: EDX[27] = 1.
6112 @param ECX MSR_IA32_TSC_AUX (0xC0000103)
6113 @param EAX Lower 32-bits of MSR value.
6114 Described by the type MSR_IA32_TSC_AUX_REGISTER.
6115 @param EDX Upper 32-bits of MSR value.
6116 Described by the type MSR_IA32_TSC_AUX_REGISTER.
6118 <b>Example usage</b>
6120 MSR_IA32_TSC_AUX_REGISTER Msr;
6122 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_TSC_AUX);
6123 AsmWriteMsr64 (MSR_IA32_TSC_AUX, Msr.Uint64);
6125 @note MSR_IA32_TSC_AUX is defined as IA32_TSC_AUX in SDM.
6127 #define MSR_IA32_TSC_AUX 0xC0000103
6130 MSR information returned for MSR index #MSR_IA32_TSC_AUX
6134 /// Individual bit fields
6138 /// [Bits 31:0] AUX: Auxiliary signature of TSC.
6144 /// All bit fields as a 32-bit value
6148 /// All bit fields as a 64-bit value
6151 } MSR_IA32_TSC_AUX_REGISTER
;