2 Architectural MSR Definitions.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.1.
22 @par Specification Reference:
23 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
24 September 2016, Appendix A VMX Capability Reporting Facility, Section A.1.
26 @par Specification Reference:
27 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
28 September 2016, Appendix A VMX Capability Reporting Facility, Section A.6.
32 #ifndef __ARCHITECTURAL_MSR_H__
33 #define __ARCHITECTURAL_MSR_H__
36 See Section 35.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).
38 @param ECX MSR_IA32_P5_MC_ADDR (0x00000000)
39 @param EAX Lower 32-bits of MSR value.
40 @param EDX Upper 32-bits of MSR value.
46 Msr = AsmReadMsr64 (MSR_IA32_P5_MC_ADDR);
47 AsmWriteMsr64 (MSR_IA32_P5_MC_ADDR, Msr);
49 @note MSR_IA32_P5_MC_ADDR is defined as IA32_P5_MC_ADDR in SDM.
51 #define MSR_IA32_P5_MC_ADDR 0x00000000
55 See Section 35.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.
57 @param ECX MSR_IA32_P5_MC_TYPE (0x00000001)
58 @param EAX Lower 32-bits of MSR value.
59 @param EDX Upper 32-bits of MSR value.
65 Msr = AsmReadMsr64 (MSR_IA32_P5_MC_TYPE);
66 AsmWriteMsr64 (MSR_IA32_P5_MC_TYPE, Msr);
68 @note MSR_IA32_P5_MC_TYPE is defined as IA32_P5_MC_TYPE in SDM.
70 #define MSR_IA32_P5_MC_TYPE 0x00000001
74 See Section 8.10.5, "Monitor/Mwait Address Range Determination.". Introduced
75 at Display Family / Display Model 0F_03H.
77 @param ECX MSR_IA32_MONITOR_FILTER_SIZE (0x00000006)
78 @param EAX Lower 32-bits of MSR value.
79 @param EDX Upper 32-bits of MSR value.
85 Msr = AsmReadMsr64 (MSR_IA32_MONITOR_FILTER_SIZE);
86 AsmWriteMsr64 (MSR_IA32_MONITOR_FILTER_SIZE, Msr);
88 @note MSR_IA32_MONITOR_FILTER_SIZE is defined as IA32_MONITOR_FILTER_SIZE in SDM.
90 #define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006
94 See Section 17.15, "Time-Stamp Counter.". Introduced at Display Family /
97 @param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010)
98 @param EAX Lower 32-bits of MSR value.
99 @param EDX Upper 32-bits of MSR value.
105 Msr = AsmReadMsr64 (MSR_IA32_TIME_STAMP_COUNTER);
106 AsmWriteMsr64 (MSR_IA32_TIME_STAMP_COUNTER, Msr);
108 @note MSR_IA32_TIME_STAMP_COUNTER is defined as IA32_TIME_STAMP_COUNTER in SDM.
110 #define MSR_IA32_TIME_STAMP_COUNTER 0x00000010
114 Platform ID (RO) The operating system can use this MSR to determine "slot"
115 information for the processor and the proper microcode update to load.
116 Introduced at Display Family / Display Model 06_01H.
118 @param ECX MSR_IA32_PLATFORM_ID (0x00000017)
119 @param EAX Lower 32-bits of MSR value.
120 Described by the type MSR_IA32_PLATFORM_ID_REGISTER.
121 @param EDX Upper 32-bits of MSR value.
122 Described by the type MSR_IA32_PLATFORM_ID_REGISTER.
126 MSR_IA32_PLATFORM_ID_REGISTER Msr;
128 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);
130 @note MSR_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.
132 #define MSR_IA32_PLATFORM_ID 0x00000017
135 MSR information returned for MSR index #MSR_IA32_PLATFORM_ID
139 /// Individual bit fields
145 /// [Bits 52:50] Platform Id (RO) Contains information concerning the
146 /// intended platform for the processor.
149 /// 0 0 0 Processor Flag 0.
150 /// 0 0 1 Processor Flag 1
151 /// 0 1 0 Processor Flag 2
152 /// 0 1 1 Processor Flag 3
153 /// 1 0 0 Processor Flag 4
154 /// 1 0 1 Processor Flag 5
155 /// 1 1 0 Processor Flag 6
156 /// 1 1 1 Processor Flag 7
162 /// All bit fields as a 64-bit value
165 } MSR_IA32_PLATFORM_ID_REGISTER
;
171 @param ECX MSR_IA32_APIC_BASE (0x0000001B)
172 @param EAX Lower 32-bits of MSR value.
173 Described by the type MSR_IA32_APIC_BASE_REGISTER.
174 @param EDX Upper 32-bits of MSR value.
175 Described by the type MSR_IA32_APIC_BASE_REGISTER.
179 MSR_IA32_APIC_BASE_REGISTER Msr;
181 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
182 AsmWriteMsr64 (MSR_IA32_APIC_BASE, Msr.Uint64);
184 @note MSR_IA32_APIC_BASE is defined as IA32_APIC_BASE in SDM.
186 #define MSR_IA32_APIC_BASE 0x0000001B
189 MSR information returned for MSR index #MSR_IA32_APIC_BASE
193 /// Individual bit fields
198 /// [Bit 8] BSP flag (R/W).
203 /// [Bit 10] Enable x2APIC mode. Introduced at Display Family / Display
208 /// [Bit 11] APIC Global Enable (R/W).
212 /// [Bits 31:12] APIC Base (R/W).
216 /// [Bits 63:32] APIC Base (R/W).
218 UINT32 ApicBaseHi
:32;
221 /// All bit fields as a 64-bit value
224 } MSR_IA32_APIC_BASE_REGISTER
;
228 Control Features in Intel 64 Processor (R/W). If any one enumeration
229 condition for defined bit field holds.
231 @param ECX MSR_IA32_FEATURE_CONTROL (0x0000003A)
232 @param EAX Lower 32-bits of MSR value.
233 Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.
234 @param EDX Upper 32-bits of MSR value.
235 Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.
239 MSR_IA32_FEATURE_CONTROL_REGISTER Msr;
241 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL);
242 AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, Msr.Uint64);
244 @note MSR_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.
246 #define MSR_IA32_FEATURE_CONTROL 0x0000003A
249 MSR information returned for MSR index #MSR_IA32_FEATURE_CONTROL
253 /// Individual bit fields
257 /// [Bit 0] Lock bit (R/WO): (1 = locked). When set, locks this MSR from
258 /// being written, writes to this bit will result in GP(0). Note: Once the
259 /// Lock bit is set, the contents of this register cannot be modified.
260 /// Therefore the lock bit must be set after configuring support for Intel
261 /// Virtualization Technology and prior to transferring control to an
262 /// option ROM or the OS. Hence, once the Lock bit is set, the entire
263 /// IA32_FEATURE_CONTROL contents are preserved across RESET when PWRGOOD
264 /// is not deasserted. If any one enumeration condition for defined bit
265 /// field position greater than bit 0 holds.
269 /// [Bit 1] Enable VMX inside SMX operation (R/WL): This bit enables a
270 /// system executive to use VMX in conjunction with SMX to support
271 /// Intel(R) Trusted Execution Technology. BIOS must set this bit only
272 /// when the CPUID function 1 returns VMX feature flag and SMX feature
273 /// flag set (ECX bits 5 and 6 respectively). If CPUID.01H:ECX[5] = 1 &&
274 /// CPUID.01H:ECX[6] = 1.
276 UINT32 EnableVmxInsideSmx
:1;
278 /// [Bit 2] Enable VMX outside SMX operation (R/WL): This bit enables VMX
279 /// for system executive that do not require SMX. BIOS must set this bit
280 /// only when the CPUID function 1 returns VMX feature flag set (ECX bit
281 /// 5). If CPUID.01H:ECX[5] = 1.
283 UINT32 EnableVmxOutsideSmx
:1;
286 /// [Bits 14:8] SENTER Local Function Enables (R/WL): When set, each bit
287 /// in the field represents an enable control for a corresponding SENTER
288 /// function. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If
289 /// CPUID.01H:ECX[6] = 1.
291 UINT32 SenterLocalFunctionEnables
:7;
293 /// [Bit 15] SENTER Global Enable (R/WL): This bit must be set to enable
294 /// SENTER leaf functions. This bit is supported only if CPUID.1:ECX.[bit
295 /// 6] is set. If CPUID.01H:ECX[6] = 1.
297 UINT32 SenterGlobalEnable
:1;
300 /// [Bit 17] SGX Launch Control Enable (R/WL): This bit must be set to
301 /// enable runtime reconfiguration of SGX Launch Control via
302 /// IA32_SGXLEPUBKEYHASHn MSR. If CPUID.(EAX=07H, ECX=0H): ECX[30] = 1.
304 UINT32 SgxLaunchControlEnable
:1;
306 /// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX
307 /// leaf functions. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.
312 /// [Bit 20] LMCE On (R/WL): When set, system software can program the
313 /// MSRs associated with LMCE to configure delivery of some machine check
314 /// exceptions to a single logical processor. If IA32_MCG_CAP[27] = 1.
321 /// All bit fields as a 32-bit value
325 /// All bit fields as a 64-bit value
328 } MSR_IA32_FEATURE_CONTROL_REGISTER
;
332 Per Logical Processor TSC Adjust (R/Write to clear). If CPUID.(EAX=07H,
333 ECX=0H): EBX[1] = 1. THREAD_ADJUST: Local offset value of the IA32_TSC for
334 a logical processor. Reset value is Zero. A write to IA32_TSC will modify
335 the local offset in IA32_TSC_ADJUST and the content of IA32_TSC, but does
336 not affect the internal invariant TSC hardware.
338 @param ECX MSR_IA32_TSC_ADJUST (0x0000003B)
339 @param EAX Lower 32-bits of MSR value.
340 @param EDX Upper 32-bits of MSR value.
346 Msr = AsmReadMsr64 (MSR_IA32_TSC_ADJUST);
347 AsmWriteMsr64 (MSR_IA32_TSC_ADJUST, Msr);
349 @note MSR_IA32_TSC_ADJUST is defined as IA32_TSC_ADJUST in SDM.
351 #define MSR_IA32_TSC_ADJUST 0x0000003B
355 BIOS Update Trigger (W) Executing a WRMSR instruction to this MSR causes a
356 microcode update to be loaded into the processor. See Section 9.11.6,
357 "Microcode Update Loader." A processor may prevent writing to this MSR when
358 loading guest states on VM entries or saving guest states on VM exits.
359 Introduced at Display Family / Display Model 06_01H.
361 @param ECX MSR_IA32_BIOS_UPDT_TRIG (0x00000079)
362 @param EAX Lower 32-bits of MSR value.
363 @param EDX Upper 32-bits of MSR value.
370 AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, Msr);
372 @note MSR_IA32_BIOS_UPDT_TRIG is defined as IA32_BIOS_UPDT_TRIG in SDM.
374 #define MSR_IA32_BIOS_UPDT_TRIG 0x00000079
378 BIOS Update Signature (RO) Returns the microcode update signature following
379 the execution of CPUID.01H. A processor may prevent writing to this MSR when
380 loading guest states on VM entries or saving guest states on VM exits.
381 Introduced at Display Family / Display Model 06_01H.
383 @param ECX MSR_IA32_BIOS_SIGN_ID (0x0000008B)
384 @param EAX Lower 32-bits of MSR value.
385 Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.
386 @param EDX Upper 32-bits of MSR value.
387 Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.
391 MSR_IA32_BIOS_SIGN_ID_REGISTER Msr;
393 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID);
395 @note MSR_IA32_BIOS_SIGN_ID is defined as IA32_BIOS_SIGN_ID in SDM.
397 #define MSR_IA32_BIOS_SIGN_ID 0x0000008B
400 MSR information returned for MSR index #MSR_IA32_BIOS_SIGN_ID
404 /// Individual bit fields
409 /// [Bits 63:32] Microcode update signature. This field contains the
410 /// signature of the currently loaded microcode update when read following
411 /// the execution of the CPUID instruction, function 1. It is required
412 /// that this register field be pre-loaded with zero prior to executing
413 /// the CPUID, function 1. If the field remains equal to zero, then there
414 /// is no microcode update loaded. Another nonzero value will be the
417 UINT32 MicrocodeUpdateSignature
:32;
420 /// All bit fields as a 64-bit value
423 } MSR_IA32_BIOS_SIGN_ID_REGISTER
;
427 IA32_SGXLEPUBKEYHASH[(64*n+63):(64*n)] (R/W) Bits (64*n+63):(64*n) of the
428 SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the
429 default value is the digest of Intel's signing key. Read permitted If
430 CPUID.(EAX=12H,ECX=0H):EAX[0]=1, Write permitted if CPUID.(EAX=12H,ECX=0H):
431 EAX[0]=1 && IA32_FEATURE_CONTROL[17] = 1 && IA32_FEATURE_CONTROL[0] = 1.
433 @param ECX MSR_IA32_SGXLEPUBKEYHASHn
434 @param EAX Lower 32-bits of MSR value.
435 @param EDX Upper 32-bits of MSR value.
441 Msr = AsmReadMsr64 (MSR_IA32_SGXLEPUBKEYHASHn);
442 AsmWriteMsr64 (MSR_IA32_SGXLEPUBKEYHASHn, Msr);
444 @note MSR_IA32_SGXLEPUBKEYHASH0 is defined as IA32_SGXLEPUBKEYHASH0 in SDM.
445 MSR_IA32_SGXLEPUBKEYHASH1 is defined as IA32_SGXLEPUBKEYHASH1 in SDM.
446 MSR_IA32_SGXLEPUBKEYHASH2 is defined as IA32_SGXLEPUBKEYHASH2 in SDM.
447 MSR_IA32_SGXLEPUBKEYHASH3 is defined as IA32_SGXLEPUBKEYHASH3 in SDM.
450 #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C
451 #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D
452 #define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E
453 #define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F
458 SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] =
461 @param ECX MSR_IA32_SMM_MONITOR_CTL (0x0000009B)
462 @param EAX Lower 32-bits of MSR value.
463 Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.
464 @param EDX Upper 32-bits of MSR value.
465 Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.
469 MSR_IA32_SMM_MONITOR_CTL_REGISTER Msr;
471 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);
472 AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, Msr.Uint64);
474 @note MSR_IA32_SMM_MONITOR_CTL is defined as IA32_SMM_MONITOR_CTL in SDM.
476 #define MSR_IA32_SMM_MONITOR_CTL 0x0000009B
479 MSR information returned for MSR index #MSR_IA32_SMM_MONITOR_CTL
483 /// Individual bit fields
487 /// [Bit 0] Valid (R/W). The STM may be invoked using VMCALL only if this
488 /// bit is 1. Because VMCALL is used to activate the dual-monitor treatment
489 /// (see Section 34.15.6), the dual-monitor treatment cannot be activated
490 /// if the bit is 0. This bit is cleared when the logical processor is
496 /// [Bit 2] Determines whether executions of VMXOFF unblock SMIs under the
497 /// default treatment of SMIs and SMM. Executions of VMXOFF unblock SMIs
498 /// unless bit 2 is 1 (the value of bit 0 is irrelevant).
503 /// [Bits 31:12] MSEG Base (R/W).
509 /// All bit fields as a 32-bit value
513 /// All bit fields as a 64-bit value
516 } MSR_IA32_SMM_MONITOR_CTL_REGISTER
;
519 MSEG header that is located at the physical address specified by the MsegBase
520 field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER.
523 UINT32 MsegHeaderRevision
;
524 UINT32 MonitorFeatures
;
526 UINT32 GdtrBaseOffset
;
532 // Pad header so total size is 2KB
534 UINT8 Reserved
[SIZE_2KB
- 8 * sizeof (UINT32
)];
539 Base address of the logical processor's SMRAM image (RO, SMM only). If
542 @param ECX MSR_IA32_SMBASE (0x0000009E)
543 @param EAX Lower 32-bits of MSR value.
544 @param EDX Upper 32-bits of MSR value.
550 Msr = AsmReadMsr64 (MSR_IA32_SMBASE);
552 @note MSR_IA32_SMBASE is defined as IA32_SMBASE in SDM.
554 #define MSR_IA32_SMBASE 0x0000009E
558 General Performance Counters (R/W).
559 MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n.
561 @param ECX MSR_IA32_PMCn
562 @param EAX Lower 32-bits of MSR value.
563 @param EDX Upper 32-bits of MSR value.
569 Msr = AsmReadMsr64 (MSR_IA32_PMC0);
570 AsmWriteMsr64 (MSR_IA32_PMC0, Msr);
572 @note MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM.
573 MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM.
574 MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM.
575 MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM.
576 MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM.
577 MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM.
578 MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM.
579 MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.
582 #define MSR_IA32_PMC0 0x000000C1
583 #define MSR_IA32_PMC1 0x000000C2
584 #define MSR_IA32_PMC2 0x000000C3
585 #define MSR_IA32_PMC3 0x000000C4
586 #define MSR_IA32_PMC4 0x000000C5
587 #define MSR_IA32_PMC5 0x000000C6
588 #define MSR_IA32_PMC6 0x000000C7
589 #define MSR_IA32_PMC7 0x000000C8
594 TSC Frequency Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 1.
595 C0_MCNT: C0 TSC Frequency Clock Count Increments at fixed interval (relative
596 to TSC freq.) when the logical processor is in C0. Cleared upon overflow /
597 wrap-around of IA32_APERF.
599 @param ECX MSR_IA32_MPERF (0x000000E7)
600 @param EAX Lower 32-bits of MSR value.
601 @param EDX Upper 32-bits of MSR value.
607 Msr = AsmReadMsr64 (MSR_IA32_MPERF);
608 AsmWriteMsr64 (MSR_IA32_MPERF, Msr);
610 @note MSR_IA32_MPERF is defined as IA32_MPERF in SDM.
612 #define MSR_IA32_MPERF 0x000000E7
616 Actual Performance Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] =
617 1. C0_ACNT: C0 Actual Frequency Clock Count Accumulates core clock counts at
618 the coordinated clock frequency, when the logical processor is in C0.
619 Cleared upon overflow / wrap-around of IA32_MPERF.
621 @param ECX MSR_IA32_APERF (0x000000E8)
622 @param EAX Lower 32-bits of MSR value.
623 @param EDX Upper 32-bits of MSR value.
629 Msr = AsmReadMsr64 (MSR_IA32_APERF);
630 AsmWriteMsr64 (MSR_IA32_APERF, Msr);
632 @note MSR_IA32_APERF is defined as IA32_APERF in SDM.
634 #define MSR_IA32_APERF 0x000000E8
638 MTRR Capability (RO) Section 11.11.2.1, "IA32_MTRR_DEF_TYPE MSR.".
639 Introduced at Display Family / Display Model 06_01H.
641 @param ECX MSR_IA32_MTRRCAP (0x000000FE)
642 @param EAX Lower 32-bits of MSR value.
643 Described by the type MSR_IA32_MTRRCAP_REGISTER.
644 @param EDX Upper 32-bits of MSR value.
645 Described by the type MSR_IA32_MTRRCAP_REGISTER.
649 MSR_IA32_MTRRCAP_REGISTER Msr;
651 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);
653 @note MSR_IA32_MTRRCAP is defined as IA32_MTRRCAP in SDM.
655 #define MSR_IA32_MTRRCAP 0x000000FE
658 MSR information returned for MSR index #MSR_IA32_MTRRCAP
662 /// Individual bit fields
666 /// [Bits 7:0] VCNT: The number of variable memory type ranges in the
671 /// [Bit 8] Fixed range MTRRs are supported when set.
676 /// [Bit 10] WC Supported when set.
680 /// [Bit 11] SMRR Supported when set.
687 /// All bit fields as a 32-bit value
691 /// All bit fields as a 64-bit value
694 } MSR_IA32_MTRRCAP_REGISTER
;
698 SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
700 @param ECX MSR_IA32_SYSENTER_CS (0x00000174)
701 @param EAX Lower 32-bits of MSR value.
702 Described by the type MSR_IA32_SYSENTER_CS_REGISTER.
703 @param EDX Upper 32-bits of MSR value.
704 Described by the type MSR_IA32_SYSENTER_CS_REGISTER.
708 MSR_IA32_SYSENTER_CS_REGISTER Msr;
710 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SYSENTER_CS);
711 AsmWriteMsr64 (MSR_IA32_SYSENTER_CS, Msr.Uint64);
713 @note MSR_IA32_SYSENTER_CS is defined as IA32_SYSENTER_CS in SDM.
715 #define MSR_IA32_SYSENTER_CS 0x00000174
718 MSR information returned for MSR index #MSR_IA32_SYSENTER_CS
722 /// Individual bit fields
726 /// [Bits 15:0] CS Selector.
733 /// All bit fields as a 32-bit value
737 /// All bit fields as a 64-bit value
740 } MSR_IA32_SYSENTER_CS_REGISTER
;
744 SYSENTER_ESP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
746 @param ECX MSR_IA32_SYSENTER_ESP (0x00000175)
747 @param EAX Lower 32-bits of MSR value.
748 @param EDX Upper 32-bits of MSR value.
754 Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_ESP);
755 AsmWriteMsr64 (MSR_IA32_SYSENTER_ESP, Msr);
757 @note MSR_IA32_SYSENTER_ESP is defined as IA32_SYSENTER_ESP in SDM.
759 #define MSR_IA32_SYSENTER_ESP 0x00000175
763 SYSENTER_EIP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
765 @param ECX MSR_IA32_SYSENTER_EIP (0x00000176)
766 @param EAX Lower 32-bits of MSR value.
767 @param EDX Upper 32-bits of MSR value.
773 Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_EIP);
774 AsmWriteMsr64 (MSR_IA32_SYSENTER_EIP, Msr);
776 @note MSR_IA32_SYSENTER_EIP is defined as IA32_SYSENTER_EIP in SDM.
778 #define MSR_IA32_SYSENTER_EIP 0x00000176
782 Global Machine Check Capability (RO). Introduced at Display Family / Display
785 @param ECX MSR_IA32_MCG_CAP (0x00000179)
786 @param EAX Lower 32-bits of MSR value.
787 Described by the type MSR_IA32_MCG_CAP_REGISTER.
788 @param EDX Upper 32-bits of MSR value.
789 Described by the type MSR_IA32_MCG_CAP_REGISTER.
793 MSR_IA32_MCG_CAP_REGISTER Msr;
795 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
797 @note MSR_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.
799 #define MSR_IA32_MCG_CAP 0x00000179
802 MSR information returned for MSR index #MSR_IA32_MCG_CAP
806 /// Individual bit fields
810 /// [Bits 7:0] Count: Number of reporting banks.
814 /// [Bit 8] MCG_CTL_P: IA32_MCG_CTL is present if this bit is set.
818 /// [Bit 9] MCG_EXT_P: Extended machine check state registers are present
819 /// if this bit is set.
823 /// [Bit 10] MCP_CMCI_P: Support for corrected MC error event is present.
824 /// Introduced at Display Family / Display Model 06_01H.
828 /// [Bit 11] MCG_TES_P: Threshold-based error status register are present
829 /// if this bit is set.
834 /// [Bits 23:16] MCG_EXT_CNT: Number of extended machine check state
835 /// registers present.
837 UINT32 MCG_EXT_CNT
:8;
839 /// [Bit 24] MCG_SER_P: The processor supports software error recovery if
845 /// [Bit 26] MCG_ELOG_P: Indicates that the processor allows platform
846 /// firmware to be invoked when an error is detected so that it may
847 /// provide additional platform specific information in an ACPI format
848 /// "Generic Error Data Entry" that augments the data included in machine
849 /// check bank registers. Introduced at Display Family / Display Model
854 /// [Bit 27] MCG_LMCE_P: Indicates that the processor support extended
855 /// state in IA32_MCG_STATUS and associated MSR necessary to configure
856 /// Local Machine Check Exception (LMCE). Introduced at Display Family /
857 /// Display Model 06_3EH.
864 /// All bit fields as a 32-bit value
868 /// All bit fields as a 64-bit value
871 } MSR_IA32_MCG_CAP_REGISTER
;
875 Global Machine Check Status (R/W0). Introduced at Display Family / Display
878 @param ECX MSR_IA32_MCG_STATUS (0x0000017A)
879 @param EAX Lower 32-bits of MSR value.
880 Described by the type MSR_IA32_MCG_STATUS_REGISTER.
881 @param EDX Upper 32-bits of MSR value.
882 Described by the type MSR_IA32_MCG_STATUS_REGISTER.
886 MSR_IA32_MCG_STATUS_REGISTER Msr;
888 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS);
889 AsmWriteMsr64 (MSR_IA32_MCG_STATUS, Msr.Uint64);
891 @note MSR_IA32_MCG_STATUS is defined as IA32_MCG_STATUS in SDM.
893 #define MSR_IA32_MCG_STATUS 0x0000017A
896 MSR information returned for MSR index #MSR_IA32_MCG_STATUS
900 /// Individual bit fields
904 /// [Bit 0] RIPV. Restart IP valid. Introduced at Display Family / Display
909 /// [Bit 1] EIPV. Error IP valid. Introduced at Display Family / Display
914 /// [Bit 2] MCIP. Machine check in progress. Introduced at Display Family
915 /// / Display Model 06_01H.
919 /// [Bit 3] LMCE_S. If IA32_MCG_CAP.LMCE_P[2 7] =1.
926 /// All bit fields as a 32-bit value
930 /// All bit fields as a 64-bit value
933 } MSR_IA32_MCG_STATUS_REGISTER
;
937 Global Machine Check Control (R/W). If IA32_MCG_CAP.CTL_P[8] =1.
939 @param ECX MSR_IA32_MCG_CTL (0x0000017B)
940 @param EAX Lower 32-bits of MSR value.
941 @param EDX Upper 32-bits of MSR value.
947 Msr = AsmReadMsr64 (MSR_IA32_MCG_CTL);
948 AsmWriteMsr64 (MSR_IA32_MCG_CTL, Msr);
950 @note MSR_IA32_MCG_CTL is defined as IA32_MCG_CTL in SDM.
952 #define MSR_IA32_MCG_CTL 0x0000017B
956 Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n.
958 @param ECX MSR_IA32_PERFEVTSELn
959 @param EAX Lower 32-bits of MSR value.
960 Described by the type MSR_IA32_PERFEVTSEL_REGISTER.
961 @param EDX Upper 32-bits of MSR value.
962 Described by the type MSR_IA32_PERFEVTSEL_REGISTER.
966 MSR_IA32_PERFEVTSEL_REGISTER Msr;
968 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0);
969 AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64);
971 @note MSR_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.
972 MSR_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.
973 MSR_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.
974 MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.
977 #define MSR_IA32_PERFEVTSEL0 0x00000186
978 #define MSR_IA32_PERFEVTSEL1 0x00000187
979 #define MSR_IA32_PERFEVTSEL2 0x00000188
980 #define MSR_IA32_PERFEVTSEL3 0x00000189
984 MSR information returned for MSR indexes #MSR_IA32_PERFEVTSEL0 to
985 #MSR_IA32_PERFEVTSEL3
989 /// Individual bit fields
993 /// [Bits 7:0] Event Select: Selects a performance event logic unit.
995 UINT32 EventSelect
:8;
997 /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to
998 /// detect on the selected event logic.
1002 /// [Bit 16] USR: Counts while in privilege level is not ring 0.
1006 /// [Bit 17] OS: Counts while in privilege level is ring 0.
1010 /// [Bit 18] Edge: Enables edge detection if set.
1014 /// [Bit 19] PC: enables pin control.
1018 /// [Bit 20] INT: enables interrupt on counter overflow.
1022 /// [Bit 21] AnyThread: When set to 1, it enables counting the associated
1023 /// event conditions occurring across all logical processors sharing a
1024 /// processor core. When set to 0, the counter only increments the
1025 /// associated event conditions occurring in the logical processor which
1026 /// programmed the MSR.
1030 /// [Bit 22] EN: enables the corresponding performance counter to commence
1031 /// counting when this bit is set.
1035 /// [Bit 23] INV: invert the CMASK.
1039 /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding
1040 /// performance counter increments each cycle if the event count is
1041 /// greater than or equal to the CMASK.
1047 /// All bit fields as a 32-bit value
1051 /// All bit fields as a 64-bit value
1054 } MSR_IA32_PERFEVTSEL_REGISTER
;
1058 Current performance state(P-State) operating point (RO). Introduced at
1059 Display Family / Display Model 0F_03H.
1061 @param ECX MSR_IA32_PERF_STATUS (0x00000198)
1062 @param EAX Lower 32-bits of MSR value.
1063 Described by the type MSR_IA32_PERF_STATUS_REGISTER.
1064 @param EDX Upper 32-bits of MSR value.
1065 Described by the type MSR_IA32_PERF_STATUS_REGISTER.
1067 <b>Example usage</b>
1069 MSR_IA32_PERF_STATUS_REGISTER Msr;
1071 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_STATUS);
1073 @note MSR_IA32_PERF_STATUS is defined as IA32_PERF_STATUS in SDM.
1075 #define MSR_IA32_PERF_STATUS 0x00000198
1078 MSR information returned for MSR index #MSR_IA32_PERF_STATUS
1082 /// Individual bit fields
1086 /// [Bits 15:0] Current performance State Value.
1089 UINT32 Reserved1
:16;
1090 UINT32 Reserved2
:32;
1093 /// All bit fields as a 32-bit value
1097 /// All bit fields as a 64-bit value
1100 } MSR_IA32_PERF_STATUS_REGISTER
;
1104 (R/W). Introduced at Display Family / Display Model 0F_03H.
1106 @param ECX MSR_IA32_PERF_CTL (0x00000199)
1107 @param EAX Lower 32-bits of MSR value.
1108 Described by the type MSR_IA32_PERF_CTL_REGISTER.
1109 @param EDX Upper 32-bits of MSR value.
1110 Described by the type MSR_IA32_PERF_CTL_REGISTER.
1112 <b>Example usage</b>
1114 MSR_IA32_PERF_CTL_REGISTER Msr;
1116 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CTL);
1117 AsmWriteMsr64 (MSR_IA32_PERF_CTL, Msr.Uint64);
1119 @note MSR_IA32_PERF_CTL is defined as IA32_PERF_CTL in SDM.
1121 #define MSR_IA32_PERF_CTL 0x00000199
1124 MSR information returned for MSR index #MSR_IA32_PERF_CTL
1128 /// Individual bit fields
1132 /// [Bits 15:0] Target performance State Value.
1134 UINT32 TargetState
:16;
1135 UINT32 Reserved1
:16;
1137 /// [Bit 32] IDA Engage. (R/W) When set to 1: disengages IDA. 06_0FH
1141 UINT32 Reserved2
:31;
1144 /// All bit fields as a 64-bit value
1147 } MSR_IA32_PERF_CTL_REGISTER
;
1151 Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled
1152 Clock Modulation.". If CPUID.01H:EDX[22] = 1.
1154 @param ECX MSR_IA32_CLOCK_MODULATION (0x0000019A)
1155 @param EAX Lower 32-bits of MSR value.
1156 Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.
1157 @param EDX Upper 32-bits of MSR value.
1158 Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.
1160 <b>Example usage</b>
1162 MSR_IA32_CLOCK_MODULATION_REGISTER Msr;
1164 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION);
1165 AsmWriteMsr64 (MSR_IA32_CLOCK_MODULATION, Msr.Uint64);
1167 @note MSR_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.
1169 #define MSR_IA32_CLOCK_MODULATION 0x0000019A
1172 MSR information returned for MSR index #MSR_IA32_CLOCK_MODULATION
1176 /// Individual bit fields
1180 /// [Bit 0] Extended On-Demand Clock Modulation Duty Cycle:. If
1181 /// CPUID.06H:EAX[5] = 1.
1183 UINT32 ExtendedOnDemandClockModulationDutyCycle
:1;
1185 /// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded
1186 /// values for target duty cycle modulation. If CPUID.01H:EDX[22] = 1.
1188 UINT32 OnDemandClockModulationDutyCycle
:3;
1190 /// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation.
1191 /// If CPUID.01H:EDX[22] = 1.
1193 UINT32 OnDemandClockModulationEnable
:1;
1194 UINT32 Reserved1
:27;
1195 UINT32 Reserved2
:32;
1198 /// All bit fields as a 32-bit value
1202 /// All bit fields as a 64-bit value
1205 } MSR_IA32_CLOCK_MODULATION_REGISTER
;
1209 Thermal Interrupt Control (R/W) Enables and disables the generation of an
1210 interrupt on temperature transitions detected with the processor's thermal
1211 sensors and thermal monitor. See Section 14.7.2, "Thermal Monitor.".
1212 If CPUID.01H:EDX[22] = 1
1214 @param ECX MSR_IA32_THERM_INTERRUPT (0x0000019B)
1215 @param EAX Lower 32-bits of MSR value.
1216 Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.
1217 @param EDX Upper 32-bits of MSR value.
1218 Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.
1220 <b>Example usage</b>
1222 MSR_IA32_THERM_INTERRUPT_REGISTER Msr;
1224 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_INTERRUPT);
1225 AsmWriteMsr64 (MSR_IA32_THERM_INTERRUPT, Msr.Uint64);
1227 @note MSR_IA32_THERM_INTERRUPT is defined as IA32_THERM_INTERRUPT in SDM.
1229 #define MSR_IA32_THERM_INTERRUPT 0x0000019B
1232 MSR information returned for MSR index #MSR_IA32_THERM_INTERRUPT
1236 /// Individual bit fields
1240 /// [Bit 0] High-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.
1242 UINT32 HighTempEnable
:1;
1244 /// [Bit 1] Low-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.
1246 UINT32 LowTempEnable
:1;
1248 /// [Bit 2] PROCHOT# Interrupt Enable. If CPUID.01H:EDX[22] = 1.
1250 UINT32 PROCHOT_Enable
:1;
1252 /// [Bit 3] FORCEPR# Interrupt Enable. If CPUID.01H:EDX[22] = 1.
1254 UINT32 FORCEPR_Enable
:1;
1256 /// [Bit 4] Critical Temperature Interrupt Enable.
1257 /// If CPUID.01H:EDX[22] = 1.
1259 UINT32 CriticalTempEnable
:1;
1262 /// [Bits 14:8] Threshold #1 Value. If CPUID.01H:EDX[22] = 1.
1264 UINT32 Threshold1
:7;
1266 /// [Bit 15] Threshold #1 Interrupt Enable. If CPUID.01H:EDX[22] = 1.
1268 UINT32 Threshold1Enable
:1;
1270 /// [Bits 22:16] Threshold #2 Value. If CPUID.01H:EDX[22] = 1.
1272 UINT32 Threshold2
:7;
1274 /// [Bit 23] Threshold #2 Interrupt Enable. If CPUID.01H:EDX[22] = 1.
1276 UINT32 Threshold2Enable
:1;
1278 /// [Bit 24] Power Limit Notification Enable. If CPUID.06H:EAX[4] = 1.
1280 UINT32 PowerLimitNotificationEnable
:1;
1282 UINT32 Reserved3
:32;
1285 /// All bit fields as a 32-bit value
1289 /// All bit fields as a 64-bit value
1292 } MSR_IA32_THERM_INTERRUPT_REGISTER
;
1296 Thermal Status Information (RO) Contains status information about the
1297 processor's thermal sensor and automatic thermal monitoring facilities. See
1298 Section 14.7.2, "Thermal Monitor". If CPUID.01H:EDX[22] = 1.
1300 @param ECX MSR_IA32_THERM_STATUS (0x0000019C)
1301 @param EAX Lower 32-bits of MSR value.
1302 Described by the type MSR_IA32_THERM_STATUS_REGISTER.
1303 @param EDX Upper 32-bits of MSR value.
1304 Described by the type MSR_IA32_THERM_STATUS_REGISTER.
1306 <b>Example usage</b>
1308 MSR_IA32_THERM_STATUS_REGISTER Msr;
1310 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_STATUS);
1312 @note MSR_IA32_THERM_STATUS is defined as IA32_THERM_STATUS in SDM.
1314 #define MSR_IA32_THERM_STATUS 0x0000019C
1317 MSR information returned for MSR index #MSR_IA32_THERM_STATUS
1321 /// Individual bit fields
1325 /// [Bit 0] Thermal Status (RO):. If CPUID.01H:EDX[22] = 1.
1327 UINT32 ThermalStatus
:1;
1329 /// [Bit 1] Thermal Status Log (R/W):. If CPUID.01H:EDX[22] = 1.
1331 UINT32 ThermalStatusLog
:1;
1333 /// [Bit 2] PROCHOT # or FORCEPR# event (RO). If CPUID.01H:EDX[22] = 1.
1335 UINT32 PROCHOT_FORCEPR_Event
:1;
1337 /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0). If CPUID.01H:EDX[22] = 1.
1339 UINT32 PROCHOT_FORCEPR_Log
:1;
1341 /// [Bit 4] Critical Temperature Status (RO). If CPUID.01H:EDX[22] = 1.
1343 UINT32 CriticalTempStatus
:1;
1345 /// [Bit 5] Critical Temperature Status log (R/WC0).
1346 /// If CPUID.01H:EDX[22] = 1.
1348 UINT32 CriticalTempStatusLog
:1;
1350 /// [Bit 6] Thermal Threshold #1 Status (RO). If CPUID.01H:ECX[8] = 1.
1352 UINT32 ThermalThreshold1Status
:1;
1354 /// [Bit 7] Thermal Threshold #1 log (R/WC0). If CPUID.01H:ECX[8] = 1.
1356 UINT32 ThermalThreshold1Log
:1;
1358 /// [Bit 8] Thermal Threshold #2 Status (RO). If CPUID.01H:ECX[8] = 1.
1360 UINT32 ThermalThreshold2Status
:1;
1362 /// [Bit 9] Thermal Threshold #2 log (R/WC0). If CPUID.01H:ECX[8] = 1.
1364 UINT32 ThermalThreshold2Log
:1;
1366 /// [Bit 10] Power Limitation Status (RO). If CPUID.06H:EAX[4] = 1.
1368 UINT32 PowerLimitStatus
:1;
1370 /// [Bit 11] Power Limitation log (R/WC0). If CPUID.06H:EAX[4] = 1.
1372 UINT32 PowerLimitLog
:1;
1374 /// [Bit 12] Current Limit Status (RO). If CPUID.06H:EAX[7] = 1.
1376 UINT32 CurrentLimitStatus
:1;
1378 /// [Bit 13] Current Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.
1380 UINT32 CurrentLimitLog
:1;
1382 /// [Bit 14] Cross Domain Limit Status (RO). If CPUID.06H:EAX[7] = 1.
1384 UINT32 CrossDomainLimitStatus
:1;
1386 /// [Bit 15] Cross Domain Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.
1388 UINT32 CrossDomainLimitLog
:1;
1390 /// [Bits 22:16] Digital Readout (RO). If CPUID.06H:EAX[0] = 1.
1392 UINT32 DigitalReadout
:7;
1395 /// [Bits 30:27] Resolution in Degrees Celsius (RO). If CPUID.06H:EAX[0] =
1398 UINT32 ResolutionInDegreesCelsius
:4;
1400 /// [Bit 31] Reading Valid (RO). If CPUID.06H:EAX[0] = 1.
1402 UINT32 ReadingValid
:1;
1403 UINT32 Reserved2
:32;
1406 /// All bit fields as a 32-bit value
1410 /// All bit fields as a 64-bit value
1413 } MSR_IA32_THERM_STATUS_REGISTER
;
1417 Enable Misc. Processor Features (R/W) Allows a variety of processor
1418 functions to be enabled and disabled.
1420 @param ECX MSR_IA32_MISC_ENABLE (0x000001A0)
1421 @param EAX Lower 32-bits of MSR value.
1422 Described by the type MSR_IA32_MISC_ENABLE_REGISTER.
1423 @param EDX Upper 32-bits of MSR value.
1424 Described by the type MSR_IA32_MISC_ENABLE_REGISTER.
1426 <b>Example usage</b>
1428 MSR_IA32_MISC_ENABLE_REGISTER Msr;
1430 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);
1431 AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, Msr.Uint64);
1433 @note MSR_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
1435 #define MSR_IA32_MISC_ENABLE 0x000001A0
1438 MSR information returned for MSR index #MSR_IA32_MISC_ENABLE
1442 /// Individual bit fields
1446 /// [Bit 0] Fast-Strings Enable When set, the fast-strings feature (for
1447 /// REP MOVS and REP STORS) is enabled (default); when clear, fast-strings
1448 /// are disabled. Introduced at Display Family / Display Model 0F_0H.
1450 UINT32 FastStrings
:1;
1453 /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting
1454 /// this bit enables the thermal control circuit (TCC) portion of the
1455 /// Intel Thermal Monitor feature. This allows the processor to
1456 /// automatically reduce power consumption in response to TCC activation.
1457 /// 0 = Disabled. Note: In some products clearing this bit might be
1458 /// ignored in critical thermal conditions, and TM1, TM2 and adaptive
1459 /// thermal throttling will still be activated. The default value of this
1460 /// field varies with product. See respective tables where default value is
1461 /// listed. Introduced at Display Family / Display Model 0F_0H.
1463 UINT32 AutomaticThermalControlCircuit
:1;
1466 /// [Bit 7] Performance Monitoring Available (R) 1 = Performance
1467 /// monitoring enabled 0 = Performance monitoring disabled. Introduced at
1468 /// Display Family / Display Model 0F_0H.
1470 UINT32 PerformanceMonitoring
:1;
1473 /// [Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't
1474 /// support branch trace storage (BTS) 0 = BTS is supported. Introduced at
1475 /// Display Family / Display Model 0F_0H.
1479 /// [Bit 12] Processor Event Based Sampling (PEBS) Unavailable (RO) 1 =
1480 /// PEBS is not supported; 0 = PEBS is supported. Introduced at Display
1481 /// Family / Display Model 06_0FH.
1486 /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 0= Enhanced
1487 /// Intel SpeedStep Technology disabled 1 = Enhanced Intel SpeedStep
1488 /// Technology enabled. If CPUID.01H: ECX[7] =1.
1493 /// [Bit 18] ENABLE MONITOR FSM (R/W) When this bit is set to 0, the
1494 /// MONITOR feature flag is not set (CPUID.01H:ECX[bit 3] = 0). This
1495 /// indicates that MONITOR/MWAIT are not supported. Software attempts to
1496 /// execute MONITOR/MWAIT will cause #UD when this bit is 0. When this bit
1497 /// is set to 1 (default), MONITOR/MWAIT are supported (CPUID.01H:ECX[bit
1498 /// 3] = 1). If the SSE3 feature flag ECX[0] is not set (CPUID.01H:ECX[bit
1499 /// 0] = 0), the OS must not attempt to alter this bit. BIOS must leave it
1500 /// in the default state. Writing this bit when the SSE3 feature flag is
1501 /// set to 0 may generate a #GP exception. Introduced at Display Family /
1502 /// Display Model 0F_03H.
1507 /// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H
1508 /// returns a maximum value in EAX[7:0] of 2. BIOS should contain a setup
1509 /// question that allows users to specify when the installed OS does not
1510 /// support CPUID functions greater than 2. Before setting this bit, BIOS
1511 /// must execute the CPUID.0H and examine the maximum value returned in
1512 /// EAX[7:0]. If the maximum value is greater than 2, this bit is
1513 /// supported. Otherwise, this bit is not supported. Setting this bit when
1514 /// the maximum value is not greater than 2 may generate a #GP exception.
1515 /// Setting this bit may cause unexpected behavior in software that
1516 /// depends on the availability of CPUID leaves greater than 2. Introduced
1517 /// at Display Family / Display Model 0F_03H.
1519 UINT32 LimitCpuidMaxval
:1;
1521 /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are
1522 /// disabled. xTPR messages are optional messages that allow the processor
1523 /// to inform the chipset of its priority. if CPUID.01H:ECX[14] = 1.
1525 UINT32 xTPR_Message_Disable
:1;
1529 /// [Bit 34] XD Bit Disable (R/W) When set to 1, the Execute Disable Bit
1530 /// feature (XD Bit) is disabled and the XD Bit extended feature flag will
1531 /// be clear (CPUID.80000001H: EDX[20]=0). When set to a 0 (default), the
1532 /// Execute Disable Bit feature (if available) allows the OS to enable PAE
1533 /// paging and take advantage of data only pages. BIOS must not alter the
1534 /// contents of this bit location, if XD bit is not supported. Writing
1535 /// this bit to 1 when the XD Bit extended feature flag is set to 0 may
1536 /// generate a #GP exception. if CPUID.80000001H:EDX[2 0] = 1.
1539 UINT32 Reserved9
:29;
1542 /// All bit fields as a 64-bit value
1545 } MSR_IA32_MISC_ENABLE_REGISTER
;
1549 Performance Energy Bias Hint (R/W). if CPUID.6H:ECX[3] = 1.
1551 @param ECX MSR_IA32_ENERGY_PERF_BIAS (0x000001B0)
1552 @param EAX Lower 32-bits of MSR value.
1553 Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.
1554 @param EDX Upper 32-bits of MSR value.
1555 Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.
1557 <b>Example usage</b>
1559 MSR_IA32_ENERGY_PERF_BIAS_REGISTER Msr;
1561 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_ENERGY_PERF_BIAS);
1562 AsmWriteMsr64 (MSR_IA32_ENERGY_PERF_BIAS, Msr.Uint64);
1564 @note MSR_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.
1566 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0
1569 MSR information returned for MSR index #MSR_IA32_ENERGY_PERF_BIAS
1573 /// Individual bit fields
1577 /// [Bits 3:0] Power Policy Preference: 0 indicates preference to highest
1578 /// performance. 15 indicates preference to maximize energy saving.
1580 UINT32 PowerPolicyPreference
:4;
1581 UINT32 Reserved1
:28;
1582 UINT32 Reserved2
:32;
1585 /// All bit fields as a 32-bit value
1589 /// All bit fields as a 64-bit value
1592 } MSR_IA32_ENERGY_PERF_BIAS_REGISTER
;
1596 Package Thermal Status Information (RO) Contains status information about
1597 the package's thermal sensor. See Section 14.8, "Package Level Thermal
1598 Management.". If CPUID.06H: EAX[6] = 1.
1600 @param ECX MSR_IA32_PACKAGE_THERM_STATUS (0x000001B1)
1601 @param EAX Lower 32-bits of MSR value.
1602 Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.
1603 @param EDX Upper 32-bits of MSR value.
1604 Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.
1606 <b>Example usage</b>
1608 MSR_IA32_PACKAGE_THERM_STATUS_REGISTER Msr;
1610 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_STATUS);
1612 @note MSR_IA32_PACKAGE_THERM_STATUS is defined as IA32_PACKAGE_THERM_STATUS in SDM.
1614 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1
1617 MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_STATUS
1621 /// Individual bit fields
1625 /// [Bit 0] Pkg Thermal Status (RO):.
1627 UINT32 ThermalStatus
:1;
1629 /// [Bit 1] Pkg Thermal Status Log (R/W):.
1631 UINT32 ThermalStatusLog
:1;
1633 /// [Bit 2] Pkg PROCHOT # event (RO).
1635 UINT32 PROCHOT_Event
:1;
1637 /// [Bit 3] Pkg PROCHOT # log (R/WC0).
1639 UINT32 PROCHOT_Log
:1;
1641 /// [Bit 4] Pkg Critical Temperature Status (RO).
1643 UINT32 CriticalTempStatus
:1;
1645 /// [Bit 5] Pkg Critical Temperature Status log (R/WC0).
1647 UINT32 CriticalTempStatusLog
:1;
1649 /// [Bit 6] Pkg Thermal Threshold #1 Status (RO).
1651 UINT32 ThermalThreshold1Status
:1;
1653 /// [Bit 7] Pkg Thermal Threshold #1 log (R/WC0).
1655 UINT32 ThermalThreshold1Log
:1;
1657 /// [Bit 8] Pkg Thermal Threshold #2 Status (RO).
1659 UINT32 ThermalThreshold2Status
:1;
1661 /// [Bit 9] Pkg Thermal Threshold #1 log (R/WC0).
1663 UINT32 ThermalThreshold2Log
:1;
1665 /// [Bit 10] Pkg Power Limitation Status (RO).
1667 UINT32 PowerLimitStatus
:1;
1669 /// [Bit 11] Pkg Power Limitation log (R/WC0).
1671 UINT32 PowerLimitLog
:1;
1674 /// [Bits 22:16] Pkg Digital Readout (RO).
1676 UINT32 DigitalReadout
:7;
1678 UINT32 Reserved3
:32;
1681 /// All bit fields as a 32-bit value
1685 /// All bit fields as a 64-bit value
1688 } MSR_IA32_PACKAGE_THERM_STATUS_REGISTER
;
1692 Pkg Thermal Interrupt Control (R/W) Enables and disables the generation of
1693 an interrupt on temperature transitions detected with the package's thermal
1694 sensor. See Section 14.8, "Package Level Thermal Management.". If CPUID.06H:
1697 @param ECX MSR_IA32_PACKAGE_THERM_INTERRUPT (0x000001B2)
1698 @param EAX Lower 32-bits of MSR value.
1699 Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.
1700 @param EDX Upper 32-bits of MSR value.
1701 Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.
1703 <b>Example usage</b>
1705 MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER Msr;
1707 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT);
1708 AsmWriteMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT, Msr.Uint64);
1710 @note MSR_IA32_PACKAGE_THERM_INTERRUPT is defined as IA32_PACKAGE_THERM_INTERRUPT in SDM.
1712 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2
1715 MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_INTERRUPT
1719 /// Individual bit fields
1723 /// [Bit 0] Pkg High-Temperature Interrupt Enable.
1725 UINT32 HighTempEnable
:1;
1727 /// [Bit 1] Pkg Low-Temperature Interrupt Enable.
1729 UINT32 LowTempEnable
:1;
1731 /// [Bit 2] Pkg PROCHOT# Interrupt Enable.
1733 UINT32 PROCHOT_Enable
:1;
1736 /// [Bit 4] Pkg Overheat Interrupt Enable.
1738 UINT32 OverheatEnable
:1;
1741 /// [Bits 14:8] Pkg Threshold #1 Value.
1743 UINT32 Threshold1
:7;
1745 /// [Bit 15] Pkg Threshold #1 Interrupt Enable.
1747 UINT32 Threshold1Enable
:1;
1749 /// [Bits 22:16] Pkg Threshold #2 Value.
1751 UINT32 Threshold2
:7;
1753 /// [Bit 23] Pkg Threshold #2 Interrupt Enable.
1755 UINT32 Threshold2Enable
:1;
1757 /// [Bit 24] Pkg Power Limit Notification Enable.
1759 UINT32 PowerLimitNotificationEnable
:1;
1761 UINT32 Reserved4
:32;
1764 /// All bit fields as a 32-bit value
1768 /// All bit fields as a 64-bit value
1771 } MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER
;
1775 Trace/Profile Resource Control (R/W). Introduced at Display Family / Display
1778 @param ECX MSR_IA32_DEBUGCTL (0x000001D9)
1779 @param EAX Lower 32-bits of MSR value.
1780 Described by the type MSR_IA32_DEBUGCTL_REGISTER.
1781 @param EDX Upper 32-bits of MSR value.
1782 Described by the type MSR_IA32_DEBUGCTL_REGISTER.
1784 <b>Example usage</b>
1786 MSR_IA32_DEBUGCTL_REGISTER Msr;
1788 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUGCTL);
1789 AsmWriteMsr64 (MSR_IA32_DEBUGCTL, Msr.Uint64);
1791 @note MSR_IA32_DEBUGCTL is defined as IA32_DEBUGCTL in SDM.
1793 #define MSR_IA32_DEBUGCTL 0x000001D9
1796 MSR information returned for MSR index #MSR_IA32_DEBUGCTL
1800 /// Individual bit fields
1804 /// [Bit 0] LBR: Setting this bit to 1 enables the processor to record a
1805 /// running trace of the most recent branches taken by the processor in
1806 /// the LBR stack. Introduced at Display Family / Display Model 06_01H.
1810 /// [Bit 1] BTF: Setting this bit to 1 enables the processor to treat
1811 /// EFLAGS.TF as single-step on branches instead of single-step on
1812 /// instructions. Introduced at Display Family / Display Model 06_01H.
1817 /// [Bit 6] TR: Setting this bit to 1 enables branch trace messages to be
1818 /// sent. Introduced at Display Family / Display Model 06_0EH.
1822 /// [Bit 7] BTS: Setting this bit enables branch trace messages (BTMs) to
1823 /// be logged in a BTS buffer. Introduced at Display Family / Display
1828 /// [Bit 8] BTINT: When clear, BTMs are logged in a BTS buffer in circular
1829 /// fashion. When this bit is set, an interrupt is generated by the BTS
1830 /// facility when the BTS buffer is full. Introduced at Display Family /
1831 /// Display Model 06_0EH.
1835 /// [Bit 9] BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0.
1836 /// Introduced at Display Family / Display Model 06_0FH.
1838 UINT32 BTS_OFF_OS
:1;
1840 /// [Bit 10] BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0.
1841 /// Introduced at Display Family / Display Model 06_0FH.
1843 UINT32 BTS_OFF_USR
:1;
1845 /// [Bit 11] FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a
1846 /// PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.
1848 UINT32 FREEZE_LBRS_ON_PMI
:1;
1850 /// [Bit 12] FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the
1851 /// global counter control MSR are frozen (address 38FH) on a PMI request.
1852 /// If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.
1854 UINT32 FREEZE_PERFMON_ON_PMI
:1;
1856 /// [Bit 13] ENABLE_UNCORE_PMI: When set, enables the logical processor to
1857 /// receive and generate PMI on behalf of the uncore. Introduced at
1858 /// Display Family / Display Model 06_1AH.
1860 UINT32 ENABLE_UNCORE_PMI
:1;
1862 /// [Bit 14] FREEZE_WHILE_SMM: When set, freezes perfmon and trace
1863 /// messages while in SMM. If IA32_PERF_CAPABILITIES[ 12] = 1.
1865 UINT32 FREEZE_WHILE_SMM
:1;
1867 /// [Bit 15] RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If
1868 /// (CPUID.(EAX=07H, ECX=0):EBX[11] = 1).
1871 UINT32 Reserved2
:16;
1872 UINT32 Reserved3
:32;
1875 /// All bit fields as a 32-bit value
1879 /// All bit fields as a 64-bit value
1882 } MSR_IA32_DEBUGCTL_REGISTER
;
1886 SMRR Base Address (Writeable only in SMM) Base address of SMM memory range.
1887 If IA32_MTRRCAP.SMRR[11] = 1.
1889 @param ECX MSR_IA32_SMRR_PHYSBASE (0x000001F2)
1890 @param EAX Lower 32-bits of MSR value.
1891 Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.
1892 @param EDX Upper 32-bits of MSR value.
1893 Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.
1895 <b>Example usage</b>
1897 MSR_IA32_SMRR_PHYSBASE_REGISTER Msr;
1899 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSBASE);
1900 AsmWriteMsr64 (MSR_IA32_SMRR_PHYSBASE, Msr.Uint64);
1902 @note MSR_IA32_SMRR_PHYSBASE is defined as IA32_SMRR_PHYSBASE in SDM.
1904 #define MSR_IA32_SMRR_PHYSBASE 0x000001F2
1907 MSR information returned for MSR index #MSR_IA32_SMRR_PHYSBASE
1911 /// Individual bit fields
1915 /// [Bits 7:0] Type. Specifies memory type of the range.
1920 /// [Bits 31:12] PhysBase. SMRR physical Base Address.
1923 UINT32 Reserved2
:32;
1926 /// All bit fields as a 32-bit value
1930 /// All bit fields as a 64-bit value
1933 } MSR_IA32_SMRR_PHYSBASE_REGISTER
;
1937 SMRR Range Mask. (Writeable only in SMM) Range Mask of SMM memory range. If
1938 IA32_MTRRCAP[SMRR] = 1.
1940 @param ECX MSR_IA32_SMRR_PHYSMASK (0x000001F3)
1941 @param EAX Lower 32-bits of MSR value.
1942 Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.
1943 @param EDX Upper 32-bits of MSR value.
1944 Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.
1946 <b>Example usage</b>
1948 MSR_IA32_SMRR_PHYSMASK_REGISTER Msr;
1950 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSMASK);
1951 AsmWriteMsr64 (MSR_IA32_SMRR_PHYSMASK, Msr.Uint64);
1953 @note MSR_IA32_SMRR_PHYSMASK is defined as IA32_SMRR_PHYSMASK in SDM.
1955 #define MSR_IA32_SMRR_PHYSMASK 0x000001F3
1958 MSR information returned for MSR index #MSR_IA32_SMRR_PHYSMASK
1962 /// Individual bit fields
1965 UINT32 Reserved1
:11;
1967 /// [Bit 11] Valid Enable range mask.
1971 /// [Bits 31:12] PhysMask SMRR address range mask.
1974 UINT32 Reserved2
:32;
1977 /// All bit fields as a 32-bit value
1981 /// All bit fields as a 64-bit value
1984 } MSR_IA32_SMRR_PHYSMASK_REGISTER
;
1988 DCA Capability (R). If CPUID.01H: ECX[18] = 1.
1990 @param ECX MSR_IA32_PLATFORM_DCA_CAP (0x000001F8)
1991 @param EAX Lower 32-bits of MSR value.
1992 @param EDX Upper 32-bits of MSR value.
1994 <b>Example usage</b>
1998 Msr = AsmReadMsr64 (MSR_IA32_PLATFORM_DCA_CAP);
2000 @note MSR_IA32_PLATFORM_DCA_CAP is defined as IA32_PLATFORM_DCA_CAP in SDM.
2002 #define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8
2006 If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1.
2008 @param ECX MSR_IA32_CPU_DCA_CAP (0x000001F9)
2009 @param EAX Lower 32-bits of MSR value.
2010 @param EDX Upper 32-bits of MSR value.
2012 <b>Example usage</b>
2016 Msr = AsmReadMsr64 (MSR_IA32_CPU_DCA_CAP);
2017 AsmWriteMsr64 (MSR_IA32_CPU_DCA_CAP, Msr);
2019 @note MSR_IA32_CPU_DCA_CAP is defined as IA32_CPU_DCA_CAP in SDM.
2021 #define MSR_IA32_CPU_DCA_CAP 0x000001F9
2025 DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1.
2027 @param ECX MSR_IA32_DCA_0_CAP (0x000001FA)
2028 @param EAX Lower 32-bits of MSR value.
2029 Described by the type MSR_IA32_DCA_0_CAP_REGISTER.
2030 @param EDX Upper 32-bits of MSR value.
2031 Described by the type MSR_IA32_DCA_0_CAP_REGISTER.
2033 <b>Example usage</b>
2035 MSR_IA32_DCA_0_CAP_REGISTER Msr;
2037 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DCA_0_CAP);
2038 AsmWriteMsr64 (MSR_IA32_DCA_0_CAP, Msr.Uint64);
2040 @note MSR_IA32_DCA_0_CAP is defined as IA32_DCA_0_CAP in SDM.
2042 #define MSR_IA32_DCA_0_CAP 0x000001FA
2045 MSR information returned for MSR index #MSR_IA32_DCA_0_CAP
2049 /// Individual bit fields
2053 /// [Bit 0] DCA_ACTIVE: Set by HW when DCA is fuseenabled and no
2054 /// defeatures are set.
2056 UINT32 DCA_ACTIVE
:1;
2058 /// [Bits 2:1] TRANSACTION.
2060 UINT32 TRANSACTION
:2;
2062 /// [Bits 6:3] DCA_TYPE.
2066 /// [Bits 10:7] DCA_QUEUE_SIZE.
2068 UINT32 DCA_QUEUE_SIZE
:4;
2071 /// [Bits 16:13] DCA_DELAY: Writes will update the register but have no HW
2077 /// [Bit 24] SW_BLOCK: SW can request DCA block by setting this bit.
2082 /// [Bit 26] HW_BLOCK: Set when DCA is blocked by HW (e.g. CR0.CD = 1).
2086 UINT32 Reserved5
:32;
2089 /// All bit fields as a 32-bit value
2093 /// All bit fields as a 64-bit value
2096 } MSR_IA32_DCA_0_CAP_REGISTER
;
2100 MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs".
2101 If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.
2103 @param ECX MSR_IA32_MTRR_PHYSBASEn
2104 @param EAX Lower 32-bits of MSR value.
2105 Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.
2106 @param EDX Upper 32-bits of MSR value.
2107 Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.
2109 <b>Example usage</b>
2111 MSR_IA32_MTRR_PHYSBASE_REGISTER Msr;
2113 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);
2114 AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);
2116 @note MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM.
2117 MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM.
2118 MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM.
2119 MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM.
2120 MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM.
2121 MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM.
2122 MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM.
2123 MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM.
2124 MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM.
2125 MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.
2128 #define MSR_IA32_MTRR_PHYSBASE0 0x00000200
2129 #define MSR_IA32_MTRR_PHYSBASE1 0x00000202
2130 #define MSR_IA32_MTRR_PHYSBASE2 0x00000204
2131 #define MSR_IA32_MTRR_PHYSBASE3 0x00000206
2132 #define MSR_IA32_MTRR_PHYSBASE4 0x00000208
2133 #define MSR_IA32_MTRR_PHYSBASE5 0x0000020A
2134 #define MSR_IA32_MTRR_PHYSBASE6 0x0000020C
2135 #define MSR_IA32_MTRR_PHYSBASE7 0x0000020E
2136 #define MSR_IA32_MTRR_PHYSBASE8 0x00000210
2137 #define MSR_IA32_MTRR_PHYSBASE9 0x00000212
2141 MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSBASE0 to
2142 #MSR_IA32_MTRR_PHYSBASE9
2146 /// Individual bit fields
2150 /// [Bits 7:0] Type. Specifies memory type of the range.
2155 /// [Bits 31:12] PhysBase. MTRR physical Base Address.
2159 /// [Bits MAXPHYSADDR:32] PhysBase. Upper bits of MTRR physical Base Address.
2160 /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the
2161 /// maximum physical address range supported by the processor. It is
2162 /// reported by CPUID leaf function 80000008H. If CPUID does not support
2163 /// leaf 80000008H, the processor supports 36-bit physical address size,
2164 /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.
2166 UINT32 PhysBaseHi
:32;
2169 /// All bit fields as a 64-bit value
2172 } MSR_IA32_MTRR_PHYSBASE_REGISTER
;
2176 MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs".
2177 If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.
2179 @param ECX MSR_IA32_MTRR_PHYSMASKn
2180 @param EAX Lower 32-bits of MSR value.
2181 Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.
2182 @param EDX Upper 32-bits of MSR value.
2183 Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.
2185 <b>Example usage</b>
2187 MSR_IA32_MTRR_PHYSMASK_REGISTER Msr;
2189 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);
2190 AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);
2192 @note MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM.
2193 MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM.
2194 MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM.
2195 MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM.
2196 MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM.
2197 MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM.
2198 MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM.
2199 MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM.
2200 MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM.
2201 MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.
2204 #define MSR_IA32_MTRR_PHYSMASK0 0x00000201
2205 #define MSR_IA32_MTRR_PHYSMASK1 0x00000203
2206 #define MSR_IA32_MTRR_PHYSMASK2 0x00000205
2207 #define MSR_IA32_MTRR_PHYSMASK3 0x00000207
2208 #define MSR_IA32_MTRR_PHYSMASK4 0x00000209
2209 #define MSR_IA32_MTRR_PHYSMASK5 0x0000020B
2210 #define MSR_IA32_MTRR_PHYSMASK6 0x0000020D
2211 #define MSR_IA32_MTRR_PHYSMASK7 0x0000020F
2212 #define MSR_IA32_MTRR_PHYSMASK8 0x00000211
2213 #define MSR_IA32_MTRR_PHYSMASK9 0x00000213
2217 MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSMASK0 to
2218 #MSR_IA32_MTRR_PHYSMASK9
2222 /// Individual bit fields
2225 UINT32 Reserved1
:11;
2227 /// [Bit 11] Valid Enable range mask.
2231 /// [Bits 31:12] PhysMask. MTRR address range mask.
2235 /// [Bits MAXPHYSADDR:32] PhysMask. Upper bits of MTRR address range mask.
2236 /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the
2237 /// maximum physical address range supported by the processor. It is
2238 /// reported by CPUID leaf function 80000008H. If CPUID does not support
2239 /// leaf 80000008H, the processor supports 36-bit physical address size,
2240 /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.
2242 UINT32 PhysMaskHi
:32;
2245 /// All bit fields as a 64-bit value
2248 } MSR_IA32_MTRR_PHYSMASK_REGISTER
;
2252 MTRRfix64K_00000. If CPUID.01H: EDX.MTRR[12] =1.
2254 @param ECX MSR_IA32_MTRR_FIX64K_00000 (0x00000250)
2255 @param EAX Lower 32-bits of MSR value.
2256 @param EDX Upper 32-bits of MSR value.
2258 <b>Example usage</b>
2262 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX64K_00000);
2263 AsmWriteMsr64 (MSR_IA32_MTRR_FIX64K_00000, Msr);
2265 @note MSR_IA32_MTRR_FIX64K_00000 is defined as IA32_MTRR_FIX64K_00000 in SDM.
2267 #define MSR_IA32_MTRR_FIX64K_00000 0x00000250
2271 MTRRfix16K_80000. If CPUID.01H: EDX.MTRR[12] =1.
2273 @param ECX MSR_IA32_MTRR_FIX16K_80000 (0x00000258)
2274 @param EAX Lower 32-bits of MSR value.
2275 @param EDX Upper 32-bits of MSR value.
2277 <b>Example usage</b>
2281 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_80000);
2282 AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_80000, Msr);
2284 @note MSR_IA32_MTRR_FIX16K_80000 is defined as IA32_MTRR_FIX16K_80000 in SDM.
2286 #define MSR_IA32_MTRR_FIX16K_80000 0x00000258
2290 MTRRfix16K_A0000. If CPUID.01H: EDX.MTRR[12] =1.
2292 @param ECX MSR_IA32_MTRR_FIX16K_A0000 (0x00000259)
2293 @param EAX Lower 32-bits of MSR value.
2294 @param EDX Upper 32-bits of MSR value.
2296 <b>Example usage</b>
2300 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_A0000);
2301 AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_A0000, Msr);
2303 @note MSR_IA32_MTRR_FIX16K_A0000 is defined as IA32_MTRR_FIX16K_A0000 in SDM.
2305 #define MSR_IA32_MTRR_FIX16K_A0000 0x00000259
2309 See Section 11.11.2.2, "Fixed Range MTRRs.". If CPUID.01H: EDX.MTRR[12] =1.
2311 @param ECX MSR_IA32_MTRR_FIX4K_C0000 (0x00000268)
2312 @param EAX Lower 32-bits of MSR value.
2313 @param EDX Upper 32-bits of MSR value.
2315 <b>Example usage</b>
2319 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C0000);
2320 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C0000, Msr);
2322 @note MSR_IA32_MTRR_FIX4K_C0000 is defined as IA32_MTRR_FIX4K_C0000 in SDM.
2324 #define MSR_IA32_MTRR_FIX4K_C0000 0x00000268
2328 MTRRfix4K_C8000. If CPUID.01H: EDX.MTRR[12] =1.
2330 @param ECX MSR_IA32_MTRR_FIX4K_C8000 (0x00000269)
2331 @param EAX Lower 32-bits of MSR value.
2332 @param EDX Upper 32-bits of MSR value.
2334 <b>Example usage</b>
2338 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C8000);
2339 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C8000, Msr);
2341 @note MSR_IA32_MTRR_FIX4K_C8000 is defined as IA32_MTRR_FIX4K_C8000 in SDM.
2343 #define MSR_IA32_MTRR_FIX4K_C8000 0x00000269
2347 MTRRfix4K_D0000. If CPUID.01H: EDX.MTRR[12] =1.
2349 @param ECX MSR_IA32_MTRR_FIX4K_D0000 (0x0000026A)
2350 @param EAX Lower 32-bits of MSR value.
2351 @param EDX Upper 32-bits of MSR value.
2353 <b>Example usage</b>
2357 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D0000);
2358 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D0000, Msr);
2360 @note MSR_IA32_MTRR_FIX4K_D0000 is defined as IA32_MTRR_FIX4K_D0000 in SDM.
2362 #define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A
2366 MTRRfix4K_D8000. If CPUID.01H: EDX.MTRR[12] =1.
2368 @param ECX MSR_IA32_MTRR_FIX4K_D8000 (0x0000026B)
2369 @param EAX Lower 32-bits of MSR value.
2370 @param EDX Upper 32-bits of MSR value.
2372 <b>Example usage</b>
2376 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D8000);
2377 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D8000, Msr);
2379 @note MSR_IA32_MTRR_FIX4K_D8000 is defined as IA32_MTRR_FIX4K_D8000 in SDM.
2381 #define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B
2385 MTRRfix4K_E0000. If CPUID.01H: EDX.MTRR[12] =1.
2387 @param ECX MSR_IA32_MTRR_FIX4K_E0000 (0x0000026C)
2388 @param EAX Lower 32-bits of MSR value.
2389 @param EDX Upper 32-bits of MSR value.
2391 <b>Example usage</b>
2395 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E0000);
2396 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E0000, Msr);
2398 @note MSR_IA32_MTRR_FIX4K_E0000 is defined as IA32_MTRR_FIX4K_E0000 in SDM.
2400 #define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C
2404 MTRRfix4K_E8000. If CPUID.01H: EDX.MTRR[12] =1.
2406 @param ECX MSR_IA32_MTRR_FIX4K_E8000 (0x0000026D)
2407 @param EAX Lower 32-bits of MSR value.
2408 @param EDX Upper 32-bits of MSR value.
2410 <b>Example usage</b>
2414 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E8000);
2415 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E8000, Msr);
2417 @note MSR_IA32_MTRR_FIX4K_E8000 is defined as IA32_MTRR_FIX4K_E8000 in SDM.
2419 #define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D
2423 MTRRfix4K_F0000. If CPUID.01H: EDX.MTRR[12] =1.
2425 @param ECX MSR_IA32_MTRR_FIX4K_F0000 (0x0000026E)
2426 @param EAX Lower 32-bits of MSR value.
2427 @param EDX Upper 32-bits of MSR value.
2429 <b>Example usage</b>
2433 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F0000);
2434 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F0000, Msr);
2436 @note MSR_IA32_MTRR_FIX4K_F0000 is defined as IA32_MTRR_FIX4K_F0000 in SDM.
2438 #define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E
2442 MTRRfix4K_F8000. If CPUID.01H: EDX.MTRR[12] =1.
2444 @param ECX MSR_IA32_MTRR_FIX4K_F8000 (0x0000026F)
2445 @param EAX Lower 32-bits of MSR value.
2446 @param EDX Upper 32-bits of MSR value.
2448 <b>Example usage</b>
2452 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F8000);
2453 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F8000, Msr);
2455 @note MSR_IA32_MTRR_FIX4K_F8000 is defined as IA32_MTRR_FIX4K_F8000 in SDM.
2457 #define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F
2461 IA32_PAT (R/W). If CPUID.01H: EDX.MTRR[16] =1.
2463 @param ECX MSR_IA32_PAT (0x00000277)
2464 @param EAX Lower 32-bits of MSR value.
2465 Described by the type MSR_IA32_PAT_REGISTER.
2466 @param EDX Upper 32-bits of MSR value.
2467 Described by the type MSR_IA32_PAT_REGISTER.
2469 <b>Example usage</b>
2471 MSR_IA32_PAT_REGISTER Msr;
2473 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PAT);
2474 AsmWriteMsr64 (MSR_IA32_PAT, Msr.Uint64);
2476 @note MSR_IA32_PAT is defined as IA32_PAT in SDM.
2478 #define MSR_IA32_PAT 0x00000277
2481 MSR information returned for MSR index #MSR_IA32_PAT
2485 /// Individual bit fields
2494 /// [Bits 10:8] PA1.
2499 /// [Bits 18:16] PA2.
2504 /// [Bits 26:24] PA3.
2509 /// [Bits 34:32] PA4.
2514 /// [Bits 42:40] PA5.
2519 /// [Bits 50:48] PA6.
2524 /// [Bits 58:56] PA7.
2530 /// All bit fields as a 64-bit value
2533 } MSR_IA32_PAT_REGISTER
;
2537 Provides the programming interface to use corrected MC error signaling
2538 capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.
2540 @param ECX MSR_IA32_MCn_CTL2
2541 @param EAX Lower 32-bits of MSR value.
2542 Described by the type MSR_IA32_MC_CTL2_REGISTER.
2543 @param EDX Upper 32-bits of MSR value.
2544 Described by the type MSR_IA32_MC_CTL2_REGISTER.
2546 <b>Example usage</b>
2548 MSR_IA32_MC_CTL2_REGISTER Msr;
2550 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
2551 AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);
2553 @note MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM.
2554 MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM.
2555 MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM.
2556 MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM.
2557 MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM.
2558 MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM.
2559 MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM.
2560 MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM.
2561 MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM.
2562 MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM.
2563 MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM.
2564 MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM.
2565 MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM.
2566 MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM.
2567 MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM.
2568 MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM.
2569 MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM.
2570 MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM.
2571 MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM.
2572 MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM.
2573 MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM.
2574 MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM.
2575 MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM.
2576 MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM.
2577 MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM.
2578 MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM.
2579 MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM.
2580 MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM.
2581 MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM.
2582 MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM.
2583 MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM.
2584 MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.
2587 #define MSR_IA32_MC0_CTL2 0x00000280
2588 #define MSR_IA32_MC1_CTL2 0x00000281
2589 #define MSR_IA32_MC2_CTL2 0x00000282
2590 #define MSR_IA32_MC3_CTL2 0x00000283
2591 #define MSR_IA32_MC4_CTL2 0x00000284
2592 #define MSR_IA32_MC5_CTL2 0x00000285
2593 #define MSR_IA32_MC6_CTL2 0x00000286
2594 #define MSR_IA32_MC7_CTL2 0x00000287
2595 #define MSR_IA32_MC8_CTL2 0x00000288
2596 #define MSR_IA32_MC9_CTL2 0x00000289
2597 #define MSR_IA32_MC10_CTL2 0x0000028A
2598 #define MSR_IA32_MC11_CTL2 0x0000028B
2599 #define MSR_IA32_MC12_CTL2 0x0000028C
2600 #define MSR_IA32_MC13_CTL2 0x0000028D
2601 #define MSR_IA32_MC14_CTL2 0x0000028E
2602 #define MSR_IA32_MC15_CTL2 0x0000028F
2603 #define MSR_IA32_MC16_CTL2 0x00000290
2604 #define MSR_IA32_MC17_CTL2 0x00000291
2605 #define MSR_IA32_MC18_CTL2 0x00000292
2606 #define MSR_IA32_MC19_CTL2 0x00000293
2607 #define MSR_IA32_MC20_CTL2 0x00000294
2608 #define MSR_IA32_MC21_CTL2 0x00000295
2609 #define MSR_IA32_MC22_CTL2 0x00000296
2610 #define MSR_IA32_MC23_CTL2 0x00000297
2611 #define MSR_IA32_MC24_CTL2 0x00000298
2612 #define MSR_IA32_MC25_CTL2 0x00000299
2613 #define MSR_IA32_MC26_CTL2 0x0000029A
2614 #define MSR_IA32_MC27_CTL2 0x0000029B
2615 #define MSR_IA32_MC28_CTL2 0x0000029C
2616 #define MSR_IA32_MC29_CTL2 0x0000029D
2617 #define MSR_IA32_MC30_CTL2 0x0000029E
2618 #define MSR_IA32_MC31_CTL2 0x0000029F
2622 MSR information returned for MSR indexes #MSR_IA32_MC0_CTL2
2623 to #MSR_IA32_MC31_CTL2
2627 /// Individual bit fields
2631 /// [Bits 14:0] Corrected error count threshold.
2633 UINT32 CorrectedErrorCountThreshold
:15;
2634 UINT32 Reserved1
:15;
2636 /// [Bit 30] CMCI_EN.
2640 UINT32 Reserved3
:32;
2643 /// All bit fields as a 32-bit value
2647 /// All bit fields as a 64-bit value
2650 } MSR_IA32_MC_CTL2_REGISTER
;
2654 MTRRdefType (R/W). If CPUID.01H: EDX.MTRR[12] =1.
2656 @param ECX MSR_IA32_MTRR_DEF_TYPE (0x000002FF)
2657 @param EAX Lower 32-bits of MSR value.
2658 Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.
2659 @param EDX Upper 32-bits of MSR value.
2660 Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.
2662 <b>Example usage</b>
2664 MSR_IA32_MTRR_DEF_TYPE_REGISTER Msr;
2666 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);
2667 AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, Msr.Uint64);
2669 @note MSR_IA32_MTRR_DEF_TYPE is defined as IA32_MTRR_DEF_TYPE in SDM.
2671 #define MSR_IA32_MTRR_DEF_TYPE 0x000002FF
2674 MSR information returned for MSR index #MSR_IA32_MTRR_DEF_TYPE
2678 /// Individual bit fields
2682 /// [Bits 2:0] Default Memory Type.
2687 /// [Bit 10] Fixed Range MTRR Enable.
2691 /// [Bit 11] MTRR Enable.
2694 UINT32 Reserved2
:20;
2695 UINT32 Reserved3
:32;
2698 /// All bit fields as a 32-bit value
2702 /// All bit fields as a 64-bit value
2705 } MSR_IA32_MTRR_DEF_TYPE_REGISTER
;
2709 Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any. If
2710 CPUID.0AH: EDX[4:0] > 0.
2712 @param ECX MSR_IA32_FIXED_CTR0 (0x00000309)
2713 @param EAX Lower 32-bits of MSR value.
2714 @param EDX Upper 32-bits of MSR value.
2716 <b>Example usage</b>
2720 Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR0);
2721 AsmWriteMsr64 (MSR_IA32_FIXED_CTR0, Msr);
2723 @note MSR_IA32_FIXED_CTR0 is defined as IA32_FIXED_CTR0 in SDM.
2725 #define MSR_IA32_FIXED_CTR0 0x00000309
2729 Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core. If
2730 CPUID.0AH: EDX[4:0] > 1.
2732 @param ECX MSR_IA32_FIXED_CTR1 (0x0000030A)
2733 @param EAX Lower 32-bits of MSR value.
2734 @param EDX Upper 32-bits of MSR value.
2736 <b>Example usage</b>
2740 Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR1);
2741 AsmWriteMsr64 (MSR_IA32_FIXED_CTR1, Msr);
2743 @note MSR_IA32_FIXED_CTR1 is defined as IA32_FIXED_CTR1 in SDM.
2745 #define MSR_IA32_FIXED_CTR1 0x0000030A
2749 Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref. If
2750 CPUID.0AH: EDX[4:0] > 2.
2752 @param ECX MSR_IA32_FIXED_CTR2 (0x0000030B)
2753 @param EAX Lower 32-bits of MSR value.
2754 @param EDX Upper 32-bits of MSR value.
2756 <b>Example usage</b>
2760 Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR2);
2761 AsmWriteMsr64 (MSR_IA32_FIXED_CTR2, Msr);
2763 @note MSR_IA32_FIXED_CTR2 is defined as IA32_FIXED_CTR2 in SDM.
2765 #define MSR_IA32_FIXED_CTR2 0x0000030B
2769 RO. If CPUID.01H: ECX[15] = 1.
2771 @param ECX MSR_IA32_PERF_CAPABILITIES (0x00000345)
2772 @param EAX Lower 32-bits of MSR value.
2773 Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.
2774 @param EDX Upper 32-bits of MSR value.
2775 Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.
2777 <b>Example usage</b>
2779 MSR_IA32_PERF_CAPABILITIES_REGISTER Msr;
2781 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CAPABILITIES);
2782 AsmWriteMsr64 (MSR_IA32_PERF_CAPABILITIES, Msr.Uint64);
2784 @note MSR_IA32_PERF_CAPABILITIES is defined as IA32_PERF_CAPABILITIES in SDM.
2786 #define MSR_IA32_PERF_CAPABILITIES 0x00000345
2789 MSR information returned for MSR index #MSR_IA32_PERF_CAPABILITIES
2793 /// Individual bit fields
2797 /// [Bits 5:0] LBR format.
2801 /// [Bit 6] PEBS Trap.
2805 /// [Bit 7] PEBSSaveArchRegs.
2807 UINT32 PEBS_ARCH_REG
:1;
2809 /// [Bits 11:8] PEBS Record Format.
2811 UINT32 PEBS_REC_FMT
:4;
2813 /// [Bit 12] 1: Freeze while SMM is supported.
2815 UINT32 SMM_FREEZE
:1;
2817 /// [Bit 13] 1: Full width of counter writable via IA32_A_PMCx.
2820 UINT32 Reserved1
:18;
2821 UINT32 Reserved2
:32;
2824 /// All bit fields as a 32-bit value
2828 /// All bit fields as a 64-bit value
2831 } MSR_IA32_PERF_CAPABILITIES_REGISTER
;
2835 Fixed-Function Performance Counter Control (R/W) Counter increments while
2836 the results of ANDing respective enable bit in IA32_PERF_GLOBAL_CTRL with
2837 the corresponding OS or USR bits in this MSR is true. If CPUID.0AH: EAX[7:0]
2840 @param ECX MSR_IA32_FIXED_CTR_CTRL (0x0000038D)
2841 @param EAX Lower 32-bits of MSR value.
2842 Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.
2843 @param EDX Upper 32-bits of MSR value.
2844 Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.
2846 <b>Example usage</b>
2848 MSR_IA32_FIXED_CTR_CTRL_REGISTER Msr;
2850 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FIXED_CTR_CTRL);
2851 AsmWriteMsr64 (MSR_IA32_FIXED_CTR_CTRL, Msr.Uint64);
2853 @note MSR_IA32_FIXED_CTR_CTRL is defined as IA32_FIXED_CTR_CTRL in SDM.
2855 #define MSR_IA32_FIXED_CTR_CTRL 0x0000038D
2858 MSR information returned for MSR index #MSR_IA32_FIXED_CTR_CTRL
2862 /// Individual bit fields
2866 /// [Bit 0] EN0_OS: Enable Fixed Counter 0 to count while CPL = 0.
2870 /// [Bit 1] EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0.
2874 /// [Bit 2] AnyThread: When set to 1, it enables counting the associated
2875 /// event conditions occurring across all logical processors sharing a
2876 /// processor core. When set to 0, the counter only increments the
2877 /// associated event conditions occurring in the logical processor which
2878 /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
2880 UINT32 AnyThread0
:1;
2882 /// [Bit 3] EN0_PMI: Enable PMI when fixed counter 0 overflows.
2886 /// [Bit 4] EN1_OS: Enable Fixed Counter 1 to count while CPL = 0.
2890 /// [Bit 5] EN1_Usr: Enable Fixed Counter 1 to count while CPL > 0.
2894 /// [Bit 6] AnyThread: When set to 1, it enables counting the associated
2895 /// event conditions occurring across all logical processors sharing a
2896 /// processor core. When set to 0, the counter only increments the
2897 /// associated event conditions occurring in the logical processor which
2898 /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
2900 UINT32 AnyThread1
:1;
2902 /// [Bit 7] EN1_PMI: Enable PMI when fixed counter 1 overflows.
2906 /// [Bit 8] EN2_OS: Enable Fixed Counter 2 to count while CPL = 0.
2910 /// [Bit 9] EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0.
2914 /// [Bit 10] AnyThread: When set to 1, it enables counting the associated
2915 /// event conditions occurring across all logical processors sharing a
2916 /// processor core. When set to 0, the counter only increments the
2917 /// associated event conditions occurring in the logical processor which
2918 /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
2920 UINT32 AnyThread2
:1;
2922 /// [Bit 11] EN2_PMI: Enable PMI when fixed counter 2 overflows.
2925 UINT32 Reserved1
:20;
2926 UINT32 Reserved2
:32;
2929 /// All bit fields as a 32-bit value
2933 /// All bit fields as a 64-bit value
2936 } MSR_IA32_FIXED_CTR_CTRL_REGISTER
;
2940 Global Performance Counter Status (RO). If CPUID.0AH: EAX[7:0] > 0.
2942 @param ECX MSR_IA32_PERF_GLOBAL_STATUS (0x0000038E)
2943 @param EAX Lower 32-bits of MSR value.
2944 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.
2945 @param EDX Upper 32-bits of MSR value.
2946 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.
2948 <b>Example usage</b>
2950 MSR_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;
2952 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS);
2954 @note MSR_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
2956 #define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E
2959 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS
2963 /// Individual bit fields
2967 /// [Bit 0] Ovf_PMC0: Overflow status of IA32_PMC0. If CPUID.0AH:
2972 /// [Bit 1] Ovf_PMC1: Overflow status of IA32_PMC1. If CPUID.0AH:
2977 /// [Bit 2] Ovf_PMC2: Overflow status of IA32_PMC2. If CPUID.0AH:
2982 /// [Bit 3] Ovf_PMC3: Overflow status of IA32_PMC3. If CPUID.0AH:
2986 UINT32 Reserved1
:28;
2988 /// [Bit 32] Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0. If
2989 /// CPUID.0AH: EAX[7:0] > 1.
2991 UINT32 Ovf_FixedCtr0
:1;
2993 /// [Bit 33] Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1. If
2994 /// CPUID.0AH: EAX[7:0] > 1.
2996 UINT32 Ovf_FixedCtr1
:1;
2998 /// [Bit 34] Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2. If
2999 /// CPUID.0AH: EAX[7:0] > 1.
3001 UINT32 Ovf_FixedCtr2
:1;
3002 UINT32 Reserved2
:20;
3004 /// [Bit 55] Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory
3005 /// buffer was completely filled. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1)
3006 /// && IA32_RTIT_CTL.ToPA = 1.
3008 UINT32 Trace_ToPA_PMI
:1;
3011 /// [Bit 58] LBR_Frz: LBRs are frozen due to -
3012 /// IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1, - The LBR stack overflowed. If
3013 /// CPUID.0AH: EAX[7:0] > 3.
3017 /// [Bit 59] CTR_Frz: Performance counters in the core PMU are frozen due
3018 /// to - IA32_DEBUGCTL.FREEZE_PERFMON_ON_ PMI=1, - one or more core PMU
3019 /// counters overflowed. If CPUID.0AH: EAX[7:0] > 3.
3023 /// [Bit 60] ASCI: Data in the performance counters in the core PMU may
3024 /// include contributions from the direct or indirect operation intel SGX
3025 /// to protect an enclave. If CPUID.(EAX=07H, ECX=0):EBX[2] = 1.
3029 /// [Bit 61] Ovf_Uncore: Uncore counter overflow status. If CPUID.0AH:
3032 UINT32 Ovf_Uncore
:1;
3034 /// [Bit 62] OvfBuf: DS SAVE area Buffer overflow status. If CPUID.0AH:
3039 /// [Bit 63] CondChgd: status bits of this register has changed. If
3040 /// CPUID.0AH: EAX[7:0] > 0.
3045 /// All bit fields as a 64-bit value
3048 } MSR_IA32_PERF_GLOBAL_STATUS_REGISTER
;
3052 Global Performance Counter Control (R/W) Counter increments while the result
3053 of ANDing respective enable bit in this MSR with the corresponding OS or USR
3054 bits in the general-purpose or fixed counter control MSR is true. If
3055 CPUID.0AH: EAX[7:0] > 0.
3057 @param ECX MSR_IA32_PERF_GLOBAL_CTRL (0x0000038F)
3058 @param EAX Lower 32-bits of MSR value.
3059 Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.
3060 @param EDX Upper 32-bits of MSR value.
3061 Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.
3063 <b>Example usage</b>
3065 MSR_IA32_PERF_GLOBAL_CTRL_REGISTER Msr;
3067 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_CTRL);
3068 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);
3070 @note MSR_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.
3072 #define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F
3075 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_CTRL
3079 /// Individual bit fields
3083 /// [Bits 31:0] EN_PMCn. If CPUID.0AH: EAX[15:8] > n.
3084 /// Enable bitmask. Only the first n-1 bits are valid.
3085 /// Bits n..31 are reserved.
3089 /// [Bits 63:32] EN_FIXED_CTRn. If CPUID.0AH: EDX[4:0] > n.
3090 /// Enable bitmask. Only the first n-1 bits are valid.
3091 /// Bits 31:n are reserved.
3093 UINT32 EN_FIXED_CTRn
:32;
3096 /// All bit fields as a 64-bit value
3099 } MSR_IA32_PERF_GLOBAL_CTRL_REGISTER
;
3103 Global Performance Counter Overflow Control (R/W). If CPUID.0AH: EAX[7:0] >
3104 0 && CPUID.0AH: EAX[7:0] <= 3.
3106 @param ECX MSR_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)
3107 @param EAX Lower 32-bits of MSR value.
3108 Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
3109 @param EDX Upper 32-bits of MSR value.
3110 Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
3112 <b>Example usage</b>
3114 MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;
3116 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL);
3117 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);
3119 @note MSR_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.
3121 #define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390
3124 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_OVF_CTRL
3128 /// Individual bit fields
3132 /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.
3133 /// Clear bitmask. Only the first n-1 bits are valid.
3134 /// Bits 31:n are reserved.
3138 /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.
3139 /// If CPUID.0AH: EDX[4:0] > n.
3140 /// Clear bitmask. Only the first n-1 bits are valid.
3141 /// Bits 22:n are reserved.
3143 UINT32 Ovf_FIXED_CTRn
:23;
3145 /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,
3146 /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1.
3148 UINT32 Trace_ToPA_PMI
:1;
3151 /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /
3152 /// Display Model 06_2EH.
3154 UINT32 Ovf_Uncore
:1;
3156 /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.
3160 /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.
3165 /// All bit fields as a 64-bit value
3168 } MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER
;
3172 Global Performance Counter Overflow Reset Control (R/W). If CPUID.0AH:
3175 @param ECX MSR_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)
3176 @param EAX Lower 32-bits of MSR value.
3177 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
3178 @param EDX Upper 32-bits of MSR value.
3179 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
3181 <b>Example usage</b>
3183 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;
3185 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET);
3186 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);
3188 @note MSR_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.
3190 #define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
3193 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_RESET
3197 /// Individual bit fields
3201 /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.
3202 /// Clear bitmask. Only the first n-1 bits are valid.
3203 /// Bits 31:n are reserved.
3207 /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.
3208 /// If CPUID.0AH: EDX[4:0] > n.
3209 /// Clear bitmask. Only the first n-1 bits are valid.
3210 /// Bits 22:n are reserved.
3212 UINT32 Ovf_FIXED_CTRn
:23;
3214 /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,
3215 /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1.
3217 UINT32 Trace_ToPA_PMI
:1;
3220 /// [Bit 58] Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.
3224 /// [Bit 59] Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.
3228 /// [Bit 60] Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3.
3232 /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /
3233 /// Display Model 06_2EH.
3235 UINT32 Ovf_Uncore
:1;
3237 /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.
3241 /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.
3246 /// All bit fields as a 64-bit value
3249 } MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER
;
3253 Global Performance Counter Overflow Set Control (R/W). If CPUID.0AH:
3256 @param ECX MSR_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)
3257 @param EAX Lower 32-bits of MSR value.
3258 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
3259 @param EDX Upper 32-bits of MSR value.
3260 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
3262 <b>Example usage</b>
3264 MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;
3266 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET);
3267 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);
3269 @note MSR_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.
3271 #define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391
3274 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_SET
3278 /// Individual bit fields
3282 /// [Bits 31:0] Set 1 to cause Ovf_PMCn = 1. If CPUID.0AH: EAX[7:0] > n.
3283 /// Set bitmask. Only the first n-1 bits are valid.
3284 /// Bits 31:n are reserved.
3288 /// [Bits 54:32] Set 1 to cause Ovf_FIXED_CTRn = 1.
3289 /// If CPUID.0AH: EAX[7:0] > n.
3290 /// Set bitmask. Only the first n-1 bits are valid.
3291 /// Bits 22:n are reserved.
3293 UINT32 Ovf_FIXED_CTRn
:23;
3295 /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1. If CPUID.0AH: EAX[7:0] > 3.
3297 UINT32 Trace_ToPA_PMI
:1;
3300 /// [Bit 58] Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.
3304 /// [Bit 59] Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.
3308 /// [Bit 60] Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3.
3312 /// [Bit 61] Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3.
3314 UINT32 Ovf_Uncore
:1;
3316 /// [Bit 62] Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 3.
3322 /// All bit fields as a 64-bit value
3325 } MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
;
3329 Indicator of core perfmon interface is in use (RO). If CPUID.0AH: EAX[7:0] >
3332 @param ECX MSR_IA32_PERF_GLOBAL_INUSE (0x00000392)
3333 @param EAX Lower 32-bits of MSR value.
3334 Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.
3335 @param EDX Upper 32-bits of MSR value.
3336 Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.
3338 <b>Example usage</b>
3340 MSR_IA32_PERF_GLOBAL_INUSE_REGISTER Msr;
3342 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_INUSE);
3344 @note MSR_IA32_PERF_GLOBAL_INUSE is defined as IA32_PERF_GLOBAL_INUSE in SDM.
3346 #define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392
3349 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_INUSE
3353 /// Individual bit fields
3357 /// [Bits 31:0] IA32_PERFEVTSELn in use. If CPUID.0AH: EAX[7:0] > n.
3358 /// Status bitmask. Only the first n-1 bits are valid.
3359 /// Bits 31:n are reserved.
3361 UINT32 IA32_PERFEVTSELn
:32;
3363 /// [Bits 62:32] IA32_FIXED_CTRn in use.
3364 /// If CPUID.0AH: EAX[7:0] > n.
3365 /// Status bitmask. Only the first n-1 bits are valid.
3366 /// Bits 30:n are reserved.
3368 UINT32 IA32_FIXED_CTRn
:31;
3370 /// [Bit 63] PMI in use.
3375 /// All bit fields as a 64-bit value
3378 } MSR_IA32_PERF_GLOBAL_INUSE_REGISTER
;
3384 @param ECX MSR_IA32_PEBS_ENABLE (0x000003F1)
3385 @param EAX Lower 32-bits of MSR value.
3386 Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.
3387 @param EDX Upper 32-bits of MSR value.
3388 Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.
3390 <b>Example usage</b>
3392 MSR_IA32_PEBS_ENABLE_REGISTER Msr;
3394 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PEBS_ENABLE);
3395 AsmWriteMsr64 (MSR_IA32_PEBS_ENABLE, Msr.Uint64);
3397 @note MSR_IA32_PEBS_ENABLE is defined as IA32_PEBS_ENABLE in SDM.
3399 #define MSR_IA32_PEBS_ENABLE 0x000003F1
3402 MSR information returned for MSR index #MSR_IA32_PEBS_ENABLE
3406 /// Individual bit fields
3410 /// [Bit 0] Enable PEBS on IA32_PMC0. Introduced at Display Family /
3411 /// Display Model 06_0FH.
3415 /// [Bits 3:1] Reserved or Model specific.
3418 UINT32 Reserved2
:28;
3420 /// [Bits 35:32] Reserved or Model specific.
3423 UINT32 Reserved4
:28;
3426 /// All bit fields as a 64-bit value
3429 } MSR_IA32_PEBS_ENABLE_REGISTER
;
3433 MCn_CTL. If IA32_MCG_CAP.CNT > n.
3435 @param ECX MSR_IA32_MCn_CTL
3436 @param EAX Lower 32-bits of MSR value.
3437 @param EDX Upper 32-bits of MSR value.
3439 <b>Example usage</b>
3443 Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
3444 AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);
3446 @note MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM.
3447 MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM.
3448 MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM.
3449 MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM.
3450 MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM.
3451 MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM.
3452 MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM.
3453 MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM.
3454 MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM.
3455 MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM.
3456 MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM.
3457 MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM.
3458 MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM.
3459 MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM.
3460 MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM.
3461 MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM.
3462 MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM.
3463 MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM.
3464 MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM.
3465 MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM.
3466 MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM.
3467 MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM.
3468 MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM.
3469 MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM.
3470 MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM.
3471 MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM.
3472 MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM.
3473 MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM.
3474 MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.
3477 #define MSR_IA32_MC0_CTL 0x00000400
3478 #define MSR_IA32_MC1_CTL 0x00000404
3479 #define MSR_IA32_MC2_CTL 0x00000408
3480 #define MSR_IA32_MC3_CTL 0x0000040C
3481 #define MSR_IA32_MC4_CTL 0x00000410
3482 #define MSR_IA32_MC5_CTL 0x00000414
3483 #define MSR_IA32_MC6_CTL 0x00000418
3484 #define MSR_IA32_MC7_CTL 0x0000041C
3485 #define MSR_IA32_MC8_CTL 0x00000420
3486 #define MSR_IA32_MC9_CTL 0x00000424
3487 #define MSR_IA32_MC10_CTL 0x00000428
3488 #define MSR_IA32_MC11_CTL 0x0000042C
3489 #define MSR_IA32_MC12_CTL 0x00000430
3490 #define MSR_IA32_MC13_CTL 0x00000434
3491 #define MSR_IA32_MC14_CTL 0x00000438
3492 #define MSR_IA32_MC15_CTL 0x0000043C
3493 #define MSR_IA32_MC16_CTL 0x00000440
3494 #define MSR_IA32_MC17_CTL 0x00000444
3495 #define MSR_IA32_MC18_CTL 0x00000448
3496 #define MSR_IA32_MC19_CTL 0x0000044C
3497 #define MSR_IA32_MC20_CTL 0x00000450
3498 #define MSR_IA32_MC21_CTL 0x00000454
3499 #define MSR_IA32_MC22_CTL 0x00000458
3500 #define MSR_IA32_MC23_CTL 0x0000045C
3501 #define MSR_IA32_MC24_CTL 0x00000460
3502 #define MSR_IA32_MC25_CTL 0x00000464
3503 #define MSR_IA32_MC26_CTL 0x00000468
3504 #define MSR_IA32_MC27_CTL 0x0000046C
3505 #define MSR_IA32_MC28_CTL 0x00000470
3510 MCn_STATUS. If IA32_MCG_CAP.CNT > n.
3512 @param ECX MSR_IA32_MCn_STATUS
3513 @param EAX Lower 32-bits of MSR value.
3514 @param EDX Upper 32-bits of MSR value.
3516 <b>Example usage</b>
3520 Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
3521 AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);
3523 @note MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM.
3524 MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM.
3525 MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM.
3526 MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM.
3527 MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM.
3528 MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM.
3529 MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM.
3530 MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM.
3531 MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM.
3532 MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM.
3533 MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM.
3534 MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM.
3535 MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM.
3536 MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM.
3537 MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM.
3538 MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM.
3539 MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM.
3540 MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM.
3541 MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM.
3542 MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM.
3543 MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM.
3544 MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM.
3545 MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM.
3546 MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM.
3547 MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM.
3548 MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM.
3549 MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM.
3550 MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM.
3551 MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.
3554 #define MSR_IA32_MC0_STATUS 0x00000401
3555 #define MSR_IA32_MC1_STATUS 0x00000405
3556 #define MSR_IA32_MC2_STATUS 0x00000409
3557 #define MSR_IA32_MC3_STATUS 0x0000040D
3558 #define MSR_IA32_MC4_STATUS 0x00000411
3559 #define MSR_IA32_MC5_STATUS 0x00000415
3560 #define MSR_IA32_MC6_STATUS 0x00000419
3561 #define MSR_IA32_MC7_STATUS 0x0000041D
3562 #define MSR_IA32_MC8_STATUS 0x00000421
3563 #define MSR_IA32_MC9_STATUS 0x00000425
3564 #define MSR_IA32_MC10_STATUS 0x00000429
3565 #define MSR_IA32_MC11_STATUS 0x0000042D
3566 #define MSR_IA32_MC12_STATUS 0x00000431
3567 #define MSR_IA32_MC13_STATUS 0x00000435
3568 #define MSR_IA32_MC14_STATUS 0x00000439
3569 #define MSR_IA32_MC15_STATUS 0x0000043D
3570 #define MSR_IA32_MC16_STATUS 0x00000441
3571 #define MSR_IA32_MC17_STATUS 0x00000445
3572 #define MSR_IA32_MC18_STATUS 0x00000449
3573 #define MSR_IA32_MC19_STATUS 0x0000044D
3574 #define MSR_IA32_MC20_STATUS 0x00000451
3575 #define MSR_IA32_MC21_STATUS 0x00000455
3576 #define MSR_IA32_MC22_STATUS 0x00000459
3577 #define MSR_IA32_MC23_STATUS 0x0000045D
3578 #define MSR_IA32_MC24_STATUS 0x00000461
3579 #define MSR_IA32_MC25_STATUS 0x00000465
3580 #define MSR_IA32_MC26_STATUS 0x00000469
3581 #define MSR_IA32_MC27_STATUS 0x0000046D
3582 #define MSR_IA32_MC28_STATUS 0x00000471
3587 MCn_ADDR. If IA32_MCG_CAP.CNT > n.
3589 @param ECX MSR_IA32_MCn_ADDR
3590 @param EAX Lower 32-bits of MSR value.
3591 @param EDX Upper 32-bits of MSR value.
3593 <b>Example usage</b>
3597 Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
3598 AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);
3600 @note MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM.
3601 MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM.
3602 MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM.
3603 MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM.
3604 MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM.
3605 MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM.
3606 MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM.
3607 MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM.
3608 MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM.
3609 MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM.
3610 MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM.
3611 MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM.
3612 MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM.
3613 MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM.
3614 MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM.
3615 MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM.
3616 MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM.
3617 MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM.
3618 MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM.
3619 MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM.
3620 MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM.
3621 MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM.
3622 MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM.
3623 MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM.
3624 MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM.
3625 MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM.
3626 MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM.
3627 MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM.
3628 MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.
3631 #define MSR_IA32_MC0_ADDR 0x00000402
3632 #define MSR_IA32_MC1_ADDR 0x00000406
3633 #define MSR_IA32_MC2_ADDR 0x0000040A
3634 #define MSR_IA32_MC3_ADDR 0x0000040E
3635 #define MSR_IA32_MC4_ADDR 0x00000412
3636 #define MSR_IA32_MC5_ADDR 0x00000416
3637 #define MSR_IA32_MC6_ADDR 0x0000041A
3638 #define MSR_IA32_MC7_ADDR 0x0000041E
3639 #define MSR_IA32_MC8_ADDR 0x00000422
3640 #define MSR_IA32_MC9_ADDR 0x00000426
3641 #define MSR_IA32_MC10_ADDR 0x0000042A
3642 #define MSR_IA32_MC11_ADDR 0x0000042E
3643 #define MSR_IA32_MC12_ADDR 0x00000432
3644 #define MSR_IA32_MC13_ADDR 0x00000436
3645 #define MSR_IA32_MC14_ADDR 0x0000043A
3646 #define MSR_IA32_MC15_ADDR 0x0000043E
3647 #define MSR_IA32_MC16_ADDR 0x00000442
3648 #define MSR_IA32_MC17_ADDR 0x00000446
3649 #define MSR_IA32_MC18_ADDR 0x0000044A
3650 #define MSR_IA32_MC19_ADDR 0x0000044E
3651 #define MSR_IA32_MC20_ADDR 0x00000452
3652 #define MSR_IA32_MC21_ADDR 0x00000456
3653 #define MSR_IA32_MC22_ADDR 0x0000045A
3654 #define MSR_IA32_MC23_ADDR 0x0000045E
3655 #define MSR_IA32_MC24_ADDR 0x00000462
3656 #define MSR_IA32_MC25_ADDR 0x00000466
3657 #define MSR_IA32_MC26_ADDR 0x0000046A
3658 #define MSR_IA32_MC27_ADDR 0x0000046E
3659 #define MSR_IA32_MC28_ADDR 0x00000472
3664 MCn_MISC. If IA32_MCG_CAP.CNT > n.
3666 @param ECX MSR_IA32_MCn_MISC
3667 @param EAX Lower 32-bits of MSR value.
3668 @param EDX Upper 32-bits of MSR value.
3670 <b>Example usage</b>
3674 Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
3675 AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);
3677 @note MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM.
3678 MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM.
3679 MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM.
3680 MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM.
3681 MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM.
3682 MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM.
3683 MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.
3684 MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM.
3685 MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM.
3686 MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM.
3687 MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM.
3688 MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM.
3689 MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM.
3690 MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM.
3691 MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM.
3692 MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM.
3693 MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM.
3694 MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM.
3695 MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM.
3696 MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM.
3697 MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM.
3698 MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM.
3699 MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM.
3700 MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM.
3701 MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM.
3702 MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM.
3703 MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM.
3704 MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM.
3705 MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.
3708 #define MSR_IA32_MC0_MISC 0x00000403
3709 #define MSR_IA32_MC1_MISC 0x00000407
3710 #define MSR_IA32_MC2_MISC 0x0000040B
3711 #define MSR_IA32_MC3_MISC 0x0000040F
3712 #define MSR_IA32_MC4_MISC 0x00000413
3713 #define MSR_IA32_MC5_MISC 0x00000417
3714 #define MSR_IA32_MC6_MISC 0x0000041B
3715 #define MSR_IA32_MC7_MISC 0x0000041F
3716 #define MSR_IA32_MC8_MISC 0x00000423
3717 #define MSR_IA32_MC9_MISC 0x00000427
3718 #define MSR_IA32_MC10_MISC 0x0000042B
3719 #define MSR_IA32_MC11_MISC 0x0000042F
3720 #define MSR_IA32_MC12_MISC 0x00000433
3721 #define MSR_IA32_MC13_MISC 0x00000437
3722 #define MSR_IA32_MC14_MISC 0x0000043B
3723 #define MSR_IA32_MC15_MISC 0x0000043F
3724 #define MSR_IA32_MC16_MISC 0x00000443
3725 #define MSR_IA32_MC17_MISC 0x00000447
3726 #define MSR_IA32_MC18_MISC 0x0000044B
3727 #define MSR_IA32_MC19_MISC 0x0000044F
3728 #define MSR_IA32_MC20_MISC 0x00000453
3729 #define MSR_IA32_MC21_MISC 0x00000457
3730 #define MSR_IA32_MC22_MISC 0x0000045B
3731 #define MSR_IA32_MC23_MISC 0x0000045F
3732 #define MSR_IA32_MC24_MISC 0x00000463
3733 #define MSR_IA32_MC25_MISC 0x00000467
3734 #define MSR_IA32_MC26_MISC 0x0000046B
3735 #define MSR_IA32_MC27_MISC 0x0000046F
3736 #define MSR_IA32_MC28_MISC 0x00000473
3741 Reporting Register of Basic VMX Capabilities (R/O) See Appendix A.1, "Basic
3742 VMX Information.". If CPUID.01H:ECX.[5] = 1.
3744 @param ECX MSR_IA32_VMX_BASIC (0x00000480)
3745 @param EAX Lower 32-bits of MSR value.
3746 @param EDX Upper 32-bits of MSR value.
3748 <b>Example usage</b>
3750 MSR_IA32_VMX_BASIC_REGISTER Msr;
3752 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_BASIC);
3754 @note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM.
3756 #define MSR_IA32_VMX_BASIC 0x00000480
3759 MSR information returned for MSR index #MSR_IA32_VMX_BASIC
3763 /// Individual bit fields
3767 /// [Bits 30:0] VMCS revision identifier used by the processor. Processors
3768 /// that use the same VMCS revision identifier use the same size for VMCS
3769 /// regions (see subsequent item on bits 44:32).
3771 /// @note Earlier versions of this manual specified that the VMCS revision
3772 /// identifier was a 32-bit field in bits 31:0 of this MSR. For all
3773 /// processors produced prior to this change, bit 31 of this MSR was read
3776 UINT32 VmcsRevisonId
:31;
3777 UINT32 MustBeZero
:1;
3779 /// [Bit 44:32] Reports the number of bytes that software should allocate
3780 /// for the VMXON region and any VMCS region. It is a value greater than
3781 /// 0 and at most 4096(bit 44 is set if and only if bits 43:32 are clear).
3786 /// [Bit 48] Indicates the width of the physical addresses that may be used
3787 /// for the VMXON region, each VMCS, and data structures referenced by
3788 /// pointers in a VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX
3789 /// transitions). If the bit is 0, these addresses are limited to the
3790 /// processor's physical-address width. If the bit is 1, these addresses
3791 /// are limited to 32 bits. This bit is always 0 for processors that
3792 /// support Intel 64 architecture.
3794 /// @note On processors that support Intel 64 architecture, the pointer
3795 /// must not set bits beyond the processor's physical address width.
3797 UINT32 VmcsAddressWidth
:1;
3799 /// [Bit 49] If bit 49 is read as 1, the logical processor supports the
3800 /// dual-monitor treatment of system-management interrupts and
3801 /// system-management mode. See Section 34.15 for details of this treatment.
3803 UINT32 DualMonitor
:1;
3805 /// [Bit 53:50] report the memory type that should be used for the VMCS,
3806 /// for data structures referenced by pointers in the VMCS (I/O bitmaps,
3807 /// virtual-APIC page, MSR areas for VMX transitions), and for the MSEG
3808 /// header. If software needs to access these data structures (e.g., to
3809 /// modify the contents of the MSR bitmaps), it can configure the paging
3810 /// structures to map them into the linear-address space. If it does so,
3811 /// it should establish mappings that use the memory type reported bits
3812 /// 53:50 in this MSR.
3814 /// As of this writing, all processors that support VMX operation indicate
3815 /// the write-back type.
3817 /// If software needs to access these data structures (e.g., to modify
3818 /// the contents of the MSR bitmaps), it can configure the paging
3819 /// structures to map them into the linear-address space. If it does so,
3820 /// it should establish mappings that use the memory type reported in this
3823 /// @note Alternatively, software may map any of these regions or
3824 /// structures with the UC memory type. (This may be necessary for the MSEG
3825 /// header.) Doing so is discouraged unless necessary as it will cause the
3826 /// performance of software accesses to those structures to suffer.
3829 UINT32 MemoryType
:4;
3831 /// [Bit 54] If bit 54 is read as 1, the processor reports information in
3832 /// the VM-exit instruction-information field on VM exitsdue to execution
3833 /// of the INS and OUTS instructions (see Section 27.2.4). This reporting
3834 /// is done only if this bit is read as 1.
3836 UINT32 InsOutsReporting
:1;
3838 /// [Bit 55] Bit 55 is read as 1 if any VMX controls that default to 1 may
3839 /// be cleared to 0. See Appendix A.2 for details. It also reports support
3840 /// for the VMX capability MSRs IA32_VMX_TRUE_PINBASED_CTLS,
3841 /// IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and
3842 /// IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3.1, Appendix A.3.2,
3843 /// Appendix A.4, and Appendix A.5 for details.
3845 UINT32 VmxControls
:1;
3849 /// All bit fields as a 64-bit value
3852 } MSR_IA32_VMX_BASIC_REGISTER
;
3855 /// @{ Define value for bit field MSR_IA32_VMX_BASIC_REGISTER.MemoryType
3857 #define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE 0x00
3858 #define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK 0x06
3865 Capability Reporting Register of Pinbased VM-execution Controls (R/O) See
3866 Appendix A.3.1, "Pin-Based VMExecution Controls.". If CPUID.01H:ECX.[5] = 1.
3868 @param ECX MSR_IA32_VMX_PINBASED_CTLS (0x00000481)
3869 @param EAX Lower 32-bits of MSR value.
3870 @param EDX Upper 32-bits of MSR value.
3872 <b>Example usage</b>
3876 Msr = AsmReadMsr64 (MSR_IA32_VMX_PINBASED_CTLS);
3878 @note MSR_IA32_VMX_PINBASED_CTLS is defined as IA32_VMX_PINBASED_CTLS in SDM.
3880 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
3884 Capability Reporting Register of Primary Processor-based VM-execution
3885 Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution
3886 Controls.". If CPUID.01H:ECX.[5] = 1.
3888 @param ECX MSR_IA32_VMX_PROCBASED_CTLS (0x00000482)
3889 @param EAX Lower 32-bits of MSR value.
3890 @param EDX Upper 32-bits of MSR value.
3892 <b>Example usage</b>
3896 Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS);
3898 @note MSR_IA32_VMX_PROCBASED_CTLS is defined as IA32_VMX_PROCBASED_CTLS in SDM.
3900 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
3904 Capability Reporting Register of VM-exit Controls (R/O) See Appendix A.4,
3905 "VM-Exit Controls.". If CPUID.01H:ECX.[5] = 1.
3907 @param ECX MSR_IA32_VMX_EXIT_CTLS (0x00000483)
3908 @param EAX Lower 32-bits of MSR value.
3909 @param EDX Upper 32-bits of MSR value.
3911 <b>Example usage</b>
3915 Msr = AsmReadMsr64 (MSR_IA32_VMX_EXIT_CTLS);
3917 @note MSR_IA32_VMX_EXIT_CTLS is defined as IA32_VMX_EXIT_CTLS in SDM.
3919 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
3923 Capability Reporting Register of VMentry Controls (R/O) See Appendix A.5,
3924 "VM-Entry Controls.". If CPUID.01H:ECX.[5] = 1.
3926 @param ECX MSR_IA32_VMX_ENTRY_CTLS (0x00000484)
3927 @param EAX Lower 32-bits of MSR value.
3928 @param EDX Upper 32-bits of MSR value.
3930 <b>Example usage</b>
3934 Msr = AsmReadMsr64 (MSR_IA32_VMX_ENTRY_CTLS);
3936 @note MSR_IA32_VMX_ENTRY_CTLS is defined as IA32_VMX_ENTRY_CTLS in SDM.
3938 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
3942 Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6,
3943 "Miscellaneous Data.". If CPUID.01H:ECX.[5] = 1.
3945 @param ECX MSR_IA32_VMX_MISC (0x00000485)
3946 @param EAX Lower 32-bits of MSR value.
3947 @param EDX Upper 32-bits of MSR value.
3949 <b>Example usage</b>
3951 IA32_VMX_MISC_REGISTER Msr;
3953 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_MISC);
3955 @note MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM.
3957 #define MSR_IA32_VMX_MISC 0x00000485
3960 MSR information returned for MSR index #IA32_VMX_MISC
3964 /// Individual bit fields
3968 /// [Bits 4:0] Reports a value X that specifies the relationship between the
3969 /// rate of the VMX-preemption timer and that of the timestamp counter (TSC).
3970 /// Specifically, the VMX-preemption timer (if it is active) counts down by
3971 /// 1 every time bit X in the TSC changes due to a TSC increment.
3973 UINT32 VmxTimerRatio
:5;
3975 /// [Bit 5] If bit 5 is read as 1, VM exits store the value of IA32_EFER.LMA
3976 /// into the "IA-32e mode guest" VM-entry control;see Section 27.2 for more
3977 /// details. This bit is read as 1 on any logical processor that supports
3978 /// the 1-setting of the "unrestricted guest" VM-execution control.
3980 UINT32 VmExitEferLma
:1;
3982 /// [Bit 6] reports (if set) the support for activity state 1 (HLT).
3984 UINT32 HltActivityStateSupported
:1;
3986 /// [Bit 7] reports (if set) the support for activity state 2 (shutdown).
3988 UINT32 ShutdownActivityStateSupported
:1;
3990 /// [Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI).
3992 UINT32 WaitForSipiActivityStateSupported
:1;
3995 /// [Bit 14] If read as 1, Intel(R) Processor Trace (Intel PT) can be used
3996 /// in VMX operation. If the processor supports Intel PT but does not allow
3997 /// it to be used in VMX operation, execution of VMXON clears
3998 /// IA32_RTIT_CTL.TraceEn (see \93VMXON\97Enter VMX Operation\94 in Chapter 30);
3999 /// any attempt to set that bit while in VMX operation (including VMX root
4000 /// operation) using the WRMSR instruction causes a general-protection
4003 UINT32 ProcessorTraceSupported
:1;
4005 /// [Bit 15] If read as 1, the RDMSR instruction can be used in system-
4006 /// management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH).
4007 /// See Section 34.15.6.3.
4009 UINT32 SmBaseMsrSupported
:1;
4011 /// [Bits 24:16] Indicate the number of CR3-target values supported by the
4012 /// processor. This number is a value between 0 and 256, inclusive (bit 24
4013 /// is set if and only if bits 23:16 are clear).
4015 UINT32 NumberOfCr3TargetValues
:9;
4017 /// [Bit 27:25] Bits 27:25 is used to compute the recommended maximum
4018 /// number of MSRs that should appear in the VM-exit MSR-store list, the
4019 /// VM-exit MSR-load list, or the VM-entry MSR-load list. Specifically, if
4020 /// the value bits 27:25 of IA32_VMX_MISC is N, then 512 * (N + 1) is the
4021 /// recommended maximum number of MSRs to be included in each list. If the
4022 /// limit is exceeded, undefined processor behavior may result (including a
4023 /// machine check during the VMX transition).
4025 UINT32 MsrStoreListMaximum
:3;
4027 /// [Bit 28] If read as 1, bit 2 of the IA32_SMM_MONITOR_CTL can be set
4028 /// to 1. VMXOFF unblocks SMIs unless IA32_SMM_MONITOR_CTL[bit 2] is 1
4029 /// (see Section 34.14.4).
4031 UINT32 BlockSmiSupported
:1;
4033 /// [Bit 29] read as 1, software can use VMWRITE to write to any supported
4034 /// field in the VMCS; otherwise, VMWRITE cannot be used to modify VM-exit
4035 /// information fields.
4037 UINT32 VmWriteSupported
:1;
4039 /// [Bit 30] If read as 1, VM entry allows injection of a software
4040 /// interrupt, software exception, or privileged software exception with an
4041 /// instruction length of 0.
4043 UINT32 VmInjectSupported
:1;
4046 /// [Bits 63:32] Reports the 32-bit MSEG revision identifier used by the
4049 UINT32 MsegRevisionIdentifier
:32;
4052 /// All bit fields as a 64-bit value
4055 } IA32_VMX_MISC_REGISTER
;
4059 Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7,
4060 "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.
4062 @param ECX MSR_IA32_VMX_CR0_FIXED0 (0x00000486)
4063 @param EAX Lower 32-bits of MSR value.
4064 @param EDX Upper 32-bits of MSR value.
4066 <b>Example usage</b>
4070 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED0);
4072 @note MSR_IA32_VMX_CR0_FIXED0 is defined as IA32_VMX_CR0_FIXED0 in SDM.
4074 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
4078 Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7,
4079 "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.
4081 @param ECX MSR_IA32_VMX_CR0_FIXED1 (0x00000487)
4082 @param EAX Lower 32-bits of MSR value.
4083 @param EDX Upper 32-bits of MSR value.
4085 <b>Example usage</b>
4089 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED1);
4091 @note MSR_IA32_VMX_CR0_FIXED1 is defined as IA32_VMX_CR0_FIXED1 in SDM.
4093 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
4097 Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8,
4098 "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.
4100 @param ECX MSR_IA32_VMX_CR4_FIXED0 (0x00000488)
4101 @param EAX Lower 32-bits of MSR value.
4102 @param EDX Upper 32-bits of MSR value.
4104 <b>Example usage</b>
4108 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED0);
4110 @note MSR_IA32_VMX_CR4_FIXED0 is defined as IA32_VMX_CR4_FIXED0 in SDM.
4112 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
4116 Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Appendix A.8,
4117 "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.
4119 @param ECX MSR_IA32_VMX_CR4_FIXED1 (0x00000489)
4120 @param EAX Lower 32-bits of MSR value.
4121 @param EDX Upper 32-bits of MSR value.
4123 <b>Example usage</b>
4127 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED1);
4129 @note MSR_IA32_VMX_CR4_FIXED1 is defined as IA32_VMX_CR4_FIXED1 in SDM.
4131 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
4135 Capability Reporting Register of VMCS Field Enumeration (R/O) See Appendix
4136 A.9, "VMCS Enumeration.". If CPUID.01H:ECX.[5] = 1.
4138 @param ECX MSR_IA32_VMX_VMCS_ENUM (0x0000048A)
4139 @param EAX Lower 32-bits of MSR value.
4140 @param EDX Upper 32-bits of MSR value.
4142 <b>Example usage</b>
4146 Msr = AsmReadMsr64 (MSR_IA32_VMX_VMCS_ENUM);
4148 @note MSR_IA32_VMX_VMCS_ENUM is defined as IA32_VMX_VMCS_ENUM in SDM.
4150 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048A
4154 Capability Reporting Register of Secondary Processor-based VM-execution
4155 Controls (R/O) See Appendix A.3.3, "Secondary Processor- Based VM-Execution
4156 Controls.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C TLS[63]).
4158 @param ECX MSR_IA32_VMX_PROCBASED_CTLS2 (0x0000048B)
4159 @param EAX Lower 32-bits of MSR value.
4160 @param EDX Upper 32-bits of MSR value.
4162 <b>Example usage</b>
4166 Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS2);
4168 @note MSR_IA32_VMX_PROCBASED_CTLS2 is defined as IA32_VMX_PROCBASED_CTLS2 in SDM.
4170 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B
4174 Capability Reporting Register of EPT and VPID (R/O) See Appendix A.10,
4175 "VPID and EPT Capabilities.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C
4176 TLS[63] && ( IA32_VMX_PROCBASED_C TLS2[33] IA32_VMX_PROCBASED_C TLS2[37]) ).
4178 @param ECX MSR_IA32_VMX_EPT_VPID_CAP (0x0000048C)
4179 @param EAX Lower 32-bits of MSR value.
4180 @param EDX Upper 32-bits of MSR value.
4182 <b>Example usage</b>
4186 Msr = AsmReadMsr64 (MSR_IA32_VMX_EPT_VPID_CAP);
4188 @note MSR_IA32_VMX_EPT_VPID_CAP is defined as IA32_VMX_EPT_VPID_CAP in SDM.
4190 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C
4194 Capability Reporting Register of Pinbased VM-execution Flex Controls (R/O)
4195 See Appendix A.3.1, "Pin-Based VMExecution Controls.". If (
4196 CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
4198 @param ECX MSR_IA32_VMX_TRUE_PINBASED_CTLS (0x0000048D)
4199 @param EAX Lower 32-bits of MSR value.
4200 @param EDX Upper 32-bits of MSR value.
4202 <b>Example usage</b>
4206 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PINBASED_CTLS);
4208 @note MSR_IA32_VMX_TRUE_PINBASED_CTLS is defined as IA32_VMX_TRUE_PINBASED_CTLS in SDM.
4210 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D
4214 Capability Reporting Register of Primary Processor-based VM-execution Flex
4215 Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution
4216 Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
4218 @param ECX MSR_IA32_VMX_TRUE_PROCBASED_CTLS (0x0000048E)
4219 @param EAX Lower 32-bits of MSR value.
4220 @param EDX Upper 32-bits of MSR value.
4222 <b>Example usage</b>
4226 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PROCBASED_CTLS);
4228 @note MSR_IA32_VMX_TRUE_PROCBASED_CTLS is defined as IA32_VMX_TRUE_PROCBASED_CTLS in SDM.
4230 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E
4234 Capability Reporting Register of VM-exit Flex Controls (R/O) See Appendix
4235 A.4, "VM-Exit Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
4237 @param ECX MSR_IA32_VMX_TRUE_EXIT_CTLS (0x0000048F)
4238 @param EAX Lower 32-bits of MSR value.
4239 @param EDX Upper 32-bits of MSR value.
4241 <b>Example usage</b>
4245 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_EXIT_CTLS);
4247 @note MSR_IA32_VMX_TRUE_EXIT_CTLS is defined as IA32_VMX_TRUE_EXIT_CTLS in SDM.
4249 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F
4253 Capability Reporting Register of VMentry Flex Controls (R/O) See Appendix
4254 A.5, "VM-Entry Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
4256 @param ECX MSR_IA32_VMX_TRUE_ENTRY_CTLS (0x00000490)
4257 @param EAX Lower 32-bits of MSR value.
4258 @param EDX Upper 32-bits of MSR value.
4260 <b>Example usage</b>
4264 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_ENTRY_CTLS);
4266 @note MSR_IA32_VMX_TRUE_ENTRY_CTLS is defined as IA32_VMX_TRUE_ENTRY_CTLS in SDM.
4268 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
4272 Capability Reporting Register of VMfunction Controls (R/O). If(
4273 CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
4275 @param ECX MSR_IA32_VMX_VMFUNC (0x00000491)
4276 @param EAX Lower 32-bits of MSR value.
4277 @param EDX Upper 32-bits of MSR value.
4279 <b>Example usage</b>
4283 Msr = AsmReadMsr64 (MSR_IA32_VMX_VMFUNC);
4285 @note MSR_IA32_VMX_VMFUNC is defined as IA32_VMX_VMFUNC in SDM.
4287 #define MSR_IA32_VMX_VMFUNC 0x00000491
4291 Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) &&
4292 IA32_PERF_CAPABILITIES[ 13] = 1.
4294 @param ECX MSR_IA32_A_PMCn
4295 @param EAX Lower 32-bits of MSR value.
4296 @param EDX Upper 32-bits of MSR value.
4298 <b>Example usage</b>
4302 Msr = AsmReadMsr64 (MSR_IA32_A_PMC0);
4303 AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr);
4305 @note MSR_IA32_A_PMC0 is defined as IA32_A_PMC0 in SDM.
4306 MSR_IA32_A_PMC1 is defined as IA32_A_PMC1 in SDM.
4307 MSR_IA32_A_PMC2 is defined as IA32_A_PMC2 in SDM.
4308 MSR_IA32_A_PMC3 is defined as IA32_A_PMC3 in SDM.
4309 MSR_IA32_A_PMC4 is defined as IA32_A_PMC4 in SDM.
4310 MSR_IA32_A_PMC5 is defined as IA32_A_PMC5 in SDM.
4311 MSR_IA32_A_PMC6 is defined as IA32_A_PMC6 in SDM.
4312 MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM.
4315 #define MSR_IA32_A_PMC0 0x000004C1
4316 #define MSR_IA32_A_PMC1 0x000004C2
4317 #define MSR_IA32_A_PMC2 0x000004C3
4318 #define MSR_IA32_A_PMC3 0x000004C4
4319 #define MSR_IA32_A_PMC4 0x000004C5
4320 #define MSR_IA32_A_PMC5 0x000004C6
4321 #define MSR_IA32_A_PMC6 0x000004C7
4322 #define MSR_IA32_A_PMC7 0x000004C8
4327 (R/W). If IA32_MCG_CAP.LMCE_P =1.
4329 @param ECX MSR_IA32_MCG_EXT_CTL (0x000004D0)
4330 @param EAX Lower 32-bits of MSR value.
4331 Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.
4332 @param EDX Upper 32-bits of MSR value.
4333 Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.
4335 <b>Example usage</b>
4337 MSR_IA32_MCG_EXT_CTL_REGISTER Msr;
4339 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL);
4340 AsmWriteMsr64 (MSR_IA32_MCG_EXT_CTL, Msr.Uint64);
4342 @note MSR_IA32_MCG_EXT_CTL is defined as IA32_MCG_EXT_CTL in SDM.
4344 #define MSR_IA32_MCG_EXT_CTL 0x000004D0
4347 MSR information returned for MSR index #MSR_IA32_MCG_EXT_CTL
4351 /// Individual bit fields
4355 /// [Bit 0] LMCE_EN.
4358 UINT32 Reserved1
:31;
4359 UINT32 Reserved2
:32;
4362 /// All bit fields as a 32-bit value
4366 /// All bit fields as a 64-bit value
4369 } MSR_IA32_MCG_EXT_CTL_REGISTER
;
4373 Status and SVN Threshold of SGX Support for ACM (RO). If CPUID.(EAX=07H,
4374 ECX=0H): EBX[2] = 1.
4376 @param ECX MSR_IA32_SGX_SVN_STATUS (0x00000500)
4377 @param EAX Lower 32-bits of MSR value.
4378 Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.
4379 @param EDX Upper 32-bits of MSR value.
4380 Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.
4382 <b>Example usage</b>
4384 MSR_IA32_SGX_SVN_STATUS_REGISTER Msr;
4386 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SGX_SVN_STATUS);
4388 @note MSR_IA32_SGX_SVN_STATUS is defined as IA32_SGX_SVN_STATUS in SDM.
4390 #define MSR_IA32_SGX_SVN_STATUS 0x00000500
4393 MSR information returned for MSR index #MSR_IA32_SGX_SVN_STATUS
4397 /// Individual bit fields
4401 /// [Bit 0] Lock. See Section 42.11.3, "Interactions with Authenticated
4402 /// Code Modules (ACMs)".
4405 UINT32 Reserved1
:15;
4407 /// [Bits 23:16] SGX_SVN_SINIT. See Section 42.11.3, "Interactions with
4408 /// Authenticated Code Modules (ACMs)".
4410 UINT32 SGX_SVN_SINIT
:8;
4412 UINT32 Reserved3
:32;
4415 /// All bit fields as a 32-bit value
4419 /// All bit fields as a 64-bit value
4422 } MSR_IA32_SGX_SVN_STATUS_REGISTER
;
4426 Trace Output Base Register (R/W). If ((CPUID.(EAX=07H, ECX=0):EBX[25] = 1)
4427 && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) (CPUID.(EAX=14H,ECX=0): ECX[2] = 1)
4430 @param ECX MSR_IA32_RTIT_OUTPUT_BASE (0x00000560)
4431 @param EAX Lower 32-bits of MSR value.
4432 Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.
4433 @param EDX Upper 32-bits of MSR value.
4434 Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.
4436 <b>Example usage</b>
4438 MSR_IA32_RTIT_OUTPUT_BASE_REGISTER Msr;
4440 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);
4441 AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_BASE, Msr.Uint64);
4443 @note MSR_IA32_RTIT_OUTPUT_BASE is defined as IA32_RTIT_OUTPUT_BASE in SDM.
4445 #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
4448 MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_BASE
4452 /// Individual bit fields
4457 /// [Bits 31:7] Base physical address.
4461 /// [Bits 63:32] Base physical address.
4466 /// All bit fields as a 64-bit value
4469 } MSR_IA32_RTIT_OUTPUT_BASE_REGISTER
;
4473 Trace Output Mask Pointers Register (R/W). If ((CPUID.(EAX=07H,
4474 ECX=0):EBX[25] = 1) && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1)
4475 (CPUID.(EAX=14H,ECX=0): ECX[2] = 1) ) ).
4477 @param ECX MSR_IA32_RTIT_OUTPUT_MASK_PTRS (0x00000561)
4478 @param EAX Lower 32-bits of MSR value.
4479 Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.
4480 @param EDX Upper 32-bits of MSR value.
4481 Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.
4483 <b>Example usage</b>
4485 MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER Msr;
4487 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS);
4488 AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS, Msr.Uint64);
4490 @note MSR_IA32_RTIT_OUTPUT_MASK_PTRS is defined as IA32_RTIT_OUTPUT_MASK_PTRS in SDM.
4492 #define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561
4495 MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_MASK_PTRS
4499 /// Individual bit fields
4504 /// [Bits 31:7] MaskOrTableOffset.
4506 UINT32 MaskOrTableOffset
:25;
4508 /// [Bits 63:32] Output Offset.
4510 UINT32 OutputOffset
:32;
4513 /// All bit fields as a 64-bit value
4516 } MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER
;
4520 Trace Control Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
4522 @param ECX MSR_IA32_RTIT_CTL (0x00000570)
4523 @param EAX Lower 32-bits of MSR value.
4524 Described by the type MSR_IA32_RTIT_CTL_REGISTER.
4525 @param EDX Upper 32-bits of MSR value.
4526 Described by the type MSR_IA32_RTIT_CTL_REGISTER.
4528 <b>Example usage</b>
4530 MSR_IA32_RTIT_CTL_REGISTER Msr;
4532 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
4533 AsmWriteMsr64 (MSR_IA32_RTIT_CTL, Msr.Uint64);
4535 @note MSR_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.
4537 #define MSR_IA32_RTIT_CTL 0x00000570
4540 MSR information returned for MSR index #MSR_IA32_RTIT_CTL
4544 /// Individual bit fields
4548 /// [Bit 0] TraceEn.
4552 /// [Bit 1] CYCEn. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
4565 /// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1).
4569 /// [Bit 7] CR3 filter.
4577 /// [Bit 9] MTCEn. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).
4585 /// [Bit 11] DisRETC.
4590 /// [Bit 13] BranchEn.
4594 /// [Bits 17:14] MTCFreq. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).
4599 /// [Bits 22:19] CYCThresh. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
4604 /// [Bits 27:24] PSBFreq. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
4609 /// [Bits 35:32] ADDR0_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0).
4613 /// [Bits 39:36] ADDR1_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 1).
4617 /// [Bits 43:40] ADDR2_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 2).
4621 /// [Bits 47:44] ADDR3_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3).
4624 UINT32 Reserved6
:16;
4627 /// All bit fields as a 64-bit value
4630 } MSR_IA32_RTIT_CTL_REGISTER
;
4634 Tracing Status Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
4636 @param ECX MSR_IA32_RTIT_STATUS (0x00000571)
4637 @param EAX Lower 32-bits of MSR value.
4638 Described by the type MSR_IA32_RTIT_STATUS_REGISTER.
4639 @param EDX Upper 32-bits of MSR value.
4640 Described by the type MSR_IA32_RTIT_STATUS_REGISTER.
4642 <b>Example usage</b>
4644 MSR_IA32_RTIT_STATUS_REGISTER Msr;
4646 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_STATUS);
4647 AsmWriteMsr64 (MSR_IA32_RTIT_STATUS, Msr.Uint64);
4649 @note MSR_IA32_RTIT_STATUS is defined as IA32_RTIT_STATUS in SDM.
4651 #define MSR_IA32_RTIT_STATUS 0x00000571
4654 MSR information returned for MSR index #MSR_IA32_RTIT_STATUS
4658 /// Individual bit fields
4662 /// [Bit 0] FilterEn, (writes ignored).
4663 /// If (CPUID.(EAX=07H, ECX=0):EBX[2] = 1).
4667 /// [Bit 1] ContexEn, (writes ignored).
4671 /// [Bit 2] TriggerEn, (writes ignored).
4680 /// [Bit 5] Stopped.
4683 UINT32 Reserved2
:26;
4685 /// [Bits 48:32] PacketByteCnt. If (CPUID.(EAX=07H, ECX=0):EBX[1] > 3).
4687 UINT32 PacketByteCnt
:17;
4688 UINT32 Reserved3
:15;
4691 /// All bit fields as a 64-bit value
4694 } MSR_IA32_RTIT_STATUS_REGISTER
;
4698 Trace Filter CR3 Match Register (R/W).
4699 If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
4701 @param ECX MSR_IA32_RTIT_CR3_MATCH (0x00000572)
4702 @param EAX Lower 32-bits of MSR value.
4703 Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.
4704 @param EDX Upper 32-bits of MSR value.
4705 Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.
4707 <b>Example usage</b>
4709 MSR_IA32_RTIT_CR3_MATCH_REGISTER Msr;
4711 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CR3_MATCH);
4712 AsmWriteMsr64 (MSR_IA32_RTIT_CR3_MATCH, Msr.Uint64);
4714 @note MSR_IA32_RTIT_CR3_MATCH is defined as IA32_RTIT_CR3_MATCH in SDM.
4716 #define MSR_IA32_RTIT_CR3_MATCH 0x00000572
4719 MSR information returned for MSR index #MSR_IA32_RTIT_CR3_MATCH
4723 /// Individual bit fields
4728 /// [Bits 31:5] CR3[63:5] value to match.
4732 /// [Bits 63:32] CR3[63:5] value to match.
4737 /// All bit fields as a 64-bit value
4740 } MSR_IA32_RTIT_CR3_MATCH_REGISTER
;
4744 Region n Start Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).
4746 @param ECX MSR_IA32_RTIT_ADDRn_A
4747 @param EAX Lower 32-bits of MSR value.
4748 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
4749 @param EDX Upper 32-bits of MSR value.
4750 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
4752 <b>Example usage</b>
4754 MSR_IA32_RTIT_ADDR_REGISTER Msr;
4756 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_A);
4757 AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_A, Msr.Uint64);
4759 @note MSR_IA32_RTIT_ADDR0_A is defined as IA32_RTIT_ADDR0_A in SDM.
4760 MSR_IA32_RTIT_ADDR1_A is defined as IA32_RTIT_ADDR1_A in SDM.
4761 MSR_IA32_RTIT_ADDR2_A is defined as IA32_RTIT_ADDR2_A in SDM.
4762 MSR_IA32_RTIT_ADDR3_A is defined as IA32_RTIT_ADDR3_A in SDM.
4765 #define MSR_IA32_RTIT_ADDR0_A 0x00000580
4766 #define MSR_IA32_RTIT_ADDR1_A 0x00000582
4767 #define MSR_IA32_RTIT_ADDR2_A 0x00000584
4768 #define MSR_IA32_RTIT_ADDR3_A 0x00000586
4773 Region n End Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).
4775 @param ECX MSR_IA32_RTIT_ADDRn_B
4776 @param EAX Lower 32-bits of MSR value.
4777 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
4778 @param EDX Upper 32-bits of MSR value.
4779 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
4781 <b>Example usage</b>
4783 MSR_IA32_RTIT_ADDR_REGISTER Msr;
4785 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_B);
4786 AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_B, Msr.Uint64);
4788 @note MSR_IA32_RTIT_ADDR0_B is defined as IA32_RTIT_ADDR0_B in SDM.
4789 MSR_IA32_RTIT_ADDR1_B is defined as IA32_RTIT_ADDR1_B in SDM.
4790 MSR_IA32_RTIT_ADDR2_B is defined as IA32_RTIT_ADDR2_B in SDM.
4791 MSR_IA32_RTIT_ADDR3_B is defined as IA32_RTIT_ADDR3_B in SDM.
4794 #define MSR_IA32_RTIT_ADDR0_B 0x00000581
4795 #define MSR_IA32_RTIT_ADDR1_B 0x00000583
4796 #define MSR_IA32_RTIT_ADDR2_B 0x00000585
4797 #define MSR_IA32_RTIT_ADDR3_B 0x00000587
4802 MSR information returned for MSR indexes
4803 #MSR_IA32_RTIT_ADDR0_A to #MSR_IA32_RTIT_ADDR3_A and
4804 #MSR_IA32_RTIT_ADDR0_B to #MSR_IA32_RTIT_ADDR3_B
4808 /// Individual bit fields
4812 /// [Bits 31:0] Virtual Address.
4814 UINT32 VirtualAddress
:32;
4816 /// [Bits 47:32] Virtual Address.
4818 UINT32 VirtualAddressHi
:16;
4820 /// [Bits 63:48] SignExt_VA.
4822 UINT32 SignExt_VA
:16;
4825 /// All bit fields as a 64-bit value
4828 } MSR_IA32_RTIT_ADDR_REGISTER
;
4832 DS Save Area (R/W) Points to the linear address of the first byte of the DS
4833 buffer management area, which is used to manage the BTS and PEBS buffers.
4834 See Section 18.15.4, "Debug Store (DS) Mechanism.". If( CPUID.01H:EDX.DS[21]
4837 [Bits 31..0] The linear address of the first byte of the DS buffer
4838 management area, if not in IA-32e mode.
4840 [Bits 63..0] The linear address of the first byte of the DS buffer
4841 management area, if IA-32e mode is active.
4843 @param ECX MSR_IA32_DS_AREA (0x00000600)
4844 @param EAX Lower 32-bits of MSR value.
4845 Described by the type MSR_IA32_DS_AREA_REGISTER.
4846 @param EDX Upper 32-bits of MSR value.
4847 Described by the type MSR_IA32_DS_AREA_REGISTER.
4849 <b>Example usage</b>
4853 Msr = AsmReadMsr64 (MSR_IA32_DS_AREA);
4854 AsmWriteMsr64 (MSR_IA32_DS_AREA, Msr);
4856 @note MSR_IA32_DS_AREA is defined as IA32_DS_AREA in SDM.
4858 #define MSR_IA32_DS_AREA 0x00000600
4862 TSC Target of Local APIC's TSC Deadline Mode (R/W). If CPUID.01H:ECX.[24] =
4865 @param ECX MSR_IA32_TSC_DEADLINE (0x000006E0)
4866 @param EAX Lower 32-bits of MSR value.
4867 @param EDX Upper 32-bits of MSR value.
4869 <b>Example usage</b>
4873 Msr = AsmReadMsr64 (MSR_IA32_TSC_DEADLINE);
4874 AsmWriteMsr64 (MSR_IA32_TSC_DEADLINE, Msr);
4876 @note MSR_IA32_TSC_DEADLINE is defined as IA32_TSC_DEADLINE in SDM.
4878 #define MSR_IA32_TSC_DEADLINE 0x000006E0
4882 Enable/disable HWP (R/W). If CPUID.06H:EAX.[7] = 1.
4884 @param ECX MSR_IA32_PM_ENABLE (0x00000770)
4885 @param EAX Lower 32-bits of MSR value.
4886 Described by the type MSR_IA32_PM_ENABLE_REGISTER.
4887 @param EDX Upper 32-bits of MSR value.
4888 Described by the type MSR_IA32_PM_ENABLE_REGISTER.
4890 <b>Example usage</b>
4892 MSR_IA32_PM_ENABLE_REGISTER Msr;
4894 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_ENABLE);
4895 AsmWriteMsr64 (MSR_IA32_PM_ENABLE, Msr.Uint64);
4897 @note MSR_IA32_PM_ENABLE is defined as IA32_PM_ENABLE in SDM.
4899 #define MSR_IA32_PM_ENABLE 0x00000770
4902 MSR information returned for MSR index #MSR_IA32_PM_ENABLE
4906 /// Individual bit fields
4910 /// [Bit 0] HWP_ENABLE (R/W1-Once). See Section 14.4.2, "Enabling HWP". If
4911 /// CPUID.06H:EAX.[7] = 1.
4913 UINT32 HWP_ENABLE
:1;
4914 UINT32 Reserved1
:31;
4915 UINT32 Reserved2
:32;
4918 /// All bit fields as a 32-bit value
4922 /// All bit fields as a 64-bit value
4925 } MSR_IA32_PM_ENABLE_REGISTER
;
4929 HWP Performance Range Enumeration (RO). If CPUID.06H:EAX.[7] = 1.
4931 @param ECX MSR_IA32_HWP_CAPABILITIES (0x00000771)
4932 @param EAX Lower 32-bits of MSR value.
4933 Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.
4934 @param EDX Upper 32-bits of MSR value.
4935 Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.
4937 <b>Example usage</b>
4939 MSR_IA32_HWP_CAPABILITIES_REGISTER Msr;
4941 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_CAPABILITIES);
4943 @note MSR_IA32_HWP_CAPABILITIES is defined as IA32_HWP_CAPABILITIES in SDM.
4945 #define MSR_IA32_HWP_CAPABILITIES 0x00000771
4948 MSR information returned for MSR index #MSR_IA32_HWP_CAPABILITIES
4952 /// Individual bit fields
4956 /// [Bits 7:0] Highest_Performance See Section 14.4.3, "HWP Performance
4957 /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
4959 UINT32 Highest_Performance
:8;
4961 /// [Bits 15:8] Guaranteed_Performance See Section 14.4.3, "HWP
4962 /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
4964 UINT32 Guaranteed_Performance
:8;
4966 /// [Bits 23:16] Most_Efficient_Performance See Section 14.4.3, "HWP
4967 /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
4969 UINT32 Most_Efficient_Performance
:8;
4971 /// [Bits 31:24] Lowest_Performance See Section 14.4.3, "HWP Performance
4972 /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
4974 UINT32 Lowest_Performance
:8;
4978 /// All bit fields as a 32-bit value
4982 /// All bit fields as a 64-bit value
4985 } MSR_IA32_HWP_CAPABILITIES_REGISTER
;
4989 Power Management Control Hints for All Logical Processors in a Package
4990 (R/W). If CPUID.06H:EAX.[11] = 1.
4992 @param ECX MSR_IA32_HWP_REQUEST_PKG (0x00000772)
4993 @param EAX Lower 32-bits of MSR value.
4994 Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.
4995 @param EDX Upper 32-bits of MSR value.
4996 Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.
4998 <b>Example usage</b>
5000 MSR_IA32_HWP_REQUEST_PKG_REGISTER Msr;
5002 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST_PKG);
5003 AsmWriteMsr64 (MSR_IA32_HWP_REQUEST_PKG, Msr.Uint64);
5005 @note MSR_IA32_HWP_REQUEST_PKG is defined as IA32_HWP_REQUEST_PKG in SDM.
5007 #define MSR_IA32_HWP_REQUEST_PKG 0x00000772
5010 MSR information returned for MSR index #MSR_IA32_HWP_REQUEST_PKG
5014 /// Individual bit fields
5018 /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If
5019 /// CPUID.06H:EAX.[11] = 1.
5021 UINT32 Minimum_Performance
:8;
5023 /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If
5024 /// CPUID.06H:EAX.[11] = 1.
5026 UINT32 Maximum_Performance
:8;
5028 /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".
5029 /// If CPUID.06H:EAX.[11] = 1.
5031 UINT32 Desired_Performance
:8;
5033 /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,
5034 /// "Managing HWP". If CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[10] = 1.
5036 UINT32 Energy_Performance_Preference
:8;
5038 /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If
5039 /// CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[9] = 1.
5041 UINT32 Activity_Window
:10;
5045 /// All bit fields as a 64-bit value
5048 } MSR_IA32_HWP_REQUEST_PKG_REGISTER
;
5052 Control HWP Native Interrupts (R/W). If CPUID.06H:EAX.[8] = 1.
5054 @param ECX MSR_IA32_HWP_INTERRUPT (0x00000773)
5055 @param EAX Lower 32-bits of MSR value.
5056 Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.
5057 @param EDX Upper 32-bits of MSR value.
5058 Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.
5060 <b>Example usage</b>
5062 MSR_IA32_HWP_INTERRUPT_REGISTER Msr;
5064 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_INTERRUPT);
5065 AsmWriteMsr64 (MSR_IA32_HWP_INTERRUPT, Msr.Uint64);
5067 @note MSR_IA32_HWP_INTERRUPT is defined as IA32_HWP_INTERRUPT in SDM.
5069 #define MSR_IA32_HWP_INTERRUPT 0x00000773
5072 MSR information returned for MSR index #MSR_IA32_HWP_INTERRUPT
5076 /// Individual bit fields
5080 /// [Bit 0] EN_Guaranteed_Performance_Change. See Section 14.4.6, "HWP
5081 /// Notifications". If CPUID.06H:EAX.[8] = 1.
5083 UINT32 EN_Guaranteed_Performance_Change
:1;
5085 /// [Bit 1] EN_Excursion_Minimum. See Section 14.4.6, "HWP Notifications".
5086 /// If CPUID.06H:EAX.[8] = 1.
5088 UINT32 EN_Excursion_Minimum
:1;
5089 UINT32 Reserved1
:30;
5090 UINT32 Reserved2
:32;
5093 /// All bit fields as a 32-bit value
5097 /// All bit fields as a 64-bit value
5100 } MSR_IA32_HWP_INTERRUPT_REGISTER
;
5104 Power Management Control Hints to a Logical Processor (R/W). If
5105 CPUID.06H:EAX.[7] = 1.
5107 @param ECX MSR_IA32_HWP_REQUEST (0x00000774)
5108 @param EAX Lower 32-bits of MSR value.
5109 Described by the type MSR_IA32_HWP_REQUEST_REGISTER.
5110 @param EDX Upper 32-bits of MSR value.
5111 Described by the type MSR_IA32_HWP_REQUEST_REGISTER.
5113 <b>Example usage</b>
5115 MSR_IA32_HWP_REQUEST_REGISTER Msr;
5117 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST);
5118 AsmWriteMsr64 (MSR_IA32_HWP_REQUEST, Msr.Uint64);
5120 @note MSR_IA32_HWP_REQUEST is defined as IA32_HWP_REQUEST in SDM.
5122 #define MSR_IA32_HWP_REQUEST 0x00000774
5125 MSR information returned for MSR index #MSR_IA32_HWP_REQUEST
5129 /// Individual bit fields
5133 /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If
5134 /// CPUID.06H:EAX.[7] = 1.
5136 UINT32 Minimum_Performance
:8;
5138 /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If
5139 /// CPUID.06H:EAX.[7] = 1.
5141 UINT32 Maximum_Performance
:8;
5143 /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".
5144 /// If CPUID.06H:EAX.[7] = 1.
5146 UINT32 Desired_Performance
:8;
5148 /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,
5149 /// "Managing HWP". If CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[10] = 1.
5151 UINT32 Energy_Performance_Preference
:8;
5153 /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If
5154 /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[9] = 1.
5156 UINT32 Activity_Window
:10;
5158 /// [Bit 42] Package_Control See Section 14.4.4, "Managing HWP". If
5159 /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[11] = 1.
5161 UINT32 Package_Control
:1;
5165 /// All bit fields as a 64-bit value
5168 } MSR_IA32_HWP_REQUEST_REGISTER
;
5172 Log bits indicating changes to Guaranteed & excursions to Minimum (R/W). If
5173 CPUID.06H:EAX.[7] = 1.
5175 @param ECX MSR_IA32_HWP_STATUS (0x00000777)
5176 @param EAX Lower 32-bits of MSR value.
5177 Described by the type MSR_IA32_HWP_STATUS_REGISTER.
5178 @param EDX Upper 32-bits of MSR value.
5179 Described by the type MSR_IA32_HWP_STATUS_REGISTER.
5181 <b>Example usage</b>
5183 MSR_IA32_HWP_STATUS_REGISTER Msr;
5185 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_STATUS);
5186 AsmWriteMsr64 (MSR_IA32_HWP_STATUS, Msr.Uint64);
5188 @note MSR_IA32_HWP_STATUS is defined as IA32_HWP_STATUS in SDM.
5190 #define MSR_IA32_HWP_STATUS 0x00000777
5193 MSR information returned for MSR index #MSR_IA32_HWP_STATUS
5197 /// Individual bit fields
5201 /// [Bit 0] Guaranteed_Performance_Change (R/WC0). See Section 14.4.5,
5202 /// "HWP Feedback". If CPUID.06H:EAX.[7] = 1.
5204 UINT32 Guaranteed_Performance_Change
:1;
5207 /// [Bit 2] Excursion_To_Minimum (R/WC0). See Section 14.4.5, "HWP
5208 /// Feedback". If CPUID.06H:EAX.[7] = 1.
5210 UINT32 Excursion_To_Minimum
:1;
5211 UINT32 Reserved2
:29;
5212 UINT32 Reserved3
:32;
5215 /// All bit fields as a 32-bit value
5219 /// All bit fields as a 64-bit value
5222 } MSR_IA32_HWP_STATUS_REGISTER
;
5226 x2APIC ID Register (R/O) See x2APIC Specification. If CPUID.01H:ECX[21] = 1
5227 && IA32_APIC_BASE.[10] = 1.
5229 @param ECX MSR_IA32_X2APIC_APICID (0x00000802)
5230 @param EAX Lower 32-bits of MSR value.
5231 @param EDX Upper 32-bits of MSR value.
5233 <b>Example usage</b>
5237 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_APICID);
5239 @note MSR_IA32_X2APIC_APICID is defined as IA32_X2APIC_APICID in SDM.
5241 #define MSR_IA32_X2APIC_APICID 0x00000802
5245 x2APIC Version Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
5246 IA32_APIC_BASE.[10] = 1.
5248 @param ECX MSR_IA32_X2APIC_VERSION (0x00000803)
5249 @param EAX Lower 32-bits of MSR value.
5250 @param EDX Upper 32-bits of MSR value.
5252 <b>Example usage</b>
5256 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_VERSION);
5258 @note MSR_IA32_X2APIC_VERSION is defined as IA32_X2APIC_VERSION in SDM.
5260 #define MSR_IA32_X2APIC_VERSION 0x00000803
5264 x2APIC Task Priority Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5265 IA32_APIC_BASE.[10] = 1.
5267 @param ECX MSR_IA32_X2APIC_TPR (0x00000808)
5268 @param EAX Lower 32-bits of MSR value.
5269 @param EDX Upper 32-bits of MSR value.
5271 <b>Example usage</b>
5275 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TPR);
5276 AsmWriteMsr64 (MSR_IA32_X2APIC_TPR, Msr);
5278 @note MSR_IA32_X2APIC_TPR is defined as IA32_X2APIC_TPR in SDM.
5280 #define MSR_IA32_X2APIC_TPR 0x00000808
5284 x2APIC Processor Priority Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
5285 IA32_APIC_BASE.[10] = 1.
5287 @param ECX MSR_IA32_X2APIC_PPR (0x0000080A)
5288 @param EAX Lower 32-bits of MSR value.
5289 @param EDX Upper 32-bits of MSR value.
5291 <b>Example usage</b>
5295 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_PPR);
5297 @note MSR_IA32_X2APIC_PPR is defined as IA32_X2APIC_PPR in SDM.
5299 #define MSR_IA32_X2APIC_PPR 0x0000080A
5303 x2APIC EOI Register (W/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10]
5306 @param ECX MSR_IA32_X2APIC_EOI (0x0000080B)
5307 @param EAX Lower 32-bits of MSR value.
5308 @param EDX Upper 32-bits of MSR value.
5310 <b>Example usage</b>
5315 AsmWriteMsr64 (MSR_IA32_X2APIC_EOI, Msr);
5317 @note MSR_IA32_X2APIC_EOI is defined as IA32_X2APIC_EOI in SDM.
5319 #define MSR_IA32_X2APIC_EOI 0x0000080B
5323 x2APIC Logical Destination Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
5324 IA32_APIC_BASE.[10] = 1.
5326 @param ECX MSR_IA32_X2APIC_LDR (0x0000080D)
5327 @param EAX Lower 32-bits of MSR value.
5328 @param EDX Upper 32-bits of MSR value.
5330 <b>Example usage</b>
5334 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LDR);
5336 @note MSR_IA32_X2APIC_LDR is defined as IA32_X2APIC_LDR in SDM.
5338 #define MSR_IA32_X2APIC_LDR 0x0000080D
5342 x2APIC Spurious Interrupt Vector Register (R/W). If CPUID.01H:ECX.[21] = 1
5343 && IA32_APIC_BASE.[10] = 1.
5345 @param ECX MSR_IA32_X2APIC_SIVR (0x0000080F)
5346 @param EAX Lower 32-bits of MSR value.
5347 @param EDX Upper 32-bits of MSR value.
5349 <b>Example usage</b>
5353 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_SIVR);
5354 AsmWriteMsr64 (MSR_IA32_X2APIC_SIVR, Msr);
5356 @note MSR_IA32_X2APIC_SIVR is defined as IA32_X2APIC_SIVR in SDM.
5358 #define MSR_IA32_X2APIC_SIVR 0x0000080F
5362 x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O).
5363 If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
5365 @param ECX MSR_IA32_X2APIC_ISRn
5366 @param EAX Lower 32-bits of MSR value.
5367 @param EDX Upper 32-bits of MSR value.
5369 <b>Example usage</b>
5373 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0);
5375 @note MSR_IA32_X2APIC_ISR0 is defined as IA32_X2APIC_ISR0 in SDM.
5376 MSR_IA32_X2APIC_ISR1 is defined as IA32_X2APIC_ISR1 in SDM.
5377 MSR_IA32_X2APIC_ISR2 is defined as IA32_X2APIC_ISR2 in SDM.
5378 MSR_IA32_X2APIC_ISR3 is defined as IA32_X2APIC_ISR3 in SDM.
5379 MSR_IA32_X2APIC_ISR4 is defined as IA32_X2APIC_ISR4 in SDM.
5380 MSR_IA32_X2APIC_ISR5 is defined as IA32_X2APIC_ISR5 in SDM.
5381 MSR_IA32_X2APIC_ISR6 is defined as IA32_X2APIC_ISR6 in SDM.
5382 MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM.
5385 #define MSR_IA32_X2APIC_ISR0 0x00000810
5386 #define MSR_IA32_X2APIC_ISR1 0x00000811
5387 #define MSR_IA32_X2APIC_ISR2 0x00000812
5388 #define MSR_IA32_X2APIC_ISR3 0x00000813
5389 #define MSR_IA32_X2APIC_ISR4 0x00000814
5390 #define MSR_IA32_X2APIC_ISR5 0x00000815
5391 #define MSR_IA32_X2APIC_ISR6 0x00000816
5392 #define MSR_IA32_X2APIC_ISR7 0x00000817
5397 x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O).
5398 If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
5400 @param ECX MSR_IA32_X2APIC_TMRn
5401 @param EAX Lower 32-bits of MSR value.
5402 @param EDX Upper 32-bits of MSR value.
5404 <b>Example usage</b>
5408 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0);
5410 @note MSR_IA32_X2APIC_TMR0 is defined as IA32_X2APIC_TMR0 in SDM.
5411 MSR_IA32_X2APIC_TMR1 is defined as IA32_X2APIC_TMR1 in SDM.
5412 MSR_IA32_X2APIC_TMR2 is defined as IA32_X2APIC_TMR2 in SDM.
5413 MSR_IA32_X2APIC_TMR3 is defined as IA32_X2APIC_TMR3 in SDM.
5414 MSR_IA32_X2APIC_TMR4 is defined as IA32_X2APIC_TMR4 in SDM.
5415 MSR_IA32_X2APIC_TMR5 is defined as IA32_X2APIC_TMR5 in SDM.
5416 MSR_IA32_X2APIC_TMR6 is defined as IA32_X2APIC_TMR6 in SDM.
5417 MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM.
5420 #define MSR_IA32_X2APIC_TMR0 0x00000818
5421 #define MSR_IA32_X2APIC_TMR1 0x00000819
5422 #define MSR_IA32_X2APIC_TMR2 0x0000081A
5423 #define MSR_IA32_X2APIC_TMR3 0x0000081B
5424 #define MSR_IA32_X2APIC_TMR4 0x0000081C
5425 #define MSR_IA32_X2APIC_TMR5 0x0000081D
5426 #define MSR_IA32_X2APIC_TMR6 0x0000081E
5427 #define MSR_IA32_X2APIC_TMR7 0x0000081F
5432 x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O).
5433 If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
5435 @param ECX MSR_IA32_X2APIC_IRRn
5436 @param EAX Lower 32-bits of MSR value.
5437 @param EDX Upper 32-bits of MSR value.
5439 <b>Example usage</b>
5443 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0);
5445 @note MSR_IA32_X2APIC_IRR0 is defined as IA32_X2APIC_IRR0 in SDM.
5446 MSR_IA32_X2APIC_IRR1 is defined as IA32_X2APIC_IRR1 in SDM.
5447 MSR_IA32_X2APIC_IRR2 is defined as IA32_X2APIC_IRR2 in SDM.
5448 MSR_IA32_X2APIC_IRR3 is defined as IA32_X2APIC_IRR3 in SDM.
5449 MSR_IA32_X2APIC_IRR4 is defined as IA32_X2APIC_IRR4 in SDM.
5450 MSR_IA32_X2APIC_IRR5 is defined as IA32_X2APIC_IRR5 in SDM.
5451 MSR_IA32_X2APIC_IRR6 is defined as IA32_X2APIC_IRR6 in SDM.
5452 MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM.
5455 #define MSR_IA32_X2APIC_IRR0 0x00000820
5456 #define MSR_IA32_X2APIC_IRR1 0x00000821
5457 #define MSR_IA32_X2APIC_IRR2 0x00000822
5458 #define MSR_IA32_X2APIC_IRR3 0x00000823
5459 #define MSR_IA32_X2APIC_IRR4 0x00000824
5460 #define MSR_IA32_X2APIC_IRR5 0x00000825
5461 #define MSR_IA32_X2APIC_IRR6 0x00000826
5462 #define MSR_IA32_X2APIC_IRR7 0x00000827
5467 x2APIC Error Status Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5468 IA32_APIC_BASE.[10] = 1.
5470 @param ECX MSR_IA32_X2APIC_ESR (0x00000828)
5471 @param EAX Lower 32-bits of MSR value.
5472 @param EDX Upper 32-bits of MSR value.
5474 <b>Example usage</b>
5478 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ESR);
5479 AsmWriteMsr64 (MSR_IA32_X2APIC_ESR, Msr);
5481 @note MSR_IA32_X2APIC_ESR is defined as IA32_X2APIC_ESR in SDM.
5483 #define MSR_IA32_X2APIC_ESR 0x00000828
5487 x2APIC LVT Corrected Machine Check Interrupt Register (R/W). If
5488 CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
5490 @param ECX MSR_IA32_X2APIC_LVT_CMCI (0x0000082F)
5491 @param EAX Lower 32-bits of MSR value.
5492 @param EDX Upper 32-bits of MSR value.
5494 <b>Example usage</b>
5498 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_CMCI);
5499 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_CMCI, Msr);
5501 @note MSR_IA32_X2APIC_LVT_CMCI is defined as IA32_X2APIC_LVT_CMCI in SDM.
5503 #define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F
5507 x2APIC Interrupt Command Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5508 IA32_APIC_BASE.[10] = 1.
5510 @param ECX MSR_IA32_X2APIC_ICR (0x00000830)
5511 @param EAX Lower 32-bits of MSR value.
5512 @param EDX Upper 32-bits of MSR value.
5514 <b>Example usage</b>
5518 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ICR);
5519 AsmWriteMsr64 (MSR_IA32_X2APIC_ICR, Msr);
5521 @note MSR_IA32_X2APIC_ICR is defined as IA32_X2APIC_ICR in SDM.
5523 #define MSR_IA32_X2APIC_ICR 0x00000830
5527 x2APIC LVT Timer Interrupt Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5528 IA32_APIC_BASE.[10] = 1.
5530 @param ECX MSR_IA32_X2APIC_LVT_TIMER (0x00000832)
5531 @param EAX Lower 32-bits of MSR value.
5532 @param EDX Upper 32-bits of MSR value.
5534 <b>Example usage</b>
5538 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_TIMER);
5539 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_TIMER, Msr);
5541 @note MSR_IA32_X2APIC_LVT_TIMER is defined as IA32_X2APIC_LVT_TIMER in SDM.
5543 #define MSR_IA32_X2APIC_LVT_TIMER 0x00000832
5547 x2APIC LVT Thermal Sensor Interrupt Register (R/W). If CPUID.01H:ECX.[21] =
5548 1 && IA32_APIC_BASE.[10] = 1.
5550 @param ECX MSR_IA32_X2APIC_LVT_THERMAL (0x00000833)
5551 @param EAX Lower 32-bits of MSR value.
5552 @param EDX Upper 32-bits of MSR value.
5554 <b>Example usage</b>
5558 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_THERMAL);
5559 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_THERMAL, Msr);
5561 @note MSR_IA32_X2APIC_LVT_THERMAL is defined as IA32_X2APIC_LVT_THERMAL in SDM.
5563 #define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833
5567 x2APIC LVT Performance Monitor Interrupt Register (R/W). If
5568 CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
5570 @param ECX MSR_IA32_X2APIC_LVT_PMI (0x00000834)
5571 @param EAX Lower 32-bits of MSR value.
5572 @param EDX Upper 32-bits of MSR value.
5574 <b>Example usage</b>
5578 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_PMI);
5579 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_PMI, Msr);
5581 @note MSR_IA32_X2APIC_LVT_PMI is defined as IA32_X2APIC_LVT_PMI in SDM.
5583 #define MSR_IA32_X2APIC_LVT_PMI 0x00000834
5587 x2APIC LVT LINT0 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5588 IA32_APIC_BASE.[10] = 1.
5590 @param ECX MSR_IA32_X2APIC_LVT_LINT0 (0x00000835)
5591 @param EAX Lower 32-bits of MSR value.
5592 @param EDX Upper 32-bits of MSR value.
5594 <b>Example usage</b>
5598 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT0);
5599 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT0, Msr);
5601 @note MSR_IA32_X2APIC_LVT_LINT0 is defined as IA32_X2APIC_LVT_LINT0 in SDM.
5603 #define MSR_IA32_X2APIC_LVT_LINT0 0x00000835
5607 x2APIC LVT LINT1 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5608 IA32_APIC_BASE.[10] = 1.
5610 @param ECX MSR_IA32_X2APIC_LVT_LINT1 (0x00000836)
5611 @param EAX Lower 32-bits of MSR value.
5612 @param EDX Upper 32-bits of MSR value.
5614 <b>Example usage</b>
5618 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT1);
5619 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT1, Msr);
5621 @note MSR_IA32_X2APIC_LVT_LINT1 is defined as IA32_X2APIC_LVT_LINT1 in SDM.
5623 #define MSR_IA32_X2APIC_LVT_LINT1 0x00000836
5627 x2APIC LVT Error Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5628 IA32_APIC_BASE.[10] = 1.
5630 @param ECX MSR_IA32_X2APIC_LVT_ERROR (0x00000837)
5631 @param EAX Lower 32-bits of MSR value.
5632 @param EDX Upper 32-bits of MSR value.
5634 <b>Example usage</b>
5638 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_ERROR);
5639 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_ERROR, Msr);
5641 @note MSR_IA32_X2APIC_LVT_ERROR is defined as IA32_X2APIC_LVT_ERROR in SDM.
5643 #define MSR_IA32_X2APIC_LVT_ERROR 0x00000837
5647 x2APIC Initial Count Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5648 IA32_APIC_BASE.[10] = 1.
5650 @param ECX MSR_IA32_X2APIC_INIT_COUNT (0x00000838)
5651 @param EAX Lower 32-bits of MSR value.
5652 @param EDX Upper 32-bits of MSR value.
5654 <b>Example usage</b>
5658 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_INIT_COUNT);
5659 AsmWriteMsr64 (MSR_IA32_X2APIC_INIT_COUNT, Msr);
5661 @note MSR_IA32_X2APIC_INIT_COUNT is defined as IA32_X2APIC_INIT_COUNT in SDM.
5663 #define MSR_IA32_X2APIC_INIT_COUNT 0x00000838
5667 x2APIC Current Count Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
5668 IA32_APIC_BASE.[10] = 1.
5670 @param ECX MSR_IA32_X2APIC_CUR_COUNT (0x00000839)
5671 @param EAX Lower 32-bits of MSR value.
5672 @param EDX Upper 32-bits of MSR value.
5674 <b>Example usage</b>
5678 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_CUR_COUNT);
5680 @note MSR_IA32_X2APIC_CUR_COUNT is defined as IA32_X2APIC_CUR_COUNT in SDM.
5682 #define MSR_IA32_X2APIC_CUR_COUNT 0x00000839
5686 x2APIC Divide Configuration Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5687 IA32_APIC_BASE.[10] = 1.
5689 @param ECX MSR_IA32_X2APIC_DIV_CONF (0x0000083E)
5690 @param EAX Lower 32-bits of MSR value.
5691 @param EDX Upper 32-bits of MSR value.
5693 <b>Example usage</b>
5697 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_DIV_CONF);
5698 AsmWriteMsr64 (MSR_IA32_X2APIC_DIV_CONF, Msr);
5700 @note MSR_IA32_X2APIC_DIV_CONF is defined as IA32_X2APIC_DIV_CONF in SDM.
5702 #define MSR_IA32_X2APIC_DIV_CONF 0x0000083E
5706 x2APIC Self IPI Register (W/O). If CPUID.01H:ECX.[21] = 1 &&
5707 IA32_APIC_BASE.[10] = 1.
5709 @param ECX MSR_IA32_X2APIC_SELF_IPI (0x0000083F)
5710 @param EAX Lower 32-bits of MSR value.
5711 @param EDX Upper 32-bits of MSR value.
5713 <b>Example usage</b>
5718 AsmWriteMsr64 (MSR_IA32_X2APIC_SELF_IPI, Msr);
5720 @note MSR_IA32_X2APIC_SELF_IPI is defined as IA32_X2APIC_SELF_IPI in SDM.
5722 #define MSR_IA32_X2APIC_SELF_IPI 0x0000083F
5726 Silicon Debug Feature Control (R/W). If CPUID.01H:ECX.[11] = 1.
5728 @param ECX MSR_IA32_DEBUG_INTERFACE (0x00000C80)
5729 @param EAX Lower 32-bits of MSR value.
5730 Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.
5731 @param EDX Upper 32-bits of MSR value.
5732 Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.
5734 <b>Example usage</b>
5736 MSR_IA32_DEBUG_INTERFACE_REGISTER Msr;
5738 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUG_INTERFACE);
5739 AsmWriteMsr64 (MSR_IA32_DEBUG_INTERFACE, Msr.Uint64);
5741 @note MSR_IA32_DEBUG_INTERFACE is defined as IA32_DEBUG_INTERFACE in SDM.
5743 #define MSR_IA32_DEBUG_INTERFACE 0x00000C80
5746 MSR information returned for MSR index #MSR_IA32_DEBUG_INTERFACE
5750 /// Individual bit fields
5754 /// [Bit 0] Enable (R/W) BIOS set 1 to enable Silicon debug features.
5755 /// Default is 0. If CPUID.01H:ECX.[11] = 1.
5758 UINT32 Reserved1
:29;
5760 /// [Bit 30] Lock (R/W): If 1, locks any further change to the MSR. The
5761 /// lock bit is set automatically on the first SMI assertion even if not
5762 /// explicitly set by BIOS. Default is 0. If CPUID.01H:ECX.[11] = 1.
5766 /// [Bit 31] Debug Occurred (R/O): This "sticky bit" is set by hardware to
5767 /// indicate the status of bit 0. Default is 0. If CPUID.01H:ECX.[11] = 1.
5769 UINT32 DebugOccurred
:1;
5770 UINT32 Reserved2
:32;
5773 /// All bit fields as a 32-bit value
5777 /// All bit fields as a 64-bit value
5780 } MSR_IA32_DEBUG_INTERFACE_REGISTER
;
5784 L3 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=1):ECX.[2] = 1 ).
5786 @param ECX MSR_IA32_L3_QOS_CFG (0x00000C81)
5787 @param EAX Lower 32-bits of MSR value.
5788 Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.
5789 @param EDX Upper 32-bits of MSR value.
5790 Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.
5792 <b>Example usage</b>
5794 MSR_IA32_L3_QOS_CFG_REGISTER Msr;
5796 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L3_QOS_CFG);
5797 AsmWriteMsr64 (MSR_IA32_L3_QOS_CFG, Msr.Uint64);
5799 @note MSR_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.
5801 #define MSR_IA32_L3_QOS_CFG 0x00000C81
5804 MSR information returned for MSR index #MSR_IA32_L3_QOS_CFG
5808 /// Individual bit fields
5812 /// [Bit 0] Enable (R/W) Set 1 to enable L3 CAT masks and COS to operate
5813 /// in Code and Data Prioritization (CDP) mode.
5816 UINT32 Reserved1
:31;
5817 UINT32 Reserved2
:32;
5820 /// All bit fields as a 32-bit value
5824 /// All bit fields as a 64-bit value
5827 } MSR_IA32_L3_QOS_CFG_REGISTER
;
5831 Monitoring Event Select Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12]
5834 @param ECX MSR_IA32_QM_EVTSEL (0x00000C8D)
5835 @param EAX Lower 32-bits of MSR value.
5836 Described by the type MSR_IA32_QM_EVTSEL_REGISTER.
5837 @param EDX Upper 32-bits of MSR value.
5838 Described by the type MSR_IA32_QM_EVTSEL_REGISTER.
5840 <b>Example usage</b>
5842 MSR_IA32_QM_EVTSEL_REGISTER Msr;
5844 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_EVTSEL);
5845 AsmWriteMsr64 (MSR_IA32_QM_EVTSEL, Msr.Uint64);
5847 @note MSR_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.
5849 #define MSR_IA32_QM_EVTSEL 0x00000C8D
5852 MSR information returned for MSR index #MSR_IA32_QM_EVTSEL
5856 /// Individual bit fields
5860 /// [Bits 7:0] Event ID: ID of a supported monitoring event to report via
5866 /// [Bits 63:32] Resource Monitoring ID: ID for monitoring hardware to
5867 /// report monitored data via IA32_QM_CTR. N = Ceil (Log:sub:`2` (
5868 /// CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).
5870 UINT32 ResourceMonitoringID
:32;
5873 /// All bit fields as a 64-bit value
5876 } MSR_IA32_QM_EVTSEL_REGISTER
;
5880 Monitoring Counter Register (R/O). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] = 1
5883 @param ECX MSR_IA32_QM_CTR (0x00000C8E)
5884 @param EAX Lower 32-bits of MSR value.
5885 Described by the type MSR_IA32_QM_CTR_REGISTER.
5886 @param EDX Upper 32-bits of MSR value.
5887 Described by the type MSR_IA32_QM_CTR_REGISTER.
5889 <b>Example usage</b>
5891 MSR_IA32_QM_CTR_REGISTER Msr;
5893 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_CTR);
5895 @note MSR_IA32_QM_CTR is defined as IA32_QM_CTR in SDM.
5897 #define MSR_IA32_QM_CTR 0x00000C8E
5900 MSR information returned for MSR index #MSR_IA32_QM_CTR
5904 /// Individual bit fields
5908 /// [Bits 31:0] Resource Monitored Data.
5910 UINT32 ResourceMonitoredData
:32;
5912 /// [Bits 61:32] Resource Monitored Data.
5914 UINT32 ResourceMonitoredDataHi
:30;
5916 /// [Bit 62] Unavailable: If 1, indicates data for this RMID is not
5917 /// available or not monitored for this resource or RMID.
5919 UINT32 Unavailable
:1;
5921 /// [Bit 63] Error: If 1, indicates and unsupported RMID or event type was
5922 /// written to IA32_PQR_QM_EVTSEL.
5927 /// All bit fields as a 64-bit value
5930 } MSR_IA32_QM_CTR_REGISTER
;
5934 Resource Association Register (R/W). If ( (CPUID.(EAX=07H, ECX=0):EBX[12]
5935 =1) or (CPUID.(EAX=07H, ECX=0):EBX[15] =1 ) ).
5937 @param ECX MSR_IA32_PQR_ASSOC (0x00000C8F)
5938 @param EAX Lower 32-bits of MSR value.
5939 Described by the type MSR_IA32_PQR_ASSOC_REGISTER.
5940 @param EDX Upper 32-bits of MSR value.
5941 Described by the type MSR_IA32_PQR_ASSOC_REGISTER.
5943 <b>Example usage</b>
5945 MSR_IA32_PQR_ASSOC_REGISTER Msr;
5947 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PQR_ASSOC);
5948 AsmWriteMsr64 (MSR_IA32_PQR_ASSOC, Msr.Uint64);
5950 @note MSR_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
5952 #define MSR_IA32_PQR_ASSOC 0x00000C8F
5955 MSR information returned for MSR index #MSR_IA32_PQR_ASSOC
5959 /// Individual bit fields
5963 /// [Bits 31:0] Resource Monitoring ID (R/W): ID for monitoring hardware
5964 /// to track internal operation, e.g. memory access. N = Ceil (Log:sub:`2`
5965 /// ( CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).
5967 UINT32 ResourceMonitoringID
:32;
5969 /// [Bits 63:32] COS (R/W). The class of service (COS) to enforce (on
5970 /// writes); returns the current COS when read. If ( CPUID.(EAX=07H,
5971 /// ECX=0):EBX.[15] = 1 ).
5976 /// All bit fields as a 64-bit value
5979 } MSR_IA32_PQR_ASSOC_REGISTER
;
5983 Supervisor State of MPX Configuration. (R/W). If (CPUID.(EAX=07H,
5984 ECX=0H):EBX[14] = 1).
5986 @param ECX MSR_IA32_BNDCFGS (0x00000D90)
5987 @param EAX Lower 32-bits of MSR value.
5988 Described by the type MSR_IA32_BNDCFGS_REGISTER.
5989 @param EDX Upper 32-bits of MSR value.
5990 Described by the type MSR_IA32_BNDCFGS_REGISTER.
5992 <b>Example usage</b>
5994 MSR_IA32_BNDCFGS_REGISTER Msr;
5996 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BNDCFGS);
5997 AsmWriteMsr64 (MSR_IA32_BNDCFGS, Msr.Uint64);
5999 @note MSR_IA32_BNDCFGS is defined as IA32_BNDCFGS in SDM.
6001 #define MSR_IA32_BNDCFGS 0x00000D90
6004 MSR information returned for MSR index #MSR_IA32_BNDCFGS
6008 /// Individual bit fields
6012 /// [Bit 0] EN: Enable Intel MPX in supervisor mode.
6016 /// [Bit 1] BNDPRESERVE: Preserve the bounds registers for near branch
6017 /// instructions in the absence of the BND prefix.
6019 UINT32 BNDPRESERVE
:1;
6022 /// [Bits 31:12] Base Address of Bound Directory.
6026 /// [Bits 63:32] Base Address of Bound Directory.
6031 /// All bit fields as a 64-bit value
6034 } MSR_IA32_BNDCFGS_REGISTER
;
6038 Extended Supervisor State Mask (R/W). If( CPUID.(0DH, 1):EAX.[3] = 1.
6040 @param ECX MSR_IA32_XSS (0x00000DA0)
6041 @param EAX Lower 32-bits of MSR value.
6042 Described by the type MSR_IA32_XSS_REGISTER.
6043 @param EDX Upper 32-bits of MSR value.
6044 Described by the type MSR_IA32_XSS_REGISTER.
6046 <b>Example usage</b>
6048 MSR_IA32_XSS_REGISTER Msr;
6050 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_XSS);
6051 AsmWriteMsr64 (MSR_IA32_XSS, Msr.Uint64);
6053 @note MSR_IA32_XSS is defined as IA32_XSS in SDM.
6055 #define MSR_IA32_XSS 0x00000DA0
6058 MSR information returned for MSR index #MSR_IA32_XSS
6062 /// Individual bit fields
6067 /// [Bit 8] Trace Packet Configuration State (R/W).
6069 UINT32 TracePacketConfigurationState
:1;
6070 UINT32 Reserved2
:23;
6071 UINT32 Reserved3
:32;
6074 /// All bit fields as a 32-bit value
6078 /// All bit fields as a 64-bit value
6081 } MSR_IA32_XSS_REGISTER
;
6085 Package Level Enable/disable HDC (R/W). If CPUID.06H:EAX.[13] = 1.
6087 @param ECX MSR_IA32_PKG_HDC_CTL (0x00000DB0)
6088 @param EAX Lower 32-bits of MSR value.
6089 Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.
6090 @param EDX Upper 32-bits of MSR value.
6091 Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.
6093 <b>Example usage</b>
6095 MSR_IA32_PKG_HDC_CTL_REGISTER Msr;
6097 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PKG_HDC_CTL);
6098 AsmWriteMsr64 (MSR_IA32_PKG_HDC_CTL, Msr.Uint64);
6100 @note MSR_IA32_PKG_HDC_CTL is defined as IA32_PKG_HDC_CTL in SDM.
6102 #define MSR_IA32_PKG_HDC_CTL 0x00000DB0
6105 MSR information returned for MSR index #MSR_IA32_PKG_HDC_CTL
6109 /// Individual bit fields
6113 /// [Bit 0] HDC_Pkg_Enable (R/W) Force HDC idling or wake up HDC-idled
6114 /// logical processors in the package. See Section 14.5.2, "Package level
6115 /// Enabling HDC". If CPUID.06H:EAX.[13] = 1.
6117 UINT32 HDC_Pkg_Enable
:1;
6118 UINT32 Reserved1
:31;
6119 UINT32 Reserved2
:32;
6122 /// All bit fields as a 32-bit value
6126 /// All bit fields as a 64-bit value
6129 } MSR_IA32_PKG_HDC_CTL_REGISTER
;
6133 Enable/disable HWP (R/W). If CPUID.06H:EAX.[13] = 1.
6135 @param ECX MSR_IA32_PM_CTL1 (0x00000DB1)
6136 @param EAX Lower 32-bits of MSR value.
6137 Described by the type MSR_IA32_PM_CTL1_REGISTER.
6138 @param EDX Upper 32-bits of MSR value.
6139 Described by the type MSR_IA32_PM_CTL1_REGISTER.
6141 <b>Example usage</b>
6143 MSR_IA32_PM_CTL1_REGISTER Msr;
6145 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_CTL1);
6146 AsmWriteMsr64 (MSR_IA32_PM_CTL1, Msr.Uint64);
6148 @note MSR_IA32_PM_CTL1 is defined as IA32_PM_CTL1 in SDM.
6150 #define MSR_IA32_PM_CTL1 0x00000DB1
6153 MSR information returned for MSR index #MSR_IA32_PM_CTL1
6157 /// Individual bit fields
6161 /// [Bit 0] HDC_Allow_Block (R/W) Allow/Block this logical processor for
6162 /// package level HDC control. See Section 14.5.3.
6163 /// If CPUID.06H:EAX.[13] = 1.
6165 UINT32 HDC_Allow_Block
:1;
6166 UINT32 Reserved1
:31;
6167 UINT32 Reserved2
:32;
6170 /// All bit fields as a 32-bit value
6174 /// All bit fields as a 64-bit value
6177 } MSR_IA32_PM_CTL1_REGISTER
;
6181 Per-Logical_Processor HDC Idle Residency (R/0). If CPUID.06H:EAX.[13] = 1.
6182 Stall_Cycle_Cnt (R/W) Stalled cycles due to HDC forced idle on this logical
6183 processor. See Section 14.5.4.1. If CPUID.06H:EAX.[13] = 1.
6185 @param ECX MSR_IA32_THREAD_STALL (0x00000DB2)
6186 @param EAX Lower 32-bits of MSR value.
6187 @param EDX Upper 32-bits of MSR value.
6189 <b>Example usage</b>
6193 Msr = AsmReadMsr64 (MSR_IA32_THREAD_STALL);
6195 @note MSR_IA32_THREAD_STALL is defined as IA32_THREAD_STALL in SDM.
6197 #define MSR_IA32_THREAD_STALL 0x00000DB2
6201 Extended Feature Enables. If ( CPUID.80000001H:EDX.[2 0]
6202 CPUID.80000001H:EDX.[2 9]).
6204 @param ECX MSR_IA32_EFER (0xC0000080)
6205 @param EAX Lower 32-bits of MSR value.
6206 Described by the type MSR_IA32_EFER_REGISTER.
6207 @param EDX Upper 32-bits of MSR value.
6208 Described by the type MSR_IA32_EFER_REGISTER.
6210 <b>Example usage</b>
6212 MSR_IA32_EFER_REGISTER Msr;
6214 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);
6215 AsmWriteMsr64 (MSR_IA32_EFER, Msr.Uint64);
6217 @note MSR_IA32_EFER is defined as IA32_EFER in SDM.
6219 #define MSR_IA32_EFER 0xC0000080
6222 MSR information returned for MSR index #MSR_IA32_EFER
6226 /// Individual bit fields
6230 /// [Bit 0] SYSCALL Enable: IA32_EFER.SCE (R/W) Enables SYSCALL/SYSRET
6231 /// instructions in 64-bit mode.
6236 /// [Bit 8] IA-32e Mode Enable: IA32_EFER.LME (R/W) Enables IA-32e mode
6242 /// [Bit 10] IA-32e Mode Active: IA32_EFER.LMA (R) Indicates IA-32e mode
6243 /// is active when set.
6247 /// [Bit 11] Execute Disable Bit Enable: IA32_EFER.NXE (R/W).
6250 UINT32 Reserved3
:20;
6251 UINT32 Reserved4
:32;
6254 /// All bit fields as a 32-bit value
6258 /// All bit fields as a 64-bit value
6261 } MSR_IA32_EFER_REGISTER
;
6265 System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.
6267 @param ECX MSR_IA32_STAR (0xC0000081)
6268 @param EAX Lower 32-bits of MSR value.
6269 @param EDX Upper 32-bits of MSR value.
6271 <b>Example usage</b>
6275 Msr = AsmReadMsr64 (MSR_IA32_STAR);
6276 AsmWriteMsr64 (MSR_IA32_STAR, Msr);
6278 @note MSR_IA32_STAR is defined as IA32_STAR in SDM.
6280 #define MSR_IA32_STAR 0xC0000081
6284 IA-32e Mode System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.
6286 @param ECX MSR_IA32_LSTAR (0xC0000082)
6287 @param EAX Lower 32-bits of MSR value.
6288 @param EDX Upper 32-bits of MSR value.
6290 <b>Example usage</b>
6294 Msr = AsmReadMsr64 (MSR_IA32_LSTAR);
6295 AsmWriteMsr64 (MSR_IA32_LSTAR, Msr);
6297 @note MSR_IA32_LSTAR is defined as IA32_LSTAR in SDM.
6299 #define MSR_IA32_LSTAR 0xC0000082
6303 System Call Flag Mask (R/W). If CPUID.80000001:EDX.[29] = 1.
6305 @param ECX MSR_IA32_FMASK (0xC0000084)
6306 @param EAX Lower 32-bits of MSR value.
6307 @param EDX Upper 32-bits of MSR value.
6309 <b>Example usage</b>
6313 Msr = AsmReadMsr64 (MSR_IA32_FMASK);
6314 AsmWriteMsr64 (MSR_IA32_FMASK, Msr);
6316 @note MSR_IA32_FMASK is defined as IA32_FMASK in SDM.
6318 #define MSR_IA32_FMASK 0xC0000084
6322 Map of BASE Address of FS (R/W). If CPUID.80000001:EDX.[29] = 1.
6324 @param ECX MSR_IA32_FS_BASE (0xC0000100)
6325 @param EAX Lower 32-bits of MSR value.
6326 @param EDX Upper 32-bits of MSR value.
6328 <b>Example usage</b>
6332 Msr = AsmReadMsr64 (MSR_IA32_FS_BASE);
6333 AsmWriteMsr64 (MSR_IA32_FS_BASE, Msr);
6335 @note MSR_IA32_FS_BASE is defined as IA32_FS_BASE in SDM.
6337 #define MSR_IA32_FS_BASE 0xC0000100
6341 Map of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.
6343 @param ECX MSR_IA32_GS_BASE (0xC0000101)
6344 @param EAX Lower 32-bits of MSR value.
6345 @param EDX Upper 32-bits of MSR value.
6347 <b>Example usage</b>
6351 Msr = AsmReadMsr64 (MSR_IA32_GS_BASE);
6352 AsmWriteMsr64 (MSR_IA32_GS_BASE, Msr);
6354 @note MSR_IA32_GS_BASE is defined as IA32_GS_BASE in SDM.
6356 #define MSR_IA32_GS_BASE 0xC0000101
6360 Swap Target of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.
6362 @param ECX MSR_IA32_KERNEL_GS_BASE (0xC0000102)
6363 @param EAX Lower 32-bits of MSR value.
6364 @param EDX Upper 32-bits of MSR value.
6366 <b>Example usage</b>
6370 Msr = AsmReadMsr64 (MSR_IA32_KERNEL_GS_BASE);
6371 AsmWriteMsr64 (MSR_IA32_KERNEL_GS_BASE, Msr);
6373 @note MSR_IA32_KERNEL_GS_BASE is defined as IA32_KERNEL_GS_BASE in SDM.
6375 #define MSR_IA32_KERNEL_GS_BASE 0xC0000102
6379 Auxiliary TSC (RW). If CPUID.80000001H: EDX[27] = 1.
6381 @param ECX MSR_IA32_TSC_AUX (0xC0000103)
6382 @param EAX Lower 32-bits of MSR value.
6383 Described by the type MSR_IA32_TSC_AUX_REGISTER.
6384 @param EDX Upper 32-bits of MSR value.
6385 Described by the type MSR_IA32_TSC_AUX_REGISTER.
6387 <b>Example usage</b>
6389 MSR_IA32_TSC_AUX_REGISTER Msr;
6391 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_TSC_AUX);
6392 AsmWriteMsr64 (MSR_IA32_TSC_AUX, Msr.Uint64);
6394 @note MSR_IA32_TSC_AUX is defined as IA32_TSC_AUX in SDM.
6396 #define MSR_IA32_TSC_AUX 0xC0000103
6399 MSR information returned for MSR index #MSR_IA32_TSC_AUX
6403 /// Individual bit fields
6407 /// [Bits 31:0] AUX: Auxiliary signature of TSC.
6413 /// All bit fields as a 32-bit value
6417 /// All bit fields as a 64-bit value
6420 } MSR_IA32_TSC_AUX_REGISTER
;