2 CPUID leaf definitions.
4 Provides defines for CPUID leaf indexes. Data structures are provided for
5 registers returned by a CPUID leaf that contain one or more bit fields.
6 If a register returned is a single 32-bit value, then a data structure is
7 not provided for that register.
9 Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials are licensed and made available under
11 the terms and conditions of the BSD License which accompanies this distribution.
12 The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A,
20 December 2015, CPUID instruction.
28 CPUID Signature Information
30 @param EAX CPUID_SIGNATURE (0x00)
32 @retval EAX Returns the highest value the CPUID instruction recognizes for
33 returning basic processor information. The value is returned is
35 @retval EBX First 4 characters of a vendor identification string.
36 @retval ECX Last 4 characters of a vendor identification string.
37 @retval EDX Middle 4 characters of a vendor identification string.
46 AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);
49 #define CPUID_SIGNATURE 0x00
52 /// @{ CPUID signature values returned by Intel processors
54 #define CPUID_SIGNATURE_GENUINE_INTEL_EBX SIGNATURE_32 ('G', 'e', 'n', 'u')
55 #define CPUID_SIGNATURE_GENUINE_INTEL_EDX SIGNATURE_32 ('i', 'n', 'e', 'I')
56 #define CPUID_SIGNATURE_GENUINE_INTEL_ECX SIGNATURE_32 ('n', 't', 'e', 'l')
63 CPUID Version Information
65 @param EAX CPUID_VERSION_INFO (0x01)
67 @retval EAX Returns Model, Family, Stepping Information described by the
68 type CPUID_VERSION_INFO_EAX.
69 @retval EBX Returns Brand, Cache Line Size, and Initial APIC ID described by
70 the type CPUID_VERSION_INFO_EBX.
71 @retval ECX CPU Feature Information described by the type
72 CPUID_VERSION_INFO_ECX.
73 @retval EDX CPU Feature Information described by the type
74 CPUID_VERSION_INFO_EDX.
78 CPUID_VERSION_INFO_EAX Eax;
79 CPUID_VERSION_INFO_EBX Ebx;
80 CPUID_VERSION_INFO_ECX Ecx;
81 CPUID_VERSION_INFO_EDX Edx;
83 AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
86 #define CPUID_VERSION_INFO 0x01
89 CPUID Version Information returned in EAX for CPUID leaf
94 /// Individual bit fields
97 UINT32 SteppingId
:4; ///< [Bits 3:0] Stepping ID
98 UINT32 Model
:4; ///< [Bits 7:4] Model
99 UINT32 FamilyId
:4; ///< [Bits 11:8] Family
100 UINT32 ProcessorType
:2; ///< [Bits 13:12] Processor Type
101 UINT32 Reserved1
:2; ///< [Bits 15:14] Reserved
102 UINT32 ExtendedModelId
:4; ///< [Bits 19:16] Extended Model ID
103 UINT32 ExtendedFamilyId
:8; ///< [Bits 27:20] Extended Family ID
104 UINT32 Reserved2
:4; ///< Reserved
107 /// All bit fields as a 32-bit value
110 } CPUID_VERSION_INFO_EAX
;
113 /// @{ Define value for bit field CPUID_VERSION_INFO_EAX.ProcessorType
115 #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_ORIGINAL_OEM_PROCESSOR 0x00
116 #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_INTEL_OVERDRIVE_PROCESSOR 0x01
117 #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_DUAL_PROCESSOR 0x02
123 CPUID Version Information returned in EBX for CPUID leaf
128 /// Individual bit fields
132 /// [Bits 7:0] Provides an entry into a brand string table that contains
133 /// brand strings for IA-32 processors.
137 /// [Bits 15:8] Indicates the size of the cache line flushed by the CLFLUSH
138 /// and CLFLUSHOPT instructions in 8-byte increments. This field was
139 /// introduced in the Pentium 4 processor.
141 UINT32 CacheLineSize
:8;
143 /// [Bits 23:16] Maximum number of addressable IDs for logical processors
144 /// in this physical package.
147 /// The nearest power-of-2 integer that is not smaller than EBX[23:16] is
148 /// the number of unique initial APICIDs reserved for addressing different
149 /// logical processors in a physical package. This field is only valid if
150 /// CPUID.1.EDX.HTT[bit 28]= 1.
152 UINT32 MaximumAddressableIdsForLogicalProcessors
:8;
154 /// [Bits 31:24] The 8-bit ID that is assigned to the local APIC on the
155 /// processor during power up. This field was introduced in the Pentium 4
158 UINT32 InitialLocalApicId
:8;
161 /// All bit fields as a 32-bit value
164 } CPUID_VERSION_INFO_EBX
;
167 CPUID Version Information returned in ECX for CPUID leaf
172 /// Individual bit fields
176 /// [Bit 0] Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the
177 /// processor supports this technology
181 /// [Bit 1] A value of 1 indicates the processor supports the PCLMULQDQ
182 /// instruction. Carryless Multiplication
186 /// [Bit 2] 64-bit DS Area. A value of 1 indicates the processor supports
187 /// DS area using 64-bit layout.
191 /// [Bit 3] MONITOR/MWAIT. A value of 1 indicates the processor supports
196 /// [Bit 4] CPL Qualified Debug Store. A value of 1 indicates the processor
197 /// supports the extensions to the Debug Store feature to allow for branch
198 /// message storage qualified by CPL
202 /// [Bit 5] Virtual Machine Extensions. A value of 1 indicates that the
203 /// processor supports this technology.
207 /// [Bit 6] Safer Mode Extensions. A value of 1 indicates that the processor
208 /// supports this technology
212 /// [Bit 7] Enhanced Intel SpeedStep(R) technology. A value of 1 indicates
213 /// that the processor supports this technology
217 /// [Bit 8] Thermal Monitor 2. A value of 1 indicates whether the processor
218 /// supports this technology
222 /// [Bit 9] A value of 1 indicates the presence of the Supplemental Streaming
223 /// SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction
224 /// extensions are not present in the processor.
228 /// [Bit 10] L1 Context ID. A value of 1 indicates the L1 data cache mode
229 /// can be set to either adaptive mode or shared mode. A value of 0 indicates
230 /// this feature is not supported. See definition of the IA32_MISC_ENABLE MSR
231 /// Bit 24 (L1 Data Cache Context Mode) for details
235 /// [Bit 11] A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE
236 /// MSR for silicon debug
240 /// [Bit 12] A value of 1 indicates the processor supports FMA (Fused Multiple
241 /// Add) extensions using YMM state.
245 /// [Bit 13] CMPXCHG16B Available. A value of 1 indicates that the feature
250 /// [Bit 14] xTPR Update Control. A value of 1 indicates that the processor
251 /// supports changing IA32_MISC_ENABLE[Bit 23].
253 UINT32 xTPR_Update_Control
:1;
255 /// [Bit 15] Perfmon and Debug Capability: A value of 1 indicates the
256 /// processor supports the performance and debug feature indication MSR
257 /// IA32_PERF_CAPABILITIES.
262 /// [Bit 17] Process-context identifiers. A value of 1 indicates that the
263 /// processor supports PCIDs and that software may set CR4.PCIDE to 1.
267 /// [Bit 18] A value of 1 indicates the processor supports the ability to
268 /// prefetch data from a memory mapped device. Direct Cache Access.
272 /// [Bit 19] A value of 1 indicates that the processor supports SSE4.1.
276 /// [Bit 20] A value of 1 indicates that the processor supports SSE4.2.
280 /// [Bit 21] A value of 1 indicates that the processor supports x2APIC
285 /// [Bit 22] A value of 1 indicates that the processor supports MOVBE
290 /// [Bit 23] A value of 1 indicates that the processor supports the POPCNT
295 /// [Bit 24] A value of 1 indicates that the processor's local APIC timer
296 /// supports one-shot operation using a TSC deadline value.
298 UINT32 TSC_Deadline
:1;
300 /// [Bit 25] A value of 1 indicates that the processor supports the AESNI
301 /// instruction extensions.
305 /// [Bit 26] A value of 1 indicates that the processor supports the
306 /// XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV
307 /// instructions, and XCR0.
311 /// [Bit 27] A value of 1 indicates that the OS has set CR4.OSXSAVE[Bit 18]
312 /// to enable XSETBV/XGETBV instructions to access XCR0 and to support
313 /// processor extended state management using XSAVE/XRSTOR.
317 /// [Bit 28] A value of 1 indicates the processor supports the AVX instruction
322 /// [Bit 29] A value of 1 indicates that processor supports 16-bit
323 /// floating-point conversion instructions.
327 /// [Bit 30] A value of 1 indicates that processor supports RDRAND instruction.
331 /// [Bit 31] Always returns 0.
336 /// All bit fields as a 32-bit value
339 } CPUID_VERSION_INFO_ECX
;
342 CPUID Version Information returned in EDX for CPUID leaf
347 /// Individual bit fields
351 /// [Bit 0] Floating Point Unit On-Chip. The processor contains an x87 FPU.
355 /// [Bit 1] Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements,
356 /// including CR4.VME for controlling the feature, CR4.PVI for protected
357 /// mode virtual interrupts, software interrupt indirection, expansion of
358 /// the TSS with the software indirection bitmap, and EFLAGS.VIF and
359 /// EFLAGS.VIP flags.
363 /// [Bit 2] Debugging Extensions. Support for I/O breakpoints, including
364 /// CR4.DE for controlling the feature, and optional trapping of accesses to
369 /// [Bit 3] Page Size Extension. Large pages of size 4 MByte are supported,
370 /// including CR4.PSE for controlling the feature, the defined dirty bit in
371 /// PDE (Page Directory Entries), optional reserved bit trapping in CR3,
376 /// [Bit 4] Time Stamp Counter. The RDTSC instruction is supported,
377 /// including CR4.TSD for controlling privilege.
381 /// [Bit 5] Model Specific Registers RDMSR and WRMSR Instructions. The
382 /// RDMSR and WRMSR instructions are supported. Some of the MSRs are
383 /// implementation dependent.
387 /// [Bit 6] Physical Address Extension. Physical addresses greater than 32
388 /// bits are supported: extended page table entry formats, an extra level in
389 /// the page translation tables is defined, 2-MByte pages are supported
390 /// instead of 4 Mbyte pages if PAE bit is 1.
394 /// [Bit 7] Machine Check Exception. Exception 18 is defined for Machine
395 /// Checks, including CR4.MCE for controlling the feature. This feature does
396 /// not define the model-specific implementations of machine-check error
397 /// logging, reporting, and processor shutdowns. Machine Check exception
398 /// handlers may have to depend on processor version to do model specific
399 /// processing of the exception, or test for the presence of the Machine
404 /// [Bit 8] CMPXCHG8B Instruction. The compare-and-exchange 8 bytes(64 bits)
405 /// instruction is supported (implicitly locked and atomic).
409 /// [Bit 9] APIC On-Chip. The processor contains an Advanced Programmable
410 /// Interrupt Controller (APIC), responding to memory mapped commands in the
411 /// physical address range FFFE0000H to FFFE0FFFH (by default - some
412 /// processors permit the APIC to be relocated).
417 /// [Bit 11] SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT
418 /// and associated MSRs are supported.
422 /// [Bit 12] Memory Type Range Registers. MTRRs are supported. The MTRRcap
423 /// MSR contains feature bits that describe what memory types are supported,
424 /// how many variable MTRRs are supported, and whether fixed MTRRs are
429 /// [Bit 13] Page Global Bit. The global bit is supported in paging-structure
430 /// entries that map a page, indicating TLB entries that are common to
431 /// different processes and need not be flushed. The CR4.PGE bit controls
436 /// [Bit 14] Machine Check Architecture. The Machine Check Architecture,
437 /// which provides a compatible mechanism for error reporting in P6 family,
438 /// Pentium 4, Intel Xeon processors, and future processors, is supported.
439 /// The MCG_CAP MSR contains feature bits describing how many banks of error
440 /// reporting MSRs are supported.
444 /// [Bit 15] Conditional Move Instructions. The conditional move instruction
445 /// CMOV is supported. In addition, if x87 FPU is present as indicated by the
446 /// CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported.
450 /// [Bit 16] Page Attribute Table. Page Attribute Table is supported. This
451 /// feature augments the Memory Type Range Registers (MTRRs), allowing an
452 /// operating system to specify attributes of memory accessed through a
453 /// linear address on a 4KB granularity.
457 /// [Bit 17] 36-Bit Page Size Extension. 4-MByte pages addressing physical
458 /// memory beyond 4 GBytes are supported with 32-bit paging. This feature
459 /// indicates that upper bits of the physical address of a 4-MByte page are
460 /// encoded in bits 20:13 of the page-directory entry. Such physical
461 /// addresses are limited by MAXPHYADDR and may be up to 40 bits in size.
465 /// [Bit 18] Processor Serial Number. The processor supports the 96-bit
466 /// processor identification number feature and the feature is enabled.
470 /// [Bit 19] CLFLUSH Instruction. CLFLUSH Instruction is supported.
475 /// [Bit 21] Debug Store. The processor supports the ability to write debug
476 /// information into a memory resident buffer. This feature is used by the
477 /// branch trace store (BTS) and precise event-based sampling (PEBS)
482 /// [Bit 22] Thermal Monitor and Software Controlled Clock Facilities. The
483 /// processor implements internal MSRs that allow processor temperature to
484 /// be monitored and processor performance to be modulated in predefined
485 /// duty cycles under software control.
489 /// [Bit 23] Intel MMX Technology. The processor supports the Intel MMX
494 /// [Bit 24] FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR
495 /// instructions are supported for fast save and restore of the floating
496 /// point context. Presence of this bit also indicates that CR4.OSFXSR is
497 /// available for an operating system to indicate that it supports the
498 /// FXSAVE and FXRSTOR instructions.
502 /// [Bit 25] SSE. The processor supports the SSE extensions.
506 /// [Bit 26] SSE2. The processor supports the SSE2 extensions.
510 /// [Bit 27] Self Snoop. The processor supports the management of
511 /// conflicting memory types by performing a snoop of its own cache
512 /// structure for transactions issued to the bus.
516 /// [Bit 28] Max APIC IDs reserved field is Valid. A value of 0 for HTT
517 /// indicates there is only a single logical processor in the package and
518 /// software should assume only a single APIC ID is reserved. A value of 1
519 /// for HTT indicates the value in CPUID.1.EBX[23:16] (the Maximum number of
520 /// addressable IDs for logical processors in this package) is valid for the
525 /// [Bit 29] Thermal Monitor. The processor implements the thermal monitor
526 /// automatic thermal control circuitry (TCC).
531 /// [Bit 31] Pending Break Enable. The processor supports the use of the
532 /// FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is
533 /// asserted) to signal the processor that an interrupt is pending and that
534 /// the processor should return to normal operation to handle the interrupt.
535 /// Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability.
540 /// All bit fields as a 32-bit value
543 } CPUID_VERSION_INFO_EDX
;
547 CPUID Cache and TLB Information
549 @param EAX CPUID_CACHE_INFO (0x02)
551 @retval EAX Cache and TLB Information described by the type
552 CPUID_CACHE_INFO_CACHE_TLB.
553 CPUID_CACHE_INFO_CACHE_TLB.CacheDescriptor[0] always returns
554 0x01 and must be ignored. Only valid if
555 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
556 @retval EBX Cache and TLB Information described by the type
557 CPUID_CACHE_INFO_CACHE_TLB. Only valid if
558 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
559 @retval ECX Cache and TLB Information described by the type
560 CPUID_CACHE_INFO_CACHE_TLB. Only valid if
561 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
562 @retval EDX Cache and TLB Information described by the type
563 CPUID_CACHE_INFO_CACHE_TLB. Only valid if
564 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
568 CPUID_CACHE_INFO_CACHE_TLB Eax;
569 CPUID_CACHE_INFO_CACHE_TLB Ebx;
570 CPUID_CACHE_INFO_CACHE_TLB Ecx;
571 CPUID_CACHE_INFO_CACHE_TLB Edx;
573 AsmCpuid (CPUID_CACHE_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
576 <b>Cache Descriptor values</b>
578 <tr><th>Value </th><th> Type </th><th> Description </th></tr>
579 <tr><td> 0x00 </td><td> General </td><td> Null descriptor, this byte contains no information</td></tr>
580 <tr><td> 0x01 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries</td></tr>
581 <tr><td> 0x02 </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, fully associative, 2 entries</td></tr>
582 <tr><td> 0x03 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 64 entries</td></tr>
583 <tr><td> 0x04 </td><td> TLB </td><td> Data TLB: 4 MByte pages, 4-way set associative, 8 entries</td></tr>
584 <tr><td> 0x05 </td><td> TLB </td><td> Data TLB1: 4 MByte pages, 4-way set associative, 32 entries</td></tr>
585 <tr><td> 0x06 </td><td> Cache </td><td> 1st-level instruction cache: 8 KBytes, 4-way set associative,
586 32 byte line size</td></tr>
587 <tr><td> 0x08 </td><td> Cache </td><td> 1st-level instruction cache: 16 KBytes, 4-way set associative,
588 32 byte line size</td></tr>
589 <tr><td> 0x09 </td><td> Cache </td><td> 1st-level instruction cache: 32KBytes, 4-way set associative,
590 64 byte line size</td></tr>
591 <tr><td> 0x0A </td><td> Cache </td><td> 1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size</td></tr>
592 <tr><td> 0x0B </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries</td></tr>
593 <tr><td> 0x0C </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size</td></tr>
594 <tr><td> 0x0D </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size</td></tr>
595 <tr><td> 0x0E </td><td> Cache </td><td> 1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size</td></tr>
596 <tr><td> 0x1D </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size</td></tr>
597 <tr><td> 0x21 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size</td></tr>
598 <tr><td> 0x22 </td><td> Cache </td><td> 3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size,
599 2 lines per sector</td></tr>
600 <tr><td> 0x23 </td><td> Cache </td><td> 3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size,
601 2 lines per sector</td></tr>
602 <tr><td> 0x24 </td><td> Cache </td><td> 2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size</td></tr>
603 <tr><td> 0x25 </td><td> Cache </td><td> 3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size,
604 2 lines per sector</td></tr>
605 <tr><td> 0x29 </td><td> Cache </td><td> 3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size,
606 2 lines per sector</td></tr>
607 <tr><td> 0x2C </td><td> Cache </td><td> 1st-level data cache: 32 KBytes, 8-way set associative,
608 64 byte line size</td></tr>
609 <tr><td> 0x30 </td><td> Cache </td><td> 1st-level instruction cache: 32 KBytes, 8-way set associative,
610 64 byte line size</td></tr>
611 <tr><td> 0x40 </td><td> Cache </td><td> No 2nd-level cache or, if processor contains a valid 2nd-level cache,
612 no 3rd-level cache</td></tr>
613 <tr><td> 0x41 </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size</td></tr>
614 <tr><td> 0x42 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size</td></tr>
615 <tr><td> 0x43 </td><td> Cache </td><td> 2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size</td></tr>
616 <tr><td> 0x44 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size</td></tr>
617 <tr><td> 0x45 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size</td></tr>
618 <tr><td> 0x46 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size</td></tr>
619 <tr><td> 0x47 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size</td></tr>
620 <tr><td> 0x48 </td><td> Cache </td><td> 2nd-level cache: 3MByte, 12-way set associative, 64 byte line size</td></tr>
621 <tr><td> 0x49 </td><td> Cache </td><td> 3rd-level cache: 4MB, 16-way set associative, 64-byte line size
622 (Intel Xeon processor MP, Family 0FH, Model 06H)<BR>
623 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>
624 <tr><td> 0x4A </td><td> Cache </td><td> 3rd-level cache: 6MByte, 12-way set associative, 64 byte line size</td></tr>
625 <tr><td> 0x4B </td><td> Cache </td><td> 3rd-level cache: 8MByte, 16-way set associative, 64 byte line size</td></tr>
626 <tr><td> 0x4C </td><td> Cache </td><td> 3rd-level cache: 12MByte, 12-way set associative, 64 byte line size</td></tr>
627 <tr><td> 0x4D </td><td> Cache </td><td> 3rd-level cache: 16MByte, 16-way set associative, 64 byte line size</td></tr>
628 <tr><td> 0x4E </td><td> Cache </td><td> 2nd-level cache: 6MByte, 24-way set associative, 64 byte line size</td></tr>
629 <tr><td> 0x4F </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 32 entries</td></tr>
630 <tr><td> 0x50 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries</td></tr>
631 <tr><td> 0x51 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries</td></tr>
632 <tr><td> 0x52 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries</td></tr>
633 <tr><td> 0x55 </td><td> TLB </td><td> Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries</td></tr>
634 <tr><td> 0x56 </td><td> TLB </td><td> Data TLB0: 4 MByte pages, 4-way set associative, 16 entries</td></tr>
635 <tr><td> 0x57 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, 4-way associative, 16 entries</td></tr>
636 <tr><td> 0x59 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, fully associative, 16 entries</td></tr>
637 <tr><td> 0x5A </td><td> TLB </td><td> Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries</td></tr>
638 <tr><td> 0x5B </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 64 entries</td></tr>
639 <tr><td> 0x5C </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,128 entries</td></tr>
640 <tr><td> 0x5D </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,256 entries</td></tr>
641 <tr><td> 0x60 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size</td></tr>
642 <tr><td> 0x61 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, fully associative, 48 entries</td></tr>
643 <tr><td> 0x63 </td><td> TLB </td><td> Data TLB: 1 GByte pages, 4-way set associative, 4 entries</td></tr>
644 <tr><td> 0x66 </td><td> Cache </td><td> 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size</td></tr>
645 <tr><td> 0x67 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size</td></tr>
646 <tr><td> 0x68 </td><td> Cache </td><td> 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size</td></tr>
647 <tr><td> 0x6A </td><td> Cache </td><td> uTLB: 4 KByte pages, 8-way set associative, 64 entries</td></tr>
648 <tr><td> 0x6B </td><td> Cache </td><td> DTLB: 4 KByte pages, 8-way set associative, 256 entries</td></tr>
649 <tr><td> 0x6C </td><td> Cache </td><td> DTLB: 2M/4M pages, 8-way set associative, 128 entries</td></tr>
650 <tr><td> 0x6D </td><td> Cache </td><td> DTLB: 1 GByte pages, fully associative, 16 entries</td></tr>
651 <tr><td> 0x70 </td><td> Cache </td><td> Trace cache: 12 K-uop, 8-way set associative</td></tr>
652 <tr><td> 0x71 </td><td> Cache </td><td> Trace cache: 16 K-uop, 8-way set associative</td></tr>
653 <tr><td> 0x72 </td><td> Cache </td><td> Trace cache: 32 K-uop, 8-way set associative</td></tr>
654 <tr><td> 0x76 </td><td> TLB </td><td> Instruction TLB: 2M/4M pages, fully associative, 8 entries</td></tr>
655 <tr><td> 0x78 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 64byte line size</td></tr>
656 <tr><td> 0x79 </td><td> Cache </td><td> 2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size,
657 2 lines per sector</td></tr>
658 <tr><td> 0x7A </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size,
659 2 lines per sector</td></tr>
660 <tr><td> 0x7B </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size,
661 2 lines per sector</td></tr>
662 <tr><td> 0x7C </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size,
663 2 lines per sector</td></tr>
664 <tr><td> 0x7D </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 64byte line size</td></tr>
665 <tr><td> 0x7F </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size</td></tr>
666 <tr><td> 0x80 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size</td></tr>
667 <tr><td> 0x82 </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size</td></tr>
668 <tr><td> 0x83 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size</td></tr>
669 <tr><td> 0x84 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size</td></tr>
670 <tr><td> 0x85 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size</td></tr>
671 <tr><td> 0x86 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>
672 <tr><td> 0x87 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>
673 <tr><td> 0xA0 </td><td> DTLB </td><td> DTLB: 4k pages, fully associative, 32 entries</td></tr>
674 <tr><td> 0xB0 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>
675 <tr><td> 0xB1 </td><td> TLB </td><td> Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries</td></tr>
676 <tr><td> 0xB2 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 4-way set associative, 64 entries</td></tr>
677 <tr><td> 0xB3 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>
678 <tr><td> 0xB4 </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 256 entries</td></tr>
679 <tr><td> 0xB5 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative, 64 entries</td></tr>
680 <tr><td> 0xB6 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative,
681 128 entries</td></tr>
682 <tr><td> 0xBA </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 64 entries</td></tr>
683 <tr><td> 0xC0 </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries</td></tr>
684 <tr><td> 0xC1 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative,
685 1024 entries</td></tr>
686 <tr><td> 0xC2 </td><td> DTLB </td><td> DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries</td></tr>
687 <tr><td> 0xC3 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative,
688 1536 entries. Also 1GBbyte pages, 4-way, 16 entries.</td></tr>
689 <tr><td> 0xCA </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries</td></tr>
690 <tr><td> 0xD0 </td><td> Cache </td><td> 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>
691 <tr><td> 0xD1 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size</td></tr>
692 <tr><td> 0xD2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size</td></tr>
693 <tr><td> 0xD6 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>
694 <tr><td> 0xD7 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size</td></tr>
695 <tr><td> 0xD8 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size</td></tr>
696 <tr><td> 0xDC </td><td> Cache </td><td> 3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size</td></tr>
697 <tr><td> 0xDD </td><td> Cache </td><td> 3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size</td></tr>
698 <tr><td> 0xDE </td><td> Cache </td><td> 3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size</td></tr>
699 <tr><td> 0xE2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size</td></tr>
700 <tr><td> 0xE3 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>
701 <tr><td> 0xE4 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size</td></tr>
702 <tr><td> 0xEA </td><td> Cache </td><td> 3rd-level cache: 12MByte, 24-way set associative, 64 byte line size</td></tr>
703 <tr><td> 0xEB </td><td> Cache </td><td> 3rd-level cache: 18MByte, 24-way set associative, 64 byte line size</td></tr>
704 <tr><td> 0xEC </td><td> Cache </td><td> 3rd-level cache: 24MByte, 24-way set associative, 64 byte line size</td></tr>
705 <tr><td> 0xF0 </td><td> Prefetch</td><td> 64-Byte prefetching</td></tr>
706 <tr><td> 0xF1 </td><td> Prefetch</td><td> 128-Byte prefetching</td></tr>
707 <tr><td> 0xFF </td><td> General </td><td> CPUID leaf 2 does not report cache descriptor information,
708 use CPUID leaf 4 to query cache parameters</td></tr>
711 #define CPUID_CACHE_INFO 0x02
714 CPUID Cache and TLB Information returned in EAX, EBX, ECX, and EDX for CPUID
715 leaf #CPUID_CACHE_INFO.
719 /// Individual bit fields
724 /// [Bit 31] If 0, then the cache descriptor bytes in the register are valid.
725 /// if 1, then none of the cache descriptor bytes in the register are valid.
730 /// Array of Cache and TLB descriptor bytes
732 UINT8 CacheDescriptor
[4];
734 /// All bit fields as a 32-bit value
737 } CPUID_CACHE_INFO_CACHE_TLB
;
741 CPUID Processor Serial Number
743 Processor serial number (PSN) is not supported in the Pentium 4 processor
744 or later. On all models, use the PSN flag (returned using CPUID) to check
745 for PSN support before accessing the feature.
747 @param EAX CPUID_SERIAL_NUMBER (0x03)
749 @retval EAX Reserved.
750 @retval EBX Reserved.
751 @retval ECX Bits 31:0 of 96 bit processor serial number. (Available in
752 Pentium III processor only; otherwise, the value in this
753 register is reserved.)
754 @retval EDX Bits 63:32 of 96 bit processor serial number. (Available in
755 Pentium III processor only; otherwise, the value in this
756 register is reserved.)
763 AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx);
766 #define CPUID_SERIAL_NUMBER 0x03
770 CPUID Cache Parameters
772 @param EAX CPUID_CACHE_PARAMS (0x04)
773 @param ECX Cache Level. Valid values start at 0. Software can enumerate
774 the deterministic cache parameters for each level of the cache
775 hierarchy starting with an index value of 0, until the
776 parameters report the value associated with the CacheType
777 field in CPUID_CACHE_PARAMS_EAX is 0.
779 @retval EAX Returns cache type information described by the type
780 CPUID_CACHE_PARAMS_EAX.
781 @retval EBX Returns cache line and associativity information described by
782 the type CPUID_CACHE_PARAMS_EBX.
783 @retval ECX Returns the number of sets in the cache.
784 @retval EDX Returns cache WINVD/INVD behavior described by the type
785 CPUID_CACHE_PARAMS_EDX.
790 CPUID_CACHE_PARAMS_EAX Eax;
791 CPUID_CACHE_PARAMS_EBX Ebx;
793 CPUID_CACHE_PARAMS_EDX Edx;
798 CPUID_CACHE_PARAMS, CacheLevel,
799 &Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32
802 } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);
805 #define CPUID_CACHE_PARAMS 0x04
808 CPUID Cache Parameters Information returned in EAX for CPUID leaf
813 /// Individual bit fields
817 /// [Bits 4:0] Cache type field. If #CPUID_CACHE_PARAMS_CACHE_TYPE_NULL,
818 /// then there is no information for the requested cache level.
822 /// [Bits 7:5] Cache level (Starts at 1).
826 /// [Bit 8] Self Initializing cache level (does not need SW initialization).
828 UINT32 SelfInitializingCache
:1;
830 /// [Bit 9] Fully Associative cache.
832 UINT32 FullyAssociativeCache
:1;
834 /// [Bits 13:10] Reserved.
838 /// [Bits 25:14] Maximum number of addressable IDs for logical processors
839 /// sharing this cache.
841 /// Add one to the return value to get the result.
842 /// The nearest power-of-2 integer that is not smaller than (1 + EAX[25:14])
843 /// is the number of unique initial APIC IDs reserved for addressing
844 /// different logical processors sharing this cache.
846 UINT32 MaximumAddressableIdsForLogicalProcessors
:12;
848 /// [Bits 31:26] Maximum number of addressable IDs for processor cores in
849 /// the physical package.
851 /// The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26])
852 /// is the number of unique Core_IDs reserved for addressing different
853 /// processor cores in a physical package. Core ID is a subset of bits of
854 /// the initial APIC ID.
855 /// The returned value is constant for valid initial values in ECX. Valid
856 /// ECX values start from 0.
858 UINT32 MaximumAddressableIdsForProcessorCores
:6;
861 /// All bit fields as a 32-bit value
864 } CPUID_CACHE_PARAMS_EAX
;
867 /// @{ Define value for bit field CPUID_CACHE_PARAMS_EAX.CacheType
869 #define CPUID_CACHE_PARAMS_CACHE_TYPE_NULL 0x00
870 #define CPUID_CACHE_PARAMS_CACHE_TYPE_DATA 0x01
871 #define CPUID_CACHE_PARAMS_CACHE_TYPE_INSTRUCTION 0x02
872 #define CPUID_CACHE_PARAMS_CACHE_TYPE_UNIFIED 0x03
878 CPUID Cache Parameters Information returned in EBX for CPUID leaf
883 /// Individual bit fields
887 /// [Bits 11:0] System Coherency Line Size. Add one to the return value to
892 /// [Bits 21:12] Physical Line Partitions. Add one to the return value to
895 UINT32 LinePartitions
:10;
897 /// [Bits 31:22] Ways of associativity. Add one to the return value to get
903 /// All bit fields as a 32-bit value
906 } CPUID_CACHE_PARAMS_EBX
;
909 CPUID Cache Parameters Information returned in EDX for CPUID leaf
914 /// Individual bit fields
918 /// [Bit 0] Write-Back Invalidate/Invalidate.
919 /// 0 = WBINVD/INVD from threads sharing this cache acts upon lower level
920 /// caches for threads sharing this cache.
921 /// 1 = WBINVD/INVD is not guaranteed to act upon lower level caches of
922 /// non-originating threads sharing this cache.
926 /// [Bit 1] Cache Inclusiveness.
927 /// 0 = Cache is not inclusive of lower cache levels.
928 /// 1 = Cache is inclusive of lower cache levels.
930 UINT32 CacheInclusiveness
:1;
932 /// [Bit 2] Complex Cache Indexing.
933 /// 0 = Direct mapped cache.
934 /// 1 = A complex function is used to index the cache, potentially using all
937 UINT32 ComplexCacheIndexing
:1;
941 /// All bit fields as a 32-bit value
944 } CPUID_CACHE_PARAMS_EDX
;
948 CPUID MONITOR/MWAIT Information
950 @param EAX CPUID_MONITOR_MWAIT (0x05)
952 @retval EAX Smallest monitor-line size in bytes described by the type
953 CPUID_MONITOR_MWAIT_EAX.
954 @retval EBX Largest monitor-line size in bytes described by the type
955 CPUID_MONITOR_MWAIT_EBX.
956 @retval ECX Enumeration of Monitor-Mwait extensions support described by
957 the type CPUID_MONITOR_MWAIT_ECX.
958 @retval EDX Sub C-states supported described by the type
959 CPUID_MONITOR_MWAIT_EDX.
963 CPUID_MONITOR_MWAIT_EAX Eax;
964 CPUID_MONITOR_MWAIT_EBX Ebx;
965 CPUID_MONITOR_MWAIT_ECX Ecx;
966 CPUID_MONITOR_MWAIT_EDX Edx;
968 AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
971 #define CPUID_MONITOR_MWAIT 0x05
974 CPUID MONITOR/MWAIT Information returned in EAX for CPUID leaf
975 #CPUID_MONITOR_MWAIT.
979 /// Individual bit fields
983 /// [Bits 15:0] Smallest monitor-line size in bytes (default is processor's
984 /// monitor granularity).
986 UINT32 SmallestMonitorLineSize
:16;
990 /// All bit fields as a 32-bit value
993 } CPUID_MONITOR_MWAIT_EAX
;
996 CPUID MONITOR/MWAIT Information returned in EBX for CPUID leaf
997 #CPUID_MONITOR_MWAIT.
1001 /// Individual bit fields
1005 /// [Bits 15:0] Largest monitor-line size in bytes (default is processor's
1006 /// monitor granularity).
1008 UINT32 LargestMonitorLineSize
:16;
1012 /// All bit fields as a 32-bit value
1015 } CPUID_MONITOR_MWAIT_EBX
;
1018 CPUID MONITOR/MWAIT Information returned in ECX for CPUID leaf
1019 #CPUID_MONITOR_MWAIT.
1023 /// Individual bit fields
1027 /// [Bit 0] If 0, then only EAX and EBX are valid. If 1, then EAX, EBX, ECX,
1028 /// and EDX are valid.
1030 UINT32 ExtensionsSupported
:1;
1032 /// [Bit 1] Supports treating interrupts as break-event for MWAIT, even when
1033 /// interrupts disabled.
1035 UINT32 InterruptAsBreak
:1;
1039 /// All bit fields as a 32-bit value
1042 } CPUID_MONITOR_MWAIT_ECX
;
1045 CPUID MONITOR/MWAIT Information returned in EDX for CPUID leaf
1046 #CPUID_MONITOR_MWAIT.
1049 The definition of C0 through C7 states for MWAIT extension are
1050 processor-specific C-states, not ACPI C-states.
1054 /// Individual bit fields
1058 /// [Bits 3:0] Number of C0 sub C-states supported using MWAIT.
1062 /// [Bits 7:4] Number of C1 sub C-states supported using MWAIT.
1066 /// [Bits 11:8] Number of C2 sub C-states supported using MWAIT.
1070 /// [Bits 15:12] Number of C3 sub C-states supported using MWAIT.
1074 /// [Bits 19:16] Number of C4 sub C-states supported using MWAIT.
1078 /// [Bits 23:20] Number of C5 sub C-states supported using MWAIT.
1082 /// [Bits 27:24] Number of C6 sub C-states supported using MWAIT.
1086 /// [Bits 31:28] Number of C7 sub C-states supported using MWAIT.
1091 /// All bit fields as a 32-bit value
1094 } CPUID_MONITOR_MWAIT_EDX
;
1098 CPUID Thermal and Power Management
1100 @param EAX CPUID_THERMAL_POWER_MANAGEMENT (0x06)
1102 @retval EAX Thermal and power management features described by the type
1103 CPUID_THERMAL_POWER_MANAGEMENT_EAX.
1104 @retval EBX Number of Interrupt Thresholds in Digital Thermal Sensor
1105 described by the type CPUID_THERMAL_POWER_MANAGEMENT_EBX.
1106 @retval ECX Performance features described by the type
1107 CPUID_THERMAL_POWER_MANAGEMENT_ECX.
1108 @retval EDX Reserved.
1110 <b>Example usage</b>
1112 CPUID_THERMAL_POWER_MANAGEMENT_EAX Eax;
1113 CPUID_THERMAL_POWER_MANAGEMENT_EBX Ebx;
1114 CPUID_THERMAL_POWER_MANAGEMENT_ECX Ecx;
1116 AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
1119 #define CPUID_THERMAL_POWER_MANAGEMENT 0x06
1122 CPUID Thermal and Power Management Information returned in EAX for CPUID leaf
1123 #CPUID_THERMAL_POWER_MANAGEMENT.
1127 /// Individual bit fields
1131 /// [Bit 0] Digital temperature sensor is supported if set.
1133 UINT32 DigitalTemperatureSensor
:1;
1135 /// [Bit 1] Intel Turbo Boost Technology Available (see IA32_MISC_ENABLE[38]).
1137 UINT32 TurboBoostTechnology
:1;
1139 /// [Bit 2] APIC-Timer-always-running feature is supported if set.
1144 /// [Bit 4] Power limit notification controls are supported if set.
1148 /// [Bit 5] Clock modulation duty cycle extension is supported if set.
1152 /// [Bit 6] Package thermal management is supported if set.
1156 /// [Bit 7] HWP base registers (IA32_PM_ENABLE[Bit 0], IA32_HWP_CAPABILITIES,
1157 /// IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.
1161 /// [Bit 8] IA32_HWP_INTERRUPT MSR is supported if set.
1163 UINT32 HWP_Notification
:1;
1165 /// [Bit 9] IA32_HWP_REQUEST[Bits 41:32] is supported if set.
1167 UINT32 HWP_Activity_Window
:1;
1169 /// [Bit 10] IA32_HWP_REQUEST[Bits 31:24] is supported if set.
1171 UINT32 HWP_Energy_Performance_Preference
:1;
1173 /// [Bit 11] IA32_HWP_REQUEST_PKG MSR is supported if set.
1175 UINT32 HWP_Package_Level_Request
:1;
1178 /// [Bit 13] HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1,
1179 /// IA32_THREAD_STALL MSRs are supported if set.
1182 UINT32 Reserved3
:18;
1185 /// All bit fields as a 32-bit value
1188 } CPUID_THERMAL_POWER_MANAGEMENT_EAX
;
1191 CPUID Thermal and Power Management Information returned in EBX for CPUID leaf
1192 #CPUID_THERMAL_POWER_MANAGEMENT.
1196 /// Individual bit fields
1200 /// {Bits 3:0] Number of Interrupt Thresholds in Digital Thermal Sensor.
1202 UINT32 InterruptThresholds
:4;
1206 /// All bit fields as a 32-bit value
1209 } CPUID_THERMAL_POWER_MANAGEMENT_EBX
;
1212 CPUID Thermal and Power Management Information returned in ECX for CPUID leaf
1213 #CPUID_THERMAL_POWER_MANAGEMENT.
1217 /// Individual bit fields
1221 /// [Bit 0] Hardware Coordination Feedback Capability (Presence of IA32_MPERF
1222 /// and IA32_APERF). The capability to provide a measure of delivered
1223 /// processor performance (since last reset of the counters), as a percentage
1224 /// of the expected processor performance when running at the TSC frequency.
1226 UINT32 HardwareCoordinationFeedback
:1;
1229 /// [Bit 3] If this bit is set, then the processor supports performance-energy
1230 /// bias preference and the architectural MSR called IA32_ENERGY_PERF_BIAS
1233 UINT32 PerformanceEnergyBias
:1;
1234 UINT32 Reserved2
:28;
1237 /// All bit fields as a 32-bit value
1240 } CPUID_THERMAL_POWER_MANAGEMENT_ECX
;
1244 CPUID Structured Extended Feature Flags Enumeration
1246 @param EAX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07)
1247 @param ECX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO (0x00).
1250 If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf
1251 index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX.
1253 @retval EAX The maximum input value for ECX to retrieve sub-leaf information.
1254 @retval EBX Structured Extended Feature Flags described by the type
1255 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX.
1256 @retval EBX Structured Extended Feature Flags described by the type
1257 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX.
1258 @retval EDX Reserved.
1260 <b>Example usage</b>
1263 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;
1264 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx;
1268 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
1269 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
1270 &Eax, NULL, NULL, NULL
1272 for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) {
1274 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
1276 NULL, &Ebx.Uint32, &Ecx.Uint32, NULL
1279 } while (SubLeaf <= Eax);
1282 #define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07
1285 /// CPUID Structured Extended Feature Flags Enumeration sub-leaf
1287 #define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO 0x00
1290 CPUID Structured Extended Feature Flags Enumeration in EBX for CPUID leaf
1291 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf
1292 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.
1296 /// Individual bit fields
1300 /// [Bit 0] Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.
1304 /// [Bit 1] IA32_TSC_ADJUST MSR is supported if 1.
1306 UINT32 IA32_TSC_ADJUST
:1;
1309 /// [Bit 3] If 1 indicates the processor supports the first group of advanced
1310 /// bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT)
1314 /// [Bit 4] Hardware Lock Elision
1318 /// [Bit 5] If 1 indicates the processor supports AVX2 instruction extensions.
1322 /// [Bit 6] x87 FPU Data Pointer updated only on x87 exceptions if 1.
1324 UINT32 FDP_EXCPTN_ONLY
:1;
1326 /// [Bit 7] Supports Supervisor-Mode Execution Prevention if 1.
1330 /// [Bit 8] If 1 indicates the processor supports the second group of
1331 /// advanced bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX,
1332 /// SARX, SHLX, SHRX)
1336 /// [Bit 9] Supports Enhanced REP MOVSB/STOSB if 1.
1338 UINT32 EnhancedRepMovsbStosb
:1;
1340 /// [Bit 10] If 1, supports INVPCID instruction for system software that
1341 /// manages process-context identifiers.
1345 /// [Bit 11] Restricted Transactional Memory
1349 /// [Bit 12] Supports Platform Quality of Service Monitoring (PQM)
1350 /// capability if 1.
1354 /// [Bit 13] Deprecates FPU CS and FPU DS values if 1.
1356 UINT32 DeprecateFpuCsDs
:1;
1358 /// [Bit 14] Supports Intel(R) Memory Protection Extensions if 1.
1362 /// [Bit 15] Supports Platform Quality of Service Enforcement (PQE)
1363 /// capability if 1.
1368 /// [Bit 18] If 1 indicates the processor supports the RDSEED instruction.
1372 /// [Bit 19] If 1 indicates the processor supports the ADCX and ADOX
1377 /// [Bit 20] Supports Supervisor-Mode Access Prevention (and the CLAC/STAC
1378 /// instructions) if 1.
1383 /// [Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction.
1385 UINT32 CLFLUSHOPT
:1;
1388 /// [Bit 25] If 1 indicates the processor supports the Intel Processor Trace
1391 UINT32 IntelProcessorTrace
:1;
1395 /// All bit fields as a 32-bit value
1398 } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
;
1401 CPUID Structured Extended Feature Flags Enumeration in ECX for CPUID leaf
1402 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf
1403 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.
1407 /// Individual bit fields
1411 /// [Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction.
1413 UINT32 PREFETCHWT1
:1;
1416 /// [Bit 3] Supports protection keys for user-mode pages if 1.
1420 /// [Bit 4] If 1, OS has set CR4.PKE to enable protection keys (and the
1421 /// RDPKRU/WRPKRU instructions).
1424 UINT32 Reserved2
:27;
1427 /// All bit fields as a 32-bit value
1430 } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX
;
1434 CPUID Direct Cache Access Information
1436 @param EAX CPUID_DIRECT_CACHE_ACCESS_INFO (0x09)
1438 @retval EAX Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1F8H).
1439 @retval EBX Reserved.
1440 @retval ECX Reserved.
1441 @retval EDX Reserved.
1443 <b>Example usage</b>
1447 AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL);
1450 #define CPUID_DIRECT_CACHE_ACCESS_INFO 0x09
1454 CPUID Architectural Performance Monitoring
1456 @param EAX CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING (0x0A)
1458 @retval EAX Architectural Performance Monitoring information described by
1459 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX.
1460 @retval EBX Architectural Performance Monitoring information described by
1461 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX.
1462 @retval ECX Reserved.
1463 @retval EDX Architectural Performance Monitoring information described by
1464 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX.
1466 <b>Example usage</b>
1468 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX Eax;
1469 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX Ebx;
1470 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX Edx;
1472 AsmCpuid (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING, &Eax.Uint32, &Ebx.Uint32, NULL, &Edx.Uint32);
1475 #define CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING 0x0A
1478 CPUID Architectural Performance Monitoring EAX for CPUID leaf
1479 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
1483 /// Individual bit fields
1487 /// [Bit 7:0] Version ID of architectural performance monitoring.
1489 UINT32 ArchPerfMonVerID
:8;
1491 /// [Bits 15:8] Number of general-purpose performance monitoring counter
1492 /// per logical processor.
1494 /// IA32_PERFEVTSELx MSRs start at address 186H and occupy a contiguous
1495 /// block of MSR address space. Each performance event select register is
1496 /// paired with a corresponding performance counter in the 0C1H address
1499 UINT32 PerformanceMonitorCounters
:8;
1501 /// [Bits 23:16] Bit width of general-purpose, performance monitoring counter.
1503 /// The bit width of an IA32_PMCx MSR. This the number of valid bits for
1504 /// read operation. On write operations, the lower-order 32 bits of the MSR
1505 /// may be written with any value, and the high-order bits are sign-extended
1506 /// from the value of bit 31.
1508 UINT32 PerformanceMonitorCounterWidth
:8;
1510 /// [Bits 31:24] Length of EBX bit vector to enumerate architectural
1511 /// performance monitoring events.
1513 UINT32 EbxBitVectorLength
:8;
1516 /// All bit fields as a 32-bit value
1519 } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX
;
1522 CPUID Architectural Performance Monitoring EBX for CPUID leaf
1523 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
1527 /// Individual bit fields
1531 /// [Bit 0] Core cycle event not available if 1.
1533 UINT32 UnhaltedCoreCycles
:1;
1535 /// [Bit 1] Instruction retired event not available if 1.
1537 UINT32 InstructionsRetired
:1;
1539 /// [Bit 2] Reference cycles event not available if 1.
1541 UINT32 UnhaltedReferenceCycles
:1;
1543 /// [Bit 3] Last-level cache reference event not available if 1.
1545 UINT32 LastLevelCacheReferences
:1;
1547 /// [Bit 4] Last-level cache misses event not available if 1.
1549 UINT32 LastLevelCacheMisses
:1;
1551 /// [Bit 5] Branch instruction retired event not available if 1.
1553 UINT32 BranchInstructionsRetired
:1;
1555 /// [Bit 6] Branch mispredict retired event not available if 1.
1557 UINT32 AllBranchMispredictRetired
:1;
1561 /// All bit fields as a 32-bit value
1564 } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX
;
1567 CPUID Architectural Performance Monitoring EDX for CPUID leaf
1568 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
1572 /// Individual bit fields
1576 /// [Bits 4:0] Number of fixed-function performance counters
1577 /// (if Version ID > 1).
1579 UINT32 FixedFunctionPerformanceCounters
:5;
1581 /// [Bits 12:5] Bit width of fixed-function performance counters
1582 /// (if Version ID > 1).
1584 UINT32 FixedFunctionPerformanceCounterWidth
:8;
1588 /// All bit fields as a 32-bit value
1591 } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX
;
1595 CPUID Extended Topology Information
1598 Most of Leaf 0BH output depends on the initial value in ECX. The EDX output
1599 of leaf 0BH is always valid and does not vary with input value in ECX. Output
1600 value in ECX[7:0] always equals input value in ECX[7:0]. For sub-leaves that
1601 return an invalid level-type of 0 in ECX[15:8]; EAX and EBX will return 0. If
1602 an input value n in ECX returns the invalid level-type of 0 in ECX[15:8],
1603 other input values with ECX > n also return 0 in ECX[15:8].
1605 @param EAX CPUID_EXTENDED_TOPOLOGY (0x0B)
1606 @param ECX Level number
1608 @retval EAX Extended topology information described by the type
1609 CPUID_EXTENDED_TOPOLOGY_EAX.
1610 @retval EBX Extended topology information described by the type
1611 CPUID_EXTENDED_TOPOLOGY_EBX.
1612 @retval ECX Extended topology information described by the type
1613 CPUID_EXTENDED_TOPOLOGY_ECX.
1614 @retval EDX x2APIC ID the current logical processor.
1616 <b>Example usage</b>
1618 CPUID_EXTENDED_TOPOLOGY_EAX Eax;
1619 CPUID_EXTENDED_TOPOLOGY_EBX Ebx;
1620 CPUID_EXTENDED_TOPOLOGY_ECX Ecx;
1627 CPUID_EXTENDED_TOPOLOGY, LevelNumber,
1628 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx
1631 } while (Eax.Bits.ApicIdShift != 0);
1634 #define CPUID_EXTENDED_TOPOLOGY 0x0B
1637 CPUID Extended Topology Information EAX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
1641 /// Individual bit fields
1645 /// [Bits 4:0] Number of bits to shift right on x2APIC ID to get a unique
1646 /// topology ID of the next level type. All logical processors with the
1647 /// same next level ID share current level.
1650 /// Software should use this field (EAX[4:0]) to enumerate processor
1651 /// topology of the system.
1653 UINT32 ApicIdShift
:5;
1657 /// All bit fields as a 32-bit value
1660 } CPUID_EXTENDED_TOPOLOGY_EAX
;
1663 CPUID Extended Topology Information EBX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
1667 /// Individual bit fields
1671 /// [Bits 15:0] Number of logical processors at this level type. The number
1672 /// reflects configuration as shipped by Intel.
1675 /// Software must not use EBX[15:0] to enumerate processor topology of the
1676 /// system. This value in this field (EBX[15:0]) is only intended for
1677 /// display/diagnostic purposes. The actual number of logical processors
1678 /// available to BIOS/OS/Applications may be different from the value of
1679 /// EBX[15:0], depending on software and platform hardware configurations.
1681 UINT32 LogicalProcessors
:16;
1685 /// All bit fields as a 32-bit value
1688 } CPUID_EXTENDED_TOPOLOGY_EBX
;
1691 CPUID Extended Topology Information ECX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
1695 /// Individual bit fields
1699 /// [Bits 7:0] Level number. Same value in ECX input.
1701 UINT32 LevelNumber
:8;
1703 /// [Bits 15:8] Level type.
1706 /// The value of the "level type" field is not related to level numbers in
1707 /// any way, higher "level type" values do not mean higher levels.
1713 /// All bit fields as a 32-bit value
1716 } CPUID_EXTENDED_TOPOLOGY_ECX
;
1719 /// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType
1721 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x00
1722 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x01
1723 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x02
1730 CPUID Extended State Information
1732 @param EAX CPUID_EXTENDED_STATE (0x0D)
1733 @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00).
1734 CPUID_EXTENDED_STATE_SUB_LEAF (0x01).
1735 CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02).
1736 Sub leafs 2..n based on supported bits in XCR0 or IA32_XSS_MSR.
1738 #define CPUID_EXTENDED_STATE 0x0D
1741 CPUID Extended State Information Main Leaf
1743 @param EAX CPUID_EXTENDED_STATE (0x0D)
1744 @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00)
1746 @retval EAX Reports the supported bits of the lower 32 bits of XCR0. XCR0[n]
1747 can be set to 1 only if EAX[n] is 1. The format of the extended
1748 state main leaf is described by the type
1749 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX.
1750 @retval EBX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save
1751 area) required by enabled features in XCR0. May be different than
1752 ECX if some features at the end of the XSAVE save area are not
1754 @retval ECX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save
1755 area) of the XSAVE/XRSTOR save area required by all supported
1756 features in the processor, i.e all the valid bit fields in XCR0.
1757 @retval EDX Reports the supported bits of the upper 32 bits of XCR0.
1758 XCR0[n+32] can be set to 1 only if EDX[n] is 1.
1760 <b>Example usage</b>
1762 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax;
1768 CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF,
1769 &Eax.Uint32, &Ebx, &Ecx, &Edx
1773 #define CPUID_EXTENDED_STATE_MAIN_LEAF 0x00
1776 CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,
1777 sub-leaf #CPUID_EXTENDED_STATE_MAIN_LEAF.
1781 /// Individual bit fields
1785 /// [Bit 0] x87 state.
1789 /// [Bit 1] SSE state.
1793 /// [Bit 2] AVX state.
1797 /// [Bits 4:3] MPX state.
1801 /// [Bits 7:5] AVX-512 state.
1805 /// [Bit 8] Used for IA32_XSS.
1809 /// [Bit 9] PKRU state.
1815 /// All bit fields as a 32-bit value
1818 } CPUID_EXTENDED_STATE_MAIN_LEAF_EAX
;
1821 CPUID Extended State Information Sub Leaf
1823 @param EAX CPUID_EXTENDED_STATE (0x0D)
1824 @param ECX CPUID_EXTENDED_STATE_SUB_LEAF (0x01)
1826 @retval EAX The format of the extended state sub-leaf is described by the
1827 type CPUID_EXTENDED_STATE_SUB_LEAF_EAX.
1828 @retval EBX The size in bytes of the XSAVE area containing all states
1829 enabled by XCRO | IA32_XSS.
1830 @retval ECX The format of the extended state sub-leaf is described by the
1831 type CPUID_EXTENDED_STATE_SUB_LEAF_ECX.
1832 @retval EDX Reports the supported bits of the upper 32 bits of the
1833 IA32_XSS MSR. IA32_XSS[n+32] can be set to 1 only if EDX[n] is 1.
1835 <b>Example usage</b>
1837 CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax;
1839 CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx;
1843 CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF,
1844 &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx
1848 #define CPUID_EXTENDED_STATE_SUB_LEAF 0x01
1851 CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,
1852 sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.
1856 /// Individual bit fields
1860 /// [Bit 0] XSAVEOPT is available.
1864 /// [Bit 1] Supports XSAVEC and the compacted form of XRSTOR if set.
1868 /// [Bit 2] Supports XGETBV with ECX = 1 if set.
1872 /// [Bit 3] Supports XSAVES/XRSTORS and IA32_XSS if set.
1878 /// All bit fields as a 32-bit value
1881 } CPUID_EXTENDED_STATE_SUB_LEAF_EAX
;
1884 CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,
1885 sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.
1889 /// Individual bit fields
1893 /// [Bits 7:0] Used for XCR0.
1897 /// [Bit 8] PT STate.
1901 /// [Bit 9] Used for XCR0.
1907 /// All bit fields as a 32-bit value
1910 } CPUID_EXTENDED_STATE_SUB_LEAF_ECX
;
1913 CPUID Extended State Information Size and Offset Sub Leaf
1916 Leaf 0DH output depends on the initial value in ECX.
1917 Each sub-leaf index (starting at position 2) is supported if it corresponds to
1918 a supported bit in either the XCR0 register or the IA32_XSS MSR.
1919 If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf
1920 n (0 <= n <= 31) is invalid if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1
1921 returns 0 in ECX[n]. Sub-leaf n (32 <= n <= 63) is invalid if sub-leaf 0
1922 returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32].
1924 @param EAX CPUID_EXTENDED_STATE (0x0D)
1925 @param ECX CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02). Sub leafs 2..n based
1926 on supported bits in XCR0 or IA32_XSS_MSR.
1928 @retval EAX The size in bytes (from the offset specified in EBX) of the save
1929 area for an extended state feature associated with a valid
1931 @retval EBX The offset in bytes of this extended state component's save area
1932 from the beginning of the XSAVE/XRSTOR area. This field reports
1933 0 if the sub-leaf index, n, does not map to a valid bit in the
1935 @retval ECX The format of the extended state components's save area as
1936 described by the type CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX.
1937 This field reports 0 if the sub-leaf index, n, is invalid.
1938 @retval EDX This field reports 0 if the sub-leaf index, n, is invalid;
1939 otherwise it is reserved.
1941 <b>Example usage</b>
1945 CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX Ecx;
1949 for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) {
1951 CPUID_EXTENDED_STATE, SubLeaf,
1952 &Eax, &Ebx, &Ecx.Uint32, &Edx
1957 #define CPUID_EXTENDED_STATE_SIZE_OFFSET 0x02
1960 CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,
1961 sub-leaf #CPUID_EXTENDED_STATE_SIZE_OFFSET.
1965 /// Individual bit fields
1969 /// [Bit 0] Is set if the bit n (corresponding to the sub-leaf index) is
1970 /// supported in the IA32_XSS MSR; it is clear if bit n is instead supported
1975 /// [Bit 1] is set if, when the compacted format of an XSAVE area is used,
1976 /// this extended state component located on the next 64-byte boundary
1977 /// following the preceding state component (otherwise, it is located
1978 /// immediately following the preceding state component).
1984 /// All bit fields as a 32-bit value
1987 } CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX
;
1991 CPUID Platform QoS Monitoring Information
1993 @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F)
1994 @param ECX CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF (0x00).
1995 CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF (0x01).
1998 #define CPUID_PLATFORM_QOS_MONITORING 0x0F
2001 CPUID Platform QoS Monitoring Information Enumeration Sub-leaf
2003 @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F)
2004 @param ECX CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF (0x00)
2006 @retval EAX Reserved.
2007 @retval EBX Maximum range (zero-based) of RMID within this physical
2008 processor of all types.
2009 @retval ECX Reserved.
2010 @retval EDX L3 Cache QoS Monitoring Information Enumeration described by the
2011 type CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX.
2013 <b>Example usage</b>
2016 CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;
2019 CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF,
2020 NULL, &Ebx, NULL, &Edx.Uint32
2024 #define CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF 0x00
2027 CPUID Platform QoS Monitoring Information EDX for CPUID leaf
2028 #CPUID_PLATFORM_QOS_MONITORING, sub-leaf
2029 #CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF.
2033 /// Individual bit fields
2038 /// [Bit 1] Supports L3 Cache QoS Monitoring if 1.
2040 UINT32 L3CacheQosEnforcement
:1;
2041 UINT32 Reserved2
:30;
2044 /// All bit fields as a 32-bit value
2047 } CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX
;
2050 CPUID Platform QoS Monitoring Information Capability Sub-leaf
2052 @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F)
2053 @param ECX CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF (0x01)
2055 @retval EAX Reserved.
2056 @retval EBX Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes).
2057 @retval ECX Maximum range (zero-based) of RMID of this resource type.
2058 @retval EDX L3 Cache QoS Monitoring Capability information described by the
2059 type CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX.
2061 <b>Example usage</b>
2065 CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX Edx;
2068 CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF,
2069 NULL, &Ebx, &Ecx, &Edx.Uint32
2073 #define CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF 0x01
2076 CPUID Platform QoS Monitoring Information Capability EDX for CPUID leaf
2077 #CPUID_PLATFORM_QOS_MONITORING, sub-leaf
2078 #CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF.
2082 /// Individual bit fields
2086 /// [Bit 0] Supports L3 occupancy monitoring if 1.
2088 UINT32 L3CacheOccupancyMonitoring
:1;
2092 /// All bit fields as a 32-bit value
2095 } CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX
;
2099 CPUID Platform QoS Enforcement Information
2101 @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10).
2102 @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF (0x00).
2103 CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF (0x01).
2104 Additional sub leafs 1..n based in RESID from sub leaf 0x00.
2106 #define CPUID_PLATFORM_QOS_ENFORCEMENT 0x10
2109 CPUID Platform QoS Enforcement Information
2111 @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10)
2112 @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF (0x00).
2114 @retval EAX Reserved.
2115 @retval EBX L3 Cache QoS Enforcement information described by the
2116 type CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX.
2117 @retval ECX Reserved.
2118 @retval EDX Reserved.
2120 <b>Example usage</b>
2122 CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX Ebx;
2125 CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF,
2126 NULL, &Ebx.Uint32, NULL, NULL
2130 #define CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF 0x00
2133 CPUID Platform QoS Enforcement Information EBX for CPUID leaf
2134 #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf
2135 #CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF.
2139 /// Individual bit fields
2144 /// [Bit 1] Supports L3 Cache QoS Enforcement if 1.
2146 UINT32 L3CacheQosEnforcement
:1;
2147 UINT32 Reserved2
:30;
2150 /// All bit fields as a 32-bit value
2153 } CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX
;
2157 CPUID Platform QoS Enforcement Information
2159 @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10)
2160 @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF (0x00)
2161 Additional sub leafs 1..n based in RESID from sub leaf 0x00.
2163 @retval EAX RESID L3 Cache3 QoS Enforcement information described by the
2164 type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX.
2165 @retval EBX Bit-granular map of isolation/contention of allocation units.
2166 @retval ECX RESID L3 Cache3 QoS Enforcement information described by the
2167 type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX.
2168 @retval EDX RESID L3 Cache3 QoS Enforcement information described by the
2169 type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX.
2171 <b>Example usage</b>
2173 CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX Eax;
2175 CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX Ecx;
2176 CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX Edx;
2179 CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF,
2180 &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32
2184 #define CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF 0x01
2187 CPUID Platform QoS Enforcement Information EAX for CPUID leaf
2188 #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf
2189 #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.
2193 /// Individual bit fields
2197 /// [Bits 3:0] Length of the capacity bit mask for the corresponding ResID.
2199 UINT32 CapacityLength
:4;
2203 /// All bit fields as a 32-bit value
2206 } CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX
;
2209 CPUID Platform QoS Enforcement Information ECX for CPUID leaf
2210 #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf
2211 #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.
2215 /// Individual bit fields
2220 /// [Bit 1] Updates of COS should be infrequent if 1.
2222 UINT32 CosUpdatesInfrequent
:1;
2224 /// [Bit 2] Code and Data Prioritization Technology supported if 1.
2226 UINT32 CodeDataPrioritization
:1;
2227 UINT32 Reserved2
:29;
2230 /// All bit fields as a 32-bit value
2233 } CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX
;
2236 CPUID Platform QoS Enforcement Information EDX for CPUID leaf
2237 #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf
2238 #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.
2242 /// Individual bit fields
2246 /// [Bits 15:0] Highest COS number supported for this ResID.
2248 UINT32 HighestCosNumber
:16;
2252 /// All bit fields as a 32-bit value
2255 } CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX
;
2259 CPUID Intel Processor Trace Information
2261 @param EAX CPUID_INTEL_PROCESSOR_TRACE (0x14)
2262 @param ECX CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF (0x00).
2263 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01).
2266 #define CPUID_INTEL_PROCESSOR_TRACE 0x14
2269 CPUID Intel Processor Trace Information Main Leaf
2271 @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)
2272 @param ECX CPUID_INTEL_PROCEDSSOR_TRACE_MAIN_LEAF (0x00)
2274 @retval EAX Reports the maximum sub-leaf supported in leaf 14H.
2275 @retval EBX Returns Intel processor trace information described by the
2276 type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX.
2277 @retval ECX Returns Intel processor trace information described by the
2278 type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX.
2279 @retval EDX Reserved.
2281 <b>Example usage</b>
2284 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Ebx;
2285 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx;
2288 CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,
2289 &Eax, &Ebx.Uint32, &Ecx.Uint32, NULL
2293 #define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF 0x00
2296 CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
2297 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.
2301 /// Individual bit fields
2305 /// [Bit 0] If 1, Indicates that IA32_RTIT_CTL.CR3Filter can be set to 1,
2306 /// and that IA32_RTIT_CR3_MATCH MSR can be accessed.
2310 /// [Bit 1] If 1, Indicates support of Configurable PSB and Cycle-Accurate
2313 UINT32 ConfigurablePsb
:1;
2315 /// [Bit 2] If 1, Indicates support of IP Filtering, TraceStop filtering,
2316 /// and preservation of Intel PT MSRs across warm reset.
2318 UINT32 IpTraceStopFiltering
:1;
2320 /// [Bit 3] If 1, Indicates support of MTC timing packet and suppression of
2321 /// COFI-based packets.
2327 /// All bit fields as a 32-bit value
2330 } CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX
;
2333 CPUID Intel Processor Trace ECX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
2334 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.
2338 /// Individual bit fields
2342 /// [Bit 0] If 1, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence
2343 /// utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and
2344 /// IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.
2348 /// [Bit 1] If 1, ToPA tables can hold any number of output entries, up to
2349 /// the maximum allowed by the MaskOrTableOffset field of
2350 /// IA32_RTIT_OUTPUT_MASK_PTRS.
2354 /// [Bit 2] If 1, Indicates support of Single-Range Output scheme.
2356 UINT32 SingleRangeOutput
:1;
2358 /// [Bit 3] If 1, Indicates support of output to Trace Transport subsystem.
2360 UINT32 TraceTransportSubsystem
:1;
2363 /// [Bit 31] If 1, Generated packets which contain IP payloads have LIP
2364 /// values, which include the CS base component.
2369 /// All bit fields as a 32-bit value
2372 } CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX
;
2376 CPUID Intel Processor Trace Information Sub-leaf
2378 @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)
2379 @param ECX CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01)
2381 @retval EAX Returns Intel processor trace information described by the
2382 type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX.
2383 @retval EBX Returns Intel processor trace information described by the
2384 type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX.
2385 @retval ECX Reserved.
2386 @retval EDX Reserved.
2388 <b>Example usage</b>
2390 UINT32 MaximumSubLeaf;
2392 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX Eax;
2393 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX Ebx;
2396 CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,
2397 &MaximumSubLeaf, NULL, NULL, NULL
2400 for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) {
2402 CPUID_INTEL_PROCESSOR_TRACE, SubLeaf,
2403 &Eax.Uint32, &Ebx.Uint32, NULL, NULL
2408 #define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF 0x01
2411 CPUID Intel Processor Trace EAX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
2412 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.
2416 /// Individual bit fields
2420 /// [Bits 2:0] Number of configurable Address Ranges for filtering.
2422 UINT32 ConfigurableAddressRanges
:3;
2425 /// [Bits 31:16] Bitmap of supported MTC period encodings
2427 UINT32 MtcPeriodEncodings
:16;
2431 /// All bit fields as a 32-bit value
2434 } CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX
;
2437 CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
2438 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.
2442 /// Individual bit fields
2446 /// [Bits 15:0] Bitmap of supported Cycle Threshold value encodings.
2448 UINT32 CycleThresholdEncodings
:16;
2450 /// [Bits 31:16] Bitmap of supported Configurable PSB frequency encodings.
2452 UINT32 PsbFrequencyEncodings
:16;
2456 /// All bit fields as a 32-bit value
2459 } CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX
;
2463 CPUID Time Stamp Counter Information
2466 If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated.
2467 EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core
2468 crystal clock frequency.
2469 "TSC frequency" = "core crystal clock frequency" * EBX/EAX.
2470 The core crystal clock may differ from the reference clock, bus clock, or core
2473 @param EAX CPUID_TIME_STAMP_COUNTER (0x15)
2475 @retval EAX An unsigned integer which is the denominator of the
2476 TSC/"core crystal clock" ratio
2477 @retval EBX An unsigned integer which is the numerator of the
2478 TSC/"core crystal clock" ratio.
2479 @retval ECX Reserved.
2480 @retval EDX Reserved.
2482 <b>Example usage</b>
2487 AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, NULL, NULL);
2490 #define CPUID_TIME_STAMP_COUNTER 0x15
2494 CPUID Processor Frequency Information
2497 Data is returned from this interface in accordance with the processor's
2498 specification and does not reflect actual values. Suitable use of this data
2499 includes the display of processor information in like manner to the processor
2500 brand string and for determining the appropriate range to use when displaying
2501 processor information e.g. frequency history graphs. The returned information
2502 should not be used for any other purpose as the returned information does not
2503 accurately correlate to information / counters returned by other processor
2504 interfaces. While a processor may support the Processor Frequency Information
2505 leaf, fields that return a value of zero are not supported.
2507 @param EAX CPUID_TIME_STAMP_COUNTER (0x16)
2509 @retval EAX Returns processor base frequency information described by the
2510 type CPUID_PROCESSOR_FREQUENCY_EAX.
2511 @retval EBX Returns maximum frequency information described by the type
2512 CPUID_PROCESSOR_FREQUENCY_EBX.
2513 @retval ECX Returns bus frequency information described by the type
2514 CPUID_PROCESSOR_FREQUENCY_ECX.
2515 @retval EDX Reserved.
2517 <b>Example usage</b>
2519 CPUID_PROCESSOR_FREQUENCY_EAX Eax;
2520 CPUID_PROCESSOR_FREQUENCY_EBX Ebx;
2521 CPUID_PROCESSOR_FREQUENCY_ECX Ecx;
2523 AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
2526 #define CPUID_PROCESSOR_FREQUENCY 0x16
2529 CPUID Processor Frequency Information EAX for CPUID leaf
2530 #CPUID_PROCESSOR_FREQUENCY.
2534 /// Individual bit fields
2538 /// [Bits 15:0] Processor Base Frequency (in MHz).
2540 UINT32 ProcessorBaseFrequency
:16;
2544 /// All bit fields as a 32-bit value
2547 } CPUID_PROCESSOR_FREQUENCY_EAX
;
2550 CPUID Processor Frequency Information EBX for CPUID leaf
2551 #CPUID_PROCESSOR_FREQUENCY.
2555 /// Individual bit fields
2559 /// [Bits 15:0] Maximum Frequency (in MHz).
2561 UINT32 MaximumFrequency
:16;
2565 /// All bit fields as a 32-bit value
2568 } CPUID_PROCESSOR_FREQUENCY_EBX
;
2571 CPUID Processor Frequency Information ECX for CPUID leaf
2572 #CPUID_PROCESSOR_FREQUENCY.
2576 /// Individual bit fields
2580 /// [Bits 15:0] Bus (Reference) Frequency (in MHz).
2582 UINT32 BusFrequency
:16;
2586 /// All bit fields as a 32-bit value
2589 } CPUID_PROCESSOR_FREQUENCY_ECX
;
2593 CPUID SoC Vendor Information
2595 @param EAX CPUID_SOC_VENDOR (0x17)
2596 @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00)
2597 CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)
2598 CPUID_SOC_VENDOR_BRAND_STRING1 (0x02)
2599 CPUID_SOC_VENDOR_BRAND_STRING1 (0x03)
2602 Leaf 17H output depends on the initial value in ECX. SOC Vendor Brand String
2603 is a UTF-8 encoded string padded with trailing bytes of 00H. The complete SOC
2604 Vendor Brand String is constructed by concatenating in ascending order of
2605 EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3.
2608 #define CPUID_SOC_VENDOR 0x17
2611 CPUID SoC Vendor Information
2613 @param EAX CPUID_SOC_VENDOR (0x17)
2614 @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00)
2616 @retval EAX MaxSOCID_Index. Reports the maximum input value of supported
2617 sub-leaf in leaf 17H.
2618 @retval EBX Returns SoC Vendor information described by the type
2619 CPUID_SOC_VENDOR_MAIN_LEAF_EBX.
2620 @retval ECX Project ID. A unique number an SOC vendor assigns to its SOC
2622 @retval EDX Stepping ID. A unique number within an SOC project that an SOC
2625 <b>Example usage</b>
2628 CPUID_SOC_VENDOR_MAIN_LEAF_EBX Ebx;
2633 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF,
2634 &Eax, &Ebx.Uint32, &Ecx, &Edx
2638 #define CPUID_SOC_VENDOR_MAIN_LEAF 0x00
2641 CPUID SoC Vendor Information EBX for CPUID leaf #CPUID_SOC_VENDOR sub-leaf
2642 #CPUID_SOC_VENDOR_MAIN_LEAF.
2646 /// Individual bit fields
2650 /// [Bits 15:0] SOC Vendor ID.
2652 UINT32 SocVendorId
:16;
2654 /// [Bit 16] If 1, the SOC Vendor ID field is assigned via an industry
2655 /// standard enumeration scheme. Otherwise, the SOC Vendor ID field is
2656 /// assigned by Intel.
2658 UINT32 IsVendorScheme
:1;
2662 /// All bit fields as a 32-bit value
2665 } CPUID_SOC_VENDOR_MAIN_LEAF_EBX
;
2668 CPUID SoC Vendor Information
2670 @param EAX CPUID_SOC_VENDOR (0x17)
2671 @param ECX CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)
2673 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type
2674 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
2675 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type
2676 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
2677 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type
2678 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
2679 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type
2680 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
2682 <b>Example usage</b>
2684 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;
2685 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;
2686 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;
2687 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;
2690 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1,
2691 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
2695 #define CPUID_SOC_VENDOR_BRAND_STRING1 0x01
2698 CPUID SoC Vendor Brand String for CPUID leafs #CPUID_SOC_VENDOR_BRAND_STRING1,
2699 #CPUID_SOC_VENDOR_BRAND_STRING2, and #CPUID_SOC_VENDOR_BRAND_STRING3.
2703 /// 4 UTF-8 characters of Soc Vendor Brand String
2705 CHAR8 BrandString
[4];
2707 /// All fields as a 32-bit value
2710 } CPUID_SOC_VENDOR_BRAND_STRING_DATA
;
2713 CPUID SoC Vendor Information
2715 @param EAX CPUID_SOC_VENDOR (0x17)
2716 @param ECX CPUID_SOC_VENDOR_BRAND_STRING2 (0x02)
2718 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type
2719 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
2720 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type
2721 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
2722 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type
2723 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
2724 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type
2725 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
2727 <b>Example usage</b>
2729 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;
2730 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;
2731 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;
2732 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;
2735 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2,
2736 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
2740 #define CPUID_SOC_VENDOR_BRAND_STRING2 0x02
2743 CPUID SoC Vendor Information
2745 @param EAX CPUID_SOC_VENDOR (0x17)
2746 @param ECX CPUID_SOC_VENDOR_BRAND_STRING3 (0x03)
2748 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type
2749 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
2750 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type
2751 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
2752 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type
2753 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
2754 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type
2755 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
2757 <b>Example usage</b>
2759 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;
2760 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;
2761 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;
2762 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;
2765 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3,
2766 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
2770 #define CPUID_SOC_VENDOR_BRAND_STRING3 0x03
2774 CPUID Extended Function
2776 @param EAX CPUID_EXTENDED_FUNCTION (0x80000000)
2778 @retval EAX Maximum Input Value for Extended Function CPUID Information.
2779 @retval EBX Reserved.
2780 @retval ECX Reserved.
2781 @retval EDX Reserved.
2783 <b>Example usage</b>
2787 AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);
2790 #define CPUID_EXTENDED_FUNCTION 0x80000000
2794 CPUID Extended Processor Signature and Feature Bits
2796 @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001)
2798 @retval EAX CPUID_EXTENDED_CPU_SIG.
2799 @retval EBX Reserved.
2800 @retval ECX Extended Processor Signature and Feature Bits information
2801 described by the type CPUID_EXTENDED_CPU_SIG_ECX.
2802 @retval EDX Extended Processor Signature and Feature Bits information
2803 described by the type CPUID_EXTENDED_CPU_SIG_EDX.
2805 <b>Example usage</b>
2808 CPUID_EXTENDED_CPU_SIG_ECX Ecx;
2809 CPUID_EXTENDED_CPU_SIG_EDX Edx;
2811 AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32);
2814 #define CPUID_EXTENDED_CPU_SIG 0x80000001
2817 CPUID Extended Processor Signature and Feature Bits ECX for CPUID leaf
2818 #CPUID_EXTENDED_CPU_SIG.
2822 /// Individual bit fields
2826 /// [Bit 0] LAHF/SAHF available in 64-bit mode.
2836 /// [Bit 8] PREFETCHW.
2839 UINT32 Reserved3
:23;
2842 /// All bit fields as a 32-bit value
2845 } CPUID_EXTENDED_CPU_SIG_ECX
;
2848 CPUID Extended Processor Signature and Feature Bits EDX for CPUID leaf
2849 #CPUID_EXTENDED_CPU_SIG.
2853 /// Individual bit fields
2856 UINT32 Reserved1
:11;
2858 /// [Bit 11] SYSCALL/SYSRET available in 64-bit mode.
2860 UINT32 SYSCALL_SYSRET
:1;
2863 /// [Bit 20] Execute Disable Bit available.
2868 /// [Bit 26] 1-GByte pages are available if 1.
2872 /// [Bit 27] RDTSCP and IA32_TSC_AUX are available if 1.
2877 /// [Bit 29] Intel(R) 64 Architecture available if 1.
2883 /// All bit fields as a 32-bit value
2886 } CPUID_EXTENDED_CPU_SIG_EDX
;
2890 CPUID Processor Brand String
2892 @param EAX CPUID_BRAND_STRING1 (0x80000002)
2894 @retval EAX Processor Brand String in type CPUID_BRAND_STRING_DATA.
2895 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
2896 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
2897 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
2899 <b>Example usage</b>
2901 CPUID_BRAND_STRING_DATA Eax;
2902 CPUID_BRAND_STRING_DATA Ebx;
2903 CPUID_BRAND_STRING_DATA Ecx;
2904 CPUID_BRAND_STRING_DATA Edx;
2906 AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
2909 #define CPUID_BRAND_STRING1 0x80000002
2912 CPUID Processor Brand String for CPUID leafs #CPUID_BRAND_STRING1,
2913 #CPUID_BRAND_STRING2, and #CPUID_BRAND_STRING3.
2917 /// 4 ASCII characters of Processor Brand String
2919 CHAR8 BrandString
[4];
2921 /// All fields as a 32-bit value
2924 } CPUID_BRAND_STRING_DATA
;
2927 CPUID Processor Brand String
2929 @param EAX CPUID_BRAND_STRING2 (0x80000003)
2931 @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
2932 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
2933 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
2934 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
2936 <b>Example usage</b>
2938 CPUID_BRAND_STRING_DATA Eax;
2939 CPUID_BRAND_STRING_DATA Ebx;
2940 CPUID_BRAND_STRING_DATA Ecx;
2941 CPUID_BRAND_STRING_DATA Edx;
2943 AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
2946 #define CPUID_BRAND_STRING2 0x80000003
2949 CPUID Processor Brand String
2951 @param EAX CPUID_BRAND_STRING3 (0x80000004)
2953 @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
2954 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
2955 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
2956 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
2958 <b>Example usage</b>
2960 CPUID_BRAND_STRING_DATA Eax;
2961 CPUID_BRAND_STRING_DATA Ebx;
2962 CPUID_BRAND_STRING_DATA Ecx;
2963 CPUID_BRAND_STRING_DATA Edx;
2965 AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
2968 #define CPUID_BRAND_STRING3 0x80000004
2972 CPUID Extended Cache information
2974 @param EAX CPUID_EXTENDED_CACHE_INFO (0x80000006)
2976 @retval EAX Reserved.
2977 @retval EBX Reserved.
2978 @retval ECX Extended cache information described by the type
2979 CPUID_EXTENDED_CACHE_INFO_ECX.
2980 @retval EDX Reserved.
2982 <b>Example usage</b>
2984 CPUID_EXTENDED_CACHE_INFO_ECX Ecx;
2986 AsmCpuid (CPUID_EXTENDED_CACHE_INFO, NULL, NULL, &Ecx.Uint32, NULL);
2989 #define CPUID_EXTENDED_CACHE_INFO 0x80000006
2992 CPUID Extended Cache information ECX for CPUID leaf #CPUID_EXTENDED_CACHE_INFO.
2996 /// Individual bit fields
3000 /// [Bits 7:0] Cache line size in bytes.
3002 UINT32 CacheLineSize
:8;
3005 /// [Bits 15:12] L2 Associativity field. Supported values are in the range
3006 /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED to
3007 /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL
3009 UINT32 L2Associativity
:4;
3011 /// [Bits 31:16] Cache size in 1K units.
3013 UINT32 CacheSize
:16;
3016 /// All bit fields as a 32-bit value
3019 } CPUID_EXTENDED_CACHE_INFO_ECX
;
3022 /// @{ Define value for bit field CPUID_EXTENDED_CACHE_INFO_ECX.L2Associativity
3024 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED 0x00
3025 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DIRECT_MAPPED 0x01
3026 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_2_WAY 0x02
3027 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_4_WAY 0x04
3028 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_8_WAY 0x06
3029 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_16_WAY 0x08
3030 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL 0x0F
3036 CPUID Extended Time Stamp Counter information
3038 @param EAX CPUID_EXTENDED_TIME_STAMP_COUNTER (0x80000007)
3040 @retval EAX Reserved.
3041 @retval EBX Reserved.
3042 @retval ECX Reserved.
3043 @retval EDX Extended time stamp counter (TSC) information described by the
3044 type CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX.
3046 <b>Example usage</b>
3048 CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX Edx;
3050 AsmCpuid (CPUID_EXTENDED_TIME_STAMP_COUNTER, NULL, NULL, NULL, &Edx.Uint32);
3053 #define CPUID_EXTENDED_TIME_STAMP_COUNTER 0x80000007
3056 CPUID Extended Time Stamp Counter information EDX for CPUID leaf
3057 #CPUID_EXTENDED_TIME_STAMP_COUNTER.
3061 /// Individual bit fields
3066 /// [Bit 8] Invariant TSC available if 1.
3068 UINT32 InvariantTsc
:1;
3069 UINT32 Reserved2
:23;
3072 /// All bit fields as a 32-bit value
3075 } CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX
;
3079 CPUID Linear Physical Address Size
3081 @param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)
3083 @retval EAX Linear/Physical Address Size described by the type
3084 CPUID_VIR_PHY_ADDRESS_SIZE_EAX.
3085 @retval EBX Reserved.
3086 @retval ECX Reserved.
3087 @retval EDX Reserved.
3089 <b>Example usage</b>
3091 CPUID_VIR_PHY_ADDRESS_SIZE_EAX Eax;
3093 AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Eax.Uint32, NULL, NULL, NULL);
3096 #define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008
3099 CPUID Linear Physical Address Size EAX for CPUID leaf
3100 #CPUID_VIR_PHY_ADDRESS_SIZE.
3104 /// Individual bit fields
3108 /// [Bits 7:0] Number of physical address bits.
3111 /// If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address
3112 /// number supported should come from this field.
3114 UINT32 PhysicalAddressBits
:8;
3116 /// [Bits 15:8] Number of linear address bits.
3118 UINT32 LinearAddressBits
:8;
3122 /// All bit fields as a 32-bit value
3125 } CPUID_VIR_PHY_ADDRESS_SIZE_EAX
;
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