864108da62220cf45ccfb33e3ad1b85626533741
[mirror_edk2.git] / UefiCpuPkg / Include / Register / Cpuid.h
1 /** @file
2 CPUID leaf definitions.
3
4 Provides defines for CPUID leaf indexes. Data structures are provided for
5 registers returned by a CPUID leaf that contain one or more bit fields.
6 If a register returned is a single 32-bit value, then a data structure is
7 not provided for that register.
8
9 Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials are licensed and made available under
11 the terms and conditions of the BSD License which accompanies this distribution.
12 The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
14
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A,
20 December 2015, CPUID instruction.
21
22 **/
23
24 #ifndef __CPUID_H__
25 #define __CPUID_H__
26
27 /**
28 CPUID Signature Information
29
30 @param EAX CPUID_SIGNATURE (0x00)
31
32 @retval EAX Returns the highest value the CPUID instruction recognizes for
33 returning basic processor information. The value is returned is
34 processor specific.
35 @retval EBX First 4 characters of a vendor identification string.
36 @retval ECX Last 4 characters of a vendor identification string.
37 @retval EDX Middle 4 characters of a vendor identification string.
38
39 <b>Example usage</b>
40 @code
41 UINT32 Eax;
42 UINT32 Ebx;
43 UINT32 Ecx;
44 UINT32 Edx;
45
46 AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);
47 @endcode
48 **/
49 #define CPUID_SIGNATURE 0x00
50
51 ///
52 /// @{ CPUID signature values returned by Intel processors
53 ///
54 #define CPUID_SIGNATURE_GENUINE_INTEL_EBX SIGNATURE_32 ('G', 'e', 'n', 'u')
55 #define CPUID_SIGNATURE_GENUINE_INTEL_EDX SIGNATURE_32 ('i', 'n', 'e', 'I')
56 #define CPUID_SIGNATURE_GENUINE_INTEL_ECX SIGNATURE_32 ('n', 't', 'e', 'l')
57 ///
58 /// @}
59 ///
60
61
62 /**
63 CPUID Version Information
64
65 @param EAX CPUID_VERSION_INFO (0x01)
66
67 @retval EAX Returns Model, Family, Stepping Information described by the
68 type CPUID_VERSION_INFO_EAX.
69 @retval EBX Returns Brand, Cache Line Size, and Initial APIC ID described by
70 the type CPUID_VERSION_INFO_EBX.
71 @retval ECX CPU Feature Information described by the type
72 CPUID_VERSION_INFO_ECX.
73 @retval EDX CPU Feature Information described by the type
74 CPUID_VERSION_INFO_EDX.
75
76 <b>Example usage</b>
77 @code
78 CPUID_VERSION_INFO_EAX Eax;
79 CPUID_VERSION_INFO_EBX Ebx;
80 CPUID_VERSION_INFO_ECX Ecx;
81 CPUID_VERSION_INFO_EDX Edx;
82
83 AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
84 @endcode
85 **/
86 #define CPUID_VERSION_INFO 0x01
87
88 /**
89 CPUID Version Information returned in EAX for CPUID leaf
90 #CPUID_VERSION_INFO.
91 **/
92 typedef union {
93 ///
94 /// Individual bit fields
95 ///
96 struct {
97 UINT32 SteppingId:4; ///< [Bits 3:0] Stepping ID
98 UINT32 Model:4; ///< [Bits 7:4] Model
99 UINT32 FamilyId:4; ///< [Bits 11:8] Family
100 UINT32 ProcessorType:2; ///< [Bits 13:12] Processor Type
101 UINT32 Reserved1:2; ///< [Bits 15:14] Reserved
102 UINT32 ExtendedModelId:4; ///< [Bits 19:16] Extended Model ID
103 UINT32 ExtendedFamilyId:8; ///< [Bits 27:20] Extended Family ID
104 UINT32 Reserved2:4; ///< Reserved
105 } Bits;
106 ///
107 /// All bit fields as a 32-bit value
108 ///
109 UINT32 Uint32;
110 } CPUID_VERSION_INFO_EAX;
111
112 ///
113 /// @{ Define value for bit field CPUID_VERSION_INFO_EAX.ProcessorType
114 ///
115 #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_ORIGINAL_OEM_PROCESSOR 0x00
116 #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_INTEL_OVERDRIVE_PROCESSOR 0x01
117 #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_DUAL_PROCESSOR 0x02
118 ///
119 /// @}
120 ///
121
122 /**
123 CPUID Version Information returned in EBX for CPUID leaf
124 #CPUID_VERSION_INFO.
125 **/
126 typedef union {
127 ///
128 /// Individual bit fields
129 ///
130 struct {
131 ///
132 /// [Bits 7:0] Provides an entry into a brand string table that contains
133 /// brand strings for IA-32 processors.
134 ///
135 UINT32 BrandIndex:8;
136 ///
137 /// [Bits 15:8] Indicates the size of the cache line flushed by the CLFLUSH
138 /// and CLFLUSHOPT instructions in 8-byte increments. This field was
139 /// introduced in the Pentium 4 processor.
140 ///
141 UINT32 CacheLineSize:8;
142 ///
143 /// [Bits 23:16] Maximum number of addressable IDs for logical processors
144 /// in this physical package.
145 ///
146 /// @note
147 /// The nearest power-of-2 integer that is not smaller than EBX[23:16] is
148 /// the number of unique initial APICIDs reserved for addressing different
149 /// logical processors in a physical package. This field is only valid if
150 /// CPUID.1.EDX.HTT[bit 28]= 1.
151 ///
152 UINT32 MaximumAddressableIdsForLogicalProcessors:8;
153 ///
154 /// [Bits 31:24] The 8-bit ID that is assigned to the local APIC on the
155 /// processor during power up. This field was introduced in the Pentium 4
156 /// processor.
157 ///
158 UINT32 InitialLocalApicId:8;
159 } Bits;
160 ///
161 /// All bit fields as a 32-bit value
162 ///
163 UINT32 Uint32;
164 } CPUID_VERSION_INFO_EBX;
165
166 /**
167 CPUID Version Information returned in ECX for CPUID leaf
168 #CPUID_VERSION_INFO.
169 **/
170 typedef union {
171 ///
172 /// Individual bit fields
173 ///
174 struct {
175 ///
176 /// [Bit 0] Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the
177 /// processor supports this technology
178 ///
179 UINT32 SSE3:1;
180 ///
181 /// [Bit 1] A value of 1 indicates the processor supports the PCLMULQDQ
182 /// instruction. Carryless Multiplication
183 ///
184 UINT32 PCLMULQDQ:1;
185 ///
186 /// [Bit 2] 64-bit DS Area. A value of 1 indicates the processor supports
187 /// DS area using 64-bit layout.
188 ///
189 UINT32 DTES64:1;
190 ///
191 /// [Bit 3] MONITOR/MWAIT. A value of 1 indicates the processor supports
192 /// this feature.
193 ///
194 UINT32 MONITOR:1;
195 ///
196 /// [Bit 4] CPL Qualified Debug Store. A value of 1 indicates the processor
197 /// supports the extensions to the Debug Store feature to allow for branch
198 /// message storage qualified by CPL
199 ///
200 UINT32 DS_CPL:1;
201 ///
202 /// [Bit 5] Virtual Machine Extensions. A value of 1 indicates that the
203 /// processor supports this technology.
204 ///
205 UINT32 VMX:1;
206 ///
207 /// [Bit 6] Safer Mode Extensions. A value of 1 indicates that the processor
208 /// supports this technology
209 ///
210 UINT32 SMX:1;
211 ///
212 /// [Bit 7] Enhanced Intel SpeedStep(R) technology. A value of 1 indicates
213 /// that the processor supports this technology
214 ///
215 UINT32 EIST:1;
216 ///
217 /// [Bit 8] Thermal Monitor 2. A value of 1 indicates whether the processor
218 /// supports this technology
219 ///
220 UINT32 TM2:1;
221 ///
222 /// [Bit 9] A value of 1 indicates the presence of the Supplemental Streaming
223 /// SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction
224 /// extensions are not present in the processor.
225 ///
226 UINT32 SSSE3:1;
227 ///
228 /// [Bit 10] L1 Context ID. A value of 1 indicates the L1 data cache mode
229 /// can be set to either adaptive mode or shared mode. A value of 0 indicates
230 /// this feature is not supported. See definition of the IA32_MISC_ENABLE MSR
231 /// Bit 24 (L1 Data Cache Context Mode) for details
232 ///
233 UINT32 CNXT_ID:1;
234 ///
235 /// [Bit 11] A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE
236 /// MSR for silicon debug
237 ///
238 UINT32 SDBG:1;
239 ///
240 /// [Bit 12] A value of 1 indicates the processor supports FMA (Fused Multiple
241 /// Add) extensions using YMM state.
242 ///
243 UINT32 FMA:1;
244 ///
245 /// [Bit 13] CMPXCHG16B Available. A value of 1 indicates that the feature
246 /// is available.
247 ///
248 UINT32 CMPXCHG16B:1;
249 ///
250 /// [Bit 14] xTPR Update Control. A value of 1 indicates that the processor
251 /// supports changing IA32_MISC_ENABLE[Bit 23].
252 ///
253 UINT32 xTPR_Update_Control:1;
254 ///
255 /// [Bit 15] Perfmon and Debug Capability: A value of 1 indicates the
256 /// processor supports the performance and debug feature indication MSR
257 /// IA32_PERF_CAPABILITIES.
258 ///
259 UINT32 PDCM:1;
260 UINT32 Reserved:1;
261 ///
262 /// [Bit 17] Process-context identifiers. A value of 1 indicates that the
263 /// processor supports PCIDs and that software may set CR4.PCIDE to 1.
264 ///
265 UINT32 PCID:1;
266 ///
267 /// [Bit 18] A value of 1 indicates the processor supports the ability to
268 /// prefetch data from a memory mapped device. Direct Cache Access.
269 ///
270 UINT32 DCA:1;
271 ///
272 /// [Bit 19] A value of 1 indicates that the processor supports SSE4.1.
273 ///
274 UINT32 SSE4_1:1;
275 ///
276 /// [Bit 20] A value of 1 indicates that the processor supports SSE4.2.
277 ///
278 UINT32 SSE4_2:1;
279 ///
280 /// [Bit 21] A value of 1 indicates that the processor supports x2APIC
281 /// feature.
282 ///
283 UINT32 x2APIC:1;
284 ///
285 /// [Bit 22] A value of 1 indicates that the processor supports MOVBE
286 /// instruction.
287 ///
288 UINT32 MOVBE:1;
289 ///
290 /// [Bit 23] A value of 1 indicates that the processor supports the POPCNT
291 /// instruction.
292 ///
293 UINT32 POPCNT:1;
294 ///
295 /// [Bit 24] A value of 1 indicates that the processor's local APIC timer
296 /// supports one-shot operation using a TSC deadline value.
297 ///
298 UINT32 TSC_Deadline:1;
299 ///
300 /// [Bit 25] A value of 1 indicates that the processor supports the AESNI
301 /// instruction extensions.
302 ///
303 UINT32 AESNI:1;
304 ///
305 /// [Bit 26] A value of 1 indicates that the processor supports the
306 /// XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV
307 /// instructions, and XCR0.
308 ///
309 UINT32 XSAVE:1;
310 ///
311 /// [Bit 27] A value of 1 indicates that the OS has set CR4.OSXSAVE[Bit 18]
312 /// to enable XSETBV/XGETBV instructions to access XCR0 and to support
313 /// processor extended state management using XSAVE/XRSTOR.
314 ///
315 UINT32 OSXSAVE:1;
316 ///
317 /// [Bit 28] A value of 1 indicates the processor supports the AVX instruction
318 /// extensions.
319 ///
320 UINT32 AVX:1;
321 ///
322 /// [Bit 29] A value of 1 indicates that processor supports 16-bit
323 /// floating-point conversion instructions.
324 ///
325 UINT32 F16C:1;
326 ///
327 /// [Bit 30] A value of 1 indicates that processor supports RDRAND instruction.
328 ///
329 UINT32 RDRAND:1;
330 ///
331 /// [Bit 31] Always returns 0.
332 ///
333 UINT32 NotUsed:1;
334 } Bits;
335 ///
336 /// All bit fields as a 32-bit value
337 ///
338 UINT32 Uint32;
339 } CPUID_VERSION_INFO_ECX;
340
341 /**
342 CPUID Version Information returned in EDX for CPUID leaf
343 #CPUID_VERSION_INFO.
344 **/
345 typedef union {
346 ///
347 /// Individual bit fields
348 ///
349 struct {
350 ///
351 /// [Bit 0] Floating Point Unit On-Chip. The processor contains an x87 FPU.
352 ///
353 UINT32 FPU:1;
354 ///
355 /// [Bit 1] Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements,
356 /// including CR4.VME for controlling the feature, CR4.PVI for protected
357 /// mode virtual interrupts, software interrupt indirection, expansion of
358 /// the TSS with the software indirection bitmap, and EFLAGS.VIF and
359 /// EFLAGS.VIP flags.
360 ///
361 UINT32 VME:1;
362 ///
363 /// [Bit 2] Debugging Extensions. Support for I/O breakpoints, including
364 /// CR4.DE for controlling the feature, and optional trapping of accesses to
365 /// DR4 and DR5.
366 ///
367 UINT32 DE:1;
368 ///
369 /// [Bit 3] Page Size Extension. Large pages of size 4 MByte are supported,
370 /// including CR4.PSE for controlling the feature, the defined dirty bit in
371 /// PDE (Page Directory Entries), optional reserved bit trapping in CR3,
372 /// PDEs, and PTEs.
373 ///
374 UINT32 PSE:1;
375 ///
376 /// [Bit 4] Time Stamp Counter. The RDTSC instruction is supported,
377 /// including CR4.TSD for controlling privilege.
378 ///
379 UINT32 TSC:1;
380 ///
381 /// [Bit 5] Model Specific Registers RDMSR and WRMSR Instructions. The
382 /// RDMSR and WRMSR instructions are supported. Some of the MSRs are
383 /// implementation dependent.
384 ///
385 UINT32 MSR:1;
386 ///
387 /// [Bit 6] Physical Address Extension. Physical addresses greater than 32
388 /// bits are supported: extended page table entry formats, an extra level in
389 /// the page translation tables is defined, 2-MByte pages are supported
390 /// instead of 4 Mbyte pages if PAE bit is 1.
391 ///
392 UINT32 PAE:1;
393 ///
394 /// [Bit 7] Machine Check Exception. Exception 18 is defined for Machine
395 /// Checks, including CR4.MCE for controlling the feature. This feature does
396 /// not define the model-specific implementations of machine-check error
397 /// logging, reporting, and processor shutdowns. Machine Check exception
398 /// handlers may have to depend on processor version to do model specific
399 /// processing of the exception, or test for the presence of the Machine
400 /// Check feature.
401 ///
402 UINT32 MCE:1;
403 ///
404 /// [Bit 8] CMPXCHG8B Instruction. The compare-and-exchange 8 bytes(64 bits)
405 /// instruction is supported (implicitly locked and atomic).
406 ///
407 UINT32 CX8:1;
408 ///
409 /// [Bit 9] APIC On-Chip. The processor contains an Advanced Programmable
410 /// Interrupt Controller (APIC), responding to memory mapped commands in the
411 /// physical address range FFFE0000H to FFFE0FFFH (by default - some
412 /// processors permit the APIC to be relocated).
413 ///
414 UINT32 APIC:1;
415 UINT32 Reserved1:1;
416 ///
417 /// [Bit 11] SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT
418 /// and associated MSRs are supported.
419 ///
420 UINT32 SEP:1;
421 ///
422 /// [Bit 12] Memory Type Range Registers. MTRRs are supported. The MTRRcap
423 /// MSR contains feature bits that describe what memory types are supported,
424 /// how many variable MTRRs are supported, and whether fixed MTRRs are
425 /// supported.
426 ///
427 UINT32 MTRR:1;
428 ///
429 /// [Bit 13] Page Global Bit. The global bit is supported in paging-structure
430 /// entries that map a page, indicating TLB entries that are common to
431 /// different processes and need not be flushed. The CR4.PGE bit controls
432 /// this feature.
433 ///
434 UINT32 PGE:1;
435 ///
436 /// [Bit 14] Machine Check Architecture. The Machine Check Architecture,
437 /// which provides a compatible mechanism for error reporting in P6 family,
438 /// Pentium 4, Intel Xeon processors, and future processors, is supported.
439 /// The MCG_CAP MSR contains feature bits describing how many banks of error
440 /// reporting MSRs are supported.
441 ///
442 UINT32 MCA:1;
443 ///
444 /// [Bit 15] Conditional Move Instructions. The conditional move instruction
445 /// CMOV is supported. In addition, if x87 FPU is present as indicated by the
446 /// CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported.
447 ///
448 UINT32 CMOV:1;
449 ///
450 /// [Bit 16] Page Attribute Table. Page Attribute Table is supported. This
451 /// feature augments the Memory Type Range Registers (MTRRs), allowing an
452 /// operating system to specify attributes of memory accessed through a
453 /// linear address on a 4KB granularity.
454 ///
455 UINT32 PAT:1;
456 ///
457 /// [Bit 17] 36-Bit Page Size Extension. 4-MByte pages addressing physical
458 /// memory beyond 4 GBytes are supported with 32-bit paging. This feature
459 /// indicates that upper bits of the physical address of a 4-MByte page are
460 /// encoded in bits 20:13 of the page-directory entry. Such physical
461 /// addresses are limited by MAXPHYADDR and may be up to 40 bits in size.
462 ///
463 UINT32 PSE_36:1;
464 ///
465 /// [Bit 18] Processor Serial Number. The processor supports the 96-bit
466 /// processor identification number feature and the feature is enabled.
467 ///
468 UINT32 PSN:1;
469 ///
470 /// [Bit 19] CLFLUSH Instruction. CLFLUSH Instruction is supported.
471 ///
472 UINT32 CLFSH:1;
473 UINT32 Reserved2:1;
474 ///
475 /// [Bit 21] Debug Store. The processor supports the ability to write debug
476 /// information into a memory resident buffer. This feature is used by the
477 /// branch trace store (BTS) and precise event-based sampling (PEBS)
478 /// facilities.
479 ///
480 UINT32 DS:1;
481 ///
482 /// [Bit 22] Thermal Monitor and Software Controlled Clock Facilities. The
483 /// processor implements internal MSRs that allow processor temperature to
484 /// be monitored and processor performance to be modulated in predefined
485 /// duty cycles under software control.
486 ///
487 UINT32 ACPI:1;
488 ///
489 /// [Bit 23] Intel MMX Technology. The processor supports the Intel MMX
490 /// technology.
491 ///
492 UINT32 MMX:1;
493 ///
494 /// [Bit 24] FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR
495 /// instructions are supported for fast save and restore of the floating
496 /// point context. Presence of this bit also indicates that CR4.OSFXSR is
497 /// available for an operating system to indicate that it supports the
498 /// FXSAVE and FXRSTOR instructions.
499 ///
500 UINT32 FXSR:1;
501 ///
502 /// [Bit 25] SSE. The processor supports the SSE extensions.
503 ///
504 UINT32 SSE:1;
505 ///
506 /// [Bit 26] SSE2. The processor supports the SSE2 extensions.
507 ///
508 UINT32 SSE2:1;
509 ///
510 /// [Bit 27] Self Snoop. The processor supports the management of
511 /// conflicting memory types by performing a snoop of its own cache
512 /// structure for transactions issued to the bus.
513 ///
514 UINT32 SS:1;
515 ///
516 /// [Bit 28] Max APIC IDs reserved field is Valid. A value of 0 for HTT
517 /// indicates there is only a single logical processor in the package and
518 /// software should assume only a single APIC ID is reserved. A value of 1
519 /// for HTT indicates the value in CPUID.1.EBX[23:16] (the Maximum number of
520 /// addressable IDs for logical processors in this package) is valid for the
521 /// package.
522 ///
523 UINT32 HTT:1;
524 ///
525 /// [Bit 29] Thermal Monitor. The processor implements the thermal monitor
526 /// automatic thermal control circuitry (TCC).
527 ///
528 UINT32 TM:1;
529 UINT32 Reserved3:1;
530 ///
531 /// [Bit 31] Pending Break Enable. The processor supports the use of the
532 /// FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is
533 /// asserted) to signal the processor that an interrupt is pending and that
534 /// the processor should return to normal operation to handle the interrupt.
535 /// Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability.
536 ///
537 UINT32 PBE:1;
538 } Bits;
539 ///
540 /// All bit fields as a 32-bit value
541 ///
542 UINT32 Uint32;
543 } CPUID_VERSION_INFO_EDX;
544
545
546 /**
547 CPUID Cache and TLB Information
548
549 @param EAX CPUID_CACHE_INFO (0x02)
550
551 @retval EAX Cache and TLB Information described by the type
552 CPUID_CACHE_INFO_CACHE_TLB.
553 CPUID_CACHE_INFO_CACHE_TLB.CacheDescriptor[0] always returns
554 0x01 and must be ignored. Only valid if
555 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
556 @retval EBX Cache and TLB Information described by the type
557 CPUID_CACHE_INFO_CACHE_TLB. Only valid if
558 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
559 @retval ECX Cache and TLB Information described by the type
560 CPUID_CACHE_INFO_CACHE_TLB. Only valid if
561 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
562 @retval EDX Cache and TLB Information described by the type
563 CPUID_CACHE_INFO_CACHE_TLB. Only valid if
564 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
565
566 <b>Example usage</b>
567 @code
568 CPUID_CACHE_INFO_CACHE_TLB Eax;
569 CPUID_CACHE_INFO_CACHE_TLB Ebx;
570 CPUID_CACHE_INFO_CACHE_TLB Ecx;
571 CPUID_CACHE_INFO_CACHE_TLB Edx;
572
573 AsmCpuid (CPUID_CACHE_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
574 @endcode
575
576 <b>Cache Descriptor values</b>
577 <table>
578 <tr><th>Value </th><th> Type </th><th> Description </th></tr>
579 <tr><td> 0x00 </td><td> General </td><td> Null descriptor, this byte contains no information</td></tr>
580 <tr><td> 0x01 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries</td></tr>
581 <tr><td> 0x02 </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, fully associative, 2 entries</td></tr>
582 <tr><td> 0x03 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 64 entries</td></tr>
583 <tr><td> 0x04 </td><td> TLB </td><td> Data TLB: 4 MByte pages, 4-way set associative, 8 entries</td></tr>
584 <tr><td> 0x05 </td><td> TLB </td><td> Data TLB1: 4 MByte pages, 4-way set associative, 32 entries</td></tr>
585 <tr><td> 0x06 </td><td> Cache </td><td> 1st-level instruction cache: 8 KBytes, 4-way set associative,
586 32 byte line size</td></tr>
587 <tr><td> 0x08 </td><td> Cache </td><td> 1st-level instruction cache: 16 KBytes, 4-way set associative,
588 32 byte line size</td></tr>
589 <tr><td> 0x09 </td><td> Cache </td><td> 1st-level instruction cache: 32KBytes, 4-way set associative,
590 64 byte line size</td></tr>
591 <tr><td> 0x0A </td><td> Cache </td><td> 1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size</td></tr>
592 <tr><td> 0x0B </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries</td></tr>
593 <tr><td> 0x0C </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size</td></tr>
594 <tr><td> 0x0D </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size</td></tr>
595 <tr><td> 0x0E </td><td> Cache </td><td> 1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size</td></tr>
596 <tr><td> 0x1D </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size</td></tr>
597 <tr><td> 0x21 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size</td></tr>
598 <tr><td> 0x22 </td><td> Cache </td><td> 3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size,
599 2 lines per sector</td></tr>
600 <tr><td> 0x23 </td><td> Cache </td><td> 3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size,
601 2 lines per sector</td></tr>
602 <tr><td> 0x24 </td><td> Cache </td><td> 2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size</td></tr>
603 <tr><td> 0x25 </td><td> Cache </td><td> 3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size,
604 2 lines per sector</td></tr>
605 <tr><td> 0x29 </td><td> Cache </td><td> 3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size,
606 2 lines per sector</td></tr>
607 <tr><td> 0x2C </td><td> Cache </td><td> 1st-level data cache: 32 KBytes, 8-way set associative,
608 64 byte line size</td></tr>
609 <tr><td> 0x30 </td><td> Cache </td><td> 1st-level instruction cache: 32 KBytes, 8-way set associative,
610 64 byte line size</td></tr>
611 <tr><td> 0x40 </td><td> Cache </td><td> No 2nd-level cache or, if processor contains a valid 2nd-level cache,
612 no 3rd-level cache</td></tr>
613 <tr><td> 0x41 </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size</td></tr>
614 <tr><td> 0x42 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size</td></tr>
615 <tr><td> 0x43 </td><td> Cache </td><td> 2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size</td></tr>
616 <tr><td> 0x44 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size</td></tr>
617 <tr><td> 0x45 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size</td></tr>
618 <tr><td> 0x46 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size</td></tr>
619 <tr><td> 0x47 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size</td></tr>
620 <tr><td> 0x48 </td><td> Cache </td><td> 2nd-level cache: 3MByte, 12-way set associative, 64 byte line size</td></tr>
621 <tr><td> 0x49 </td><td> Cache </td><td> 3rd-level cache: 4MB, 16-way set associative, 64-byte line size
622 (Intel Xeon processor MP, Family 0FH, Model 06H)<BR>
623 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>
624 <tr><td> 0x4A </td><td> Cache </td><td> 3rd-level cache: 6MByte, 12-way set associative, 64 byte line size</td></tr>
625 <tr><td> 0x4B </td><td> Cache </td><td> 3rd-level cache: 8MByte, 16-way set associative, 64 byte line size</td></tr>
626 <tr><td> 0x4C </td><td> Cache </td><td> 3rd-level cache: 12MByte, 12-way set associative, 64 byte line size</td></tr>
627 <tr><td> 0x4D </td><td> Cache </td><td> 3rd-level cache: 16MByte, 16-way set associative, 64 byte line size</td></tr>
628 <tr><td> 0x4E </td><td> Cache </td><td> 2nd-level cache: 6MByte, 24-way set associative, 64 byte line size</td></tr>
629 <tr><td> 0x4F </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 32 entries</td></tr>
630 <tr><td> 0x50 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries</td></tr>
631 <tr><td> 0x51 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries</td></tr>
632 <tr><td> 0x52 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries</td></tr>
633 <tr><td> 0x55 </td><td> TLB </td><td> Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries</td></tr>
634 <tr><td> 0x56 </td><td> TLB </td><td> Data TLB0: 4 MByte pages, 4-way set associative, 16 entries</td></tr>
635 <tr><td> 0x57 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, 4-way associative, 16 entries</td></tr>
636 <tr><td> 0x59 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, fully associative, 16 entries</td></tr>
637 <tr><td> 0x5A </td><td> TLB </td><td> Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries</td></tr>
638 <tr><td> 0x5B </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 64 entries</td></tr>
639 <tr><td> 0x5C </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,128 entries</td></tr>
640 <tr><td> 0x5D </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,256 entries</td></tr>
641 <tr><td> 0x60 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size</td></tr>
642 <tr><td> 0x61 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, fully associative, 48 entries</td></tr>
643 <tr><td> 0x63 </td><td> TLB </td><td> Data TLB: 1 GByte pages, 4-way set associative, 4 entries</td></tr>
644 <tr><td> 0x66 </td><td> Cache </td><td> 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size</td></tr>
645 <tr><td> 0x67 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size</td></tr>
646 <tr><td> 0x68 </td><td> Cache </td><td> 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size</td></tr>
647 <tr><td> 0x6A </td><td> Cache </td><td> uTLB: 4 KByte pages, 8-way set associative, 64 entries</td></tr>
648 <tr><td> 0x6B </td><td> Cache </td><td> DTLB: 4 KByte pages, 8-way set associative, 256 entries</td></tr>
649 <tr><td> 0x6C </td><td> Cache </td><td> DTLB: 2M/4M pages, 8-way set associative, 128 entries</td></tr>
650 <tr><td> 0x6D </td><td> Cache </td><td> DTLB: 1 GByte pages, fully associative, 16 entries</td></tr>
651 <tr><td> 0x70 </td><td> Cache </td><td> Trace cache: 12 K-uop, 8-way set associative</td></tr>
652 <tr><td> 0x71 </td><td> Cache </td><td> Trace cache: 16 K-uop, 8-way set associative</td></tr>
653 <tr><td> 0x72 </td><td> Cache </td><td> Trace cache: 32 K-uop, 8-way set associative</td></tr>
654 <tr><td> 0x76 </td><td> TLB </td><td> Instruction TLB: 2M/4M pages, fully associative, 8 entries</td></tr>
655 <tr><td> 0x78 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 64byte line size</td></tr>
656 <tr><td> 0x79 </td><td> Cache </td><td> 2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size,
657 2 lines per sector</td></tr>
658 <tr><td> 0x7A </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size,
659 2 lines per sector</td></tr>
660 <tr><td> 0x7B </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size,
661 2 lines per sector</td></tr>
662 <tr><td> 0x7C </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size,
663 2 lines per sector</td></tr>
664 <tr><td> 0x7D </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 64byte line size</td></tr>
665 <tr><td> 0x7F </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size</td></tr>
666 <tr><td> 0x80 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size</td></tr>
667 <tr><td> 0x82 </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size</td></tr>
668 <tr><td> 0x83 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size</td></tr>
669 <tr><td> 0x84 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size</td></tr>
670 <tr><td> 0x85 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size</td></tr>
671 <tr><td> 0x86 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>
672 <tr><td> 0x87 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>
673 <tr><td> 0xA0 </td><td> DTLB </td><td> DTLB: 4k pages, fully associative, 32 entries</td></tr>
674 <tr><td> 0xB0 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>
675 <tr><td> 0xB1 </td><td> TLB </td><td> Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries</td></tr>
676 <tr><td> 0xB2 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 4-way set associative, 64 entries</td></tr>
677 <tr><td> 0xB3 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>
678 <tr><td> 0xB4 </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 256 entries</td></tr>
679 <tr><td> 0xB5 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative, 64 entries</td></tr>
680 <tr><td> 0xB6 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative,
681 128 entries</td></tr>
682 <tr><td> 0xBA </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 64 entries</td></tr>
683 <tr><td> 0xC0 </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries</td></tr>
684 <tr><td> 0xC1 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative,
685 1024 entries</td></tr>
686 <tr><td> 0xC2 </td><td> DTLB </td><td> DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries</td></tr>
687 <tr><td> 0xC3 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative,
688 1536 entries. Also 1GBbyte pages, 4-way, 16 entries.</td></tr>
689 <tr><td> 0xCA </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries</td></tr>
690 <tr><td> 0xD0 </td><td> Cache </td><td> 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>
691 <tr><td> 0xD1 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size</td></tr>
692 <tr><td> 0xD2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size</td></tr>
693 <tr><td> 0xD6 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>
694 <tr><td> 0xD7 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size</td></tr>
695 <tr><td> 0xD8 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size</td></tr>
696 <tr><td> 0xDC </td><td> Cache </td><td> 3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size</td></tr>
697 <tr><td> 0xDD </td><td> Cache </td><td> 3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size</td></tr>
698 <tr><td> 0xDE </td><td> Cache </td><td> 3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size</td></tr>
699 <tr><td> 0xE2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size</td></tr>
700 <tr><td> 0xE3 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>
701 <tr><td> 0xE4 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size</td></tr>
702 <tr><td> 0xEA </td><td> Cache </td><td> 3rd-level cache: 12MByte, 24-way set associative, 64 byte line size</td></tr>
703 <tr><td> 0xEB </td><td> Cache </td><td> 3rd-level cache: 18MByte, 24-way set associative, 64 byte line size</td></tr>
704 <tr><td> 0xEC </td><td> Cache </td><td> 3rd-level cache: 24MByte, 24-way set associative, 64 byte line size</td></tr>
705 <tr><td> 0xF0 </td><td> Prefetch</td><td> 64-Byte prefetching</td></tr>
706 <tr><td> 0xF1 </td><td> Prefetch</td><td> 128-Byte prefetching</td></tr>
707 <tr><td> 0xFF </td><td> General </td><td> CPUID leaf 2 does not report cache descriptor information,
708 use CPUID leaf 4 to query cache parameters</td></tr>
709 </table>
710 **/
711 #define CPUID_CACHE_INFO 0x02
712
713 /**
714 CPUID Cache and TLB Information returned in EAX, EBX, ECX, and EDX for CPUID
715 leaf #CPUID_CACHE_INFO.
716 **/
717 typedef union {
718 ///
719 /// Individual bit fields
720 ///
721 struct {
722 UINT32 Reserved:31;
723 ///
724 /// [Bit 31] If 0, then the cache descriptor bytes in the register are valid.
725 /// if 1, then none of the cache descriptor bytes in the register are valid.
726 ///
727 UINT32 NotValid:1;
728 } Bits;
729 ///
730 /// Array of Cache and TLB descriptor bytes
731 ///
732 UINT8 CacheDescriptor[4];
733 ///
734 /// All bit fields as a 32-bit value
735 ///
736 UINT32 Uint32;
737 } CPUID_CACHE_INFO_CACHE_TLB;
738
739
740 /**
741 CPUID Processor Serial Number
742
743 Processor serial number (PSN) is not supported in the Pentium 4 processor
744 or later. On all models, use the PSN flag (returned using CPUID) to check
745 for PSN support before accessing the feature.
746
747 @param EAX CPUID_SERIAL_NUMBER (0x03)
748
749 @retval EAX Reserved.
750 @retval EBX Reserved.
751 @retval ECX Bits 31:0 of 96 bit processor serial number. (Available in
752 Pentium III processor only; otherwise, the value in this
753 register is reserved.)
754 @retval EDX Bits 63:32 of 96 bit processor serial number. (Available in
755 Pentium III processor only; otherwise, the value in this
756 register is reserved.)
757
758 <b>Example usage</b>
759 @code
760 UINT32 Ecx;
761 UINT32 Edx;
762
763 AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx);
764 @endcode
765 **/
766 #define CPUID_SERIAL_NUMBER 0x03
767
768
769 /**
770 CPUID Cache Parameters
771
772 @param EAX CPUID_CACHE_PARAMS (0x04)
773 @param ECX Cache Level. Valid values start at 0. Software can enumerate
774 the deterministic cache parameters for each level of the cache
775 hierarchy starting with an index value of 0, until the
776 parameters report the value associated with the CacheType
777 field in CPUID_CACHE_PARAMS_EAX is 0.
778
779 @retval EAX Returns cache type information described by the type
780 CPUID_CACHE_PARAMS_EAX.
781 @retval EBX Returns cache line and associativity information described by
782 the type CPUID_CACHE_PARAMS_EBX.
783 @retval ECX Returns the number of sets in the cache.
784 @retval EDX Returns cache WINVD/INVD behavior described by the type
785 CPUID_CACHE_PARAMS_EDX.
786
787 <b>Example usage</b>
788 @code
789 UINT32 CacheLevel;
790 CPUID_CACHE_PARAMS_EAX Eax;
791 CPUID_CACHE_PARAMS_EBX Ebx;
792 UINT32 Ecx;
793 CPUID_CACHE_PARAMS_EDX Edx;
794
795 CacheLevel = 0;
796 do {
797 AsmCpuidEx (
798 CPUID_CACHE_PARAMS, CacheLevel,
799 &Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32
800 );
801 CacheLevel++;
802 } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);
803 @endcode
804 **/
805 #define CPUID_CACHE_PARAMS 0x04
806
807 /**
808 CPUID Cache Parameters Information returned in EAX for CPUID leaf
809 #CPUID_CACHE_PARAMS.
810 **/
811 typedef union {
812 ///
813 /// Individual bit fields
814 ///
815 struct {
816 ///
817 /// [Bits 4:0] Cache type field. If #CPUID_CACHE_PARAMS_CACHE_TYPE_NULL,
818 /// then there is no information for the requested cache level.
819 ///
820 UINT32 CacheType:5;
821 ///
822 /// [Bits 7:5] Cache level (Starts at 1).
823 ///
824 UINT32 CacheLevel:3;
825 ///
826 /// [Bit 8] Self Initializing cache level (does not need SW initialization).
827 ///
828 UINT32 SelfInitializingCache:1;
829 ///
830 /// [Bit 9] Fully Associative cache.
831 ///
832 UINT32 FullyAssociativeCache:1;
833 ///
834 /// [Bits 13:10] Reserved.
835 ///
836 UINT32 Reserved:4;
837 ///
838 /// [Bits 25:14] Maximum number of addressable IDs for logical processors
839 /// sharing this cache.
840 ///
841 /// Add one to the return value to get the result.
842 /// The nearest power-of-2 integer that is not smaller than (1 + EAX[25:14])
843 /// is the number of unique initial APIC IDs reserved for addressing
844 /// different logical processors sharing this cache.
845 ///
846 UINT32 MaximumAddressableIdsForLogicalProcessors:12;
847 ///
848 /// [Bits 31:26] Maximum number of addressable IDs for processor cores in
849 /// the physical package.
850 ///
851 /// The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26])
852 /// is the number of unique Core_IDs reserved for addressing different
853 /// processor cores in a physical package. Core ID is a subset of bits of
854 /// the initial APIC ID.
855 /// The returned value is constant for valid initial values in ECX. Valid
856 /// ECX values start from 0.
857 ///
858 UINT32 MaximumAddressableIdsForProcessorCores:6;
859 } Bits;
860 ///
861 /// All bit fields as a 32-bit value
862 ///
863 UINT32 Uint32;
864 } CPUID_CACHE_PARAMS_EAX;
865
866 ///
867 /// @{ Define value for bit field CPUID_CACHE_PARAMS_EAX.CacheType
868 ///
869 #define CPUID_CACHE_PARAMS_CACHE_TYPE_NULL 0x00
870 #define CPUID_CACHE_PARAMS_CACHE_TYPE_DATA 0x01
871 #define CPUID_CACHE_PARAMS_CACHE_TYPE_INSTRUCTION 0x02
872 #define CPUID_CACHE_PARAMS_CACHE_TYPE_UNIFIED 0x03
873 ///
874 /// @}
875 ///
876
877 /**
878 CPUID Cache Parameters Information returned in EBX for CPUID leaf
879 #CPUID_CACHE_PARAMS.
880 **/
881 typedef union {
882 ///
883 /// Individual bit fields
884 ///
885 struct {
886 ///
887 /// [Bits 11:0] System Coherency Line Size. Add one to the return value to
888 /// get the result.
889 ///
890 UINT32 LineSize:12;
891 ///
892 /// [Bits 21:12] Physical Line Partitions. Add one to the return value to
893 /// get the result.
894 ///
895 UINT32 LinePartitions:10;
896 ///
897 /// [Bits 31:22] Ways of associativity. Add one to the return value to get
898 /// the result.
899 ///
900 UINT32 Ways:10;
901 } Bits;
902 ///
903 /// All bit fields as a 32-bit value
904 ///
905 UINT32 Uint32;
906 } CPUID_CACHE_PARAMS_EBX;
907
908 /**
909 CPUID Cache Parameters Information returned in EDX for CPUID leaf
910 #CPUID_CACHE_PARAMS.
911 **/
912 typedef union {
913 ///
914 /// Individual bit fields
915 ///
916 struct {
917 ///
918 /// [Bit 0] Write-Back Invalidate/Invalidate.
919 /// 0 = WBINVD/INVD from threads sharing this cache acts upon lower level
920 /// caches for threads sharing this cache.
921 /// 1 = WBINVD/INVD is not guaranteed to act upon lower level caches of
922 /// non-originating threads sharing this cache.
923 ///
924 UINT32 Invalidate:1;
925 ///
926 /// [Bit 1] Cache Inclusiveness.
927 /// 0 = Cache is not inclusive of lower cache levels.
928 /// 1 = Cache is inclusive of lower cache levels.
929 ///
930 UINT32 CacheInclusiveness:1;
931 ///
932 /// [Bit 2] Complex Cache Indexing.
933 /// 0 = Direct mapped cache.
934 /// 1 = A complex function is used to index the cache, potentially using all
935 /// address bits.
936 ///
937 UINT32 ComplexCacheIndexing:1;
938 UINT32 Reserved:29;
939 } Bits;
940 ///
941 /// All bit fields as a 32-bit value
942 ///
943 UINT32 Uint32;
944 } CPUID_CACHE_PARAMS_EDX;
945
946
947 /**
948 CPUID MONITOR/MWAIT Information
949
950 @param EAX CPUID_MONITOR_MWAIT (0x05)
951
952 @retval EAX Smallest monitor-line size in bytes described by the type
953 CPUID_MONITOR_MWAIT_EAX.
954 @retval EBX Largest monitor-line size in bytes described by the type
955 CPUID_MONITOR_MWAIT_EBX.
956 @retval ECX Enumeration of Monitor-Mwait extensions support described by
957 the type CPUID_MONITOR_MWAIT_ECX.
958 @retval EDX Sub C-states supported described by the type
959 CPUID_MONITOR_MWAIT_EDX.
960
961 <b>Example usage</b>
962 @code
963 CPUID_MONITOR_MWAIT_EAX Eax;
964 CPUID_MONITOR_MWAIT_EBX Ebx;
965 CPUID_MONITOR_MWAIT_ECX Ecx;
966 CPUID_MONITOR_MWAIT_EDX Edx;
967
968 AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
969 @endcode
970 **/
971 #define CPUID_MONITOR_MWAIT 0x05
972
973 /**
974 CPUID MONITOR/MWAIT Information returned in EAX for CPUID leaf
975 #CPUID_MONITOR_MWAIT.
976 **/
977 typedef union {
978 ///
979 /// Individual bit fields
980 ///
981 struct {
982 ///
983 /// [Bits 15:0] Smallest monitor-line size in bytes (default is processor's
984 /// monitor granularity).
985 ///
986 UINT32 SmallestMonitorLineSize:16;
987 UINT32 Reserved:16;
988 } Bits;
989 ///
990 /// All bit fields as a 32-bit value
991 ///
992 UINT32 Uint32;
993 } CPUID_MONITOR_MWAIT_EAX;
994
995 /**
996 CPUID MONITOR/MWAIT Information returned in EBX for CPUID leaf
997 #CPUID_MONITOR_MWAIT.
998 **/
999 typedef union {
1000 ///
1001 /// Individual bit fields
1002 ///
1003 struct {
1004 ///
1005 /// [Bits 15:0] Largest monitor-line size in bytes (default is processor's
1006 /// monitor granularity).
1007 ///
1008 UINT32 LargestMonitorLineSize:16;
1009 UINT32 Reserved:16;
1010 } Bits;
1011 ///
1012 /// All bit fields as a 32-bit value
1013 ///
1014 UINT32 Uint32;
1015 } CPUID_MONITOR_MWAIT_EBX;
1016
1017 /**
1018 CPUID MONITOR/MWAIT Information returned in ECX for CPUID leaf
1019 #CPUID_MONITOR_MWAIT.
1020 **/
1021 typedef union {
1022 ///
1023 /// Individual bit fields
1024 ///
1025 struct {
1026 ///
1027 /// [Bit 0] If 0, then only EAX and EBX are valid. If 1, then EAX, EBX, ECX,
1028 /// and EDX are valid.
1029 ///
1030 UINT32 ExtensionsSupported:1;
1031 ///
1032 /// [Bit 1] Supports treating interrupts as break-event for MWAIT, even when
1033 /// interrupts disabled.
1034 ///
1035 UINT32 InterruptAsBreak:1;
1036 UINT32 Reserved:30;
1037 } Bits;
1038 ///
1039 /// All bit fields as a 32-bit value
1040 ///
1041 UINT32 Uint32;
1042 } CPUID_MONITOR_MWAIT_ECX;
1043
1044 /**
1045 CPUID MONITOR/MWAIT Information returned in EDX for CPUID leaf
1046 #CPUID_MONITOR_MWAIT.
1047
1048 @note
1049 The definition of C0 through C7 states for MWAIT extension are
1050 processor-specific C-states, not ACPI C-states.
1051 **/
1052 typedef union {
1053 ///
1054 /// Individual bit fields
1055 ///
1056 struct {
1057 ///
1058 /// [Bits 3:0] Number of C0 sub C-states supported using MWAIT.
1059 ///
1060 UINT32 C0States:4;
1061 ///
1062 /// [Bits 7:4] Number of C1 sub C-states supported using MWAIT.
1063 ///
1064 UINT32 C1States:4;
1065 ///
1066 /// [Bits 11:8] Number of C2 sub C-states supported using MWAIT.
1067 ///
1068 UINT32 C2States:4;
1069 ///
1070 /// [Bits 15:12] Number of C3 sub C-states supported using MWAIT.
1071 ///
1072 UINT32 C3States:4;
1073 ///
1074 /// [Bits 19:16] Number of C4 sub C-states supported using MWAIT.
1075 ///
1076 UINT32 C4States:4;
1077 ///
1078 /// [Bits 23:20] Number of C5 sub C-states supported using MWAIT.
1079 ///
1080 UINT32 C5States:4;
1081 ///
1082 /// [Bits 27:24] Number of C6 sub C-states supported using MWAIT.
1083 ///
1084 UINT32 C6States:4;
1085 ///
1086 /// [Bits 31:28] Number of C7 sub C-states supported using MWAIT.
1087 ///
1088 UINT32 C7States:4;
1089 } Bits;
1090 ///
1091 /// All bit fields as a 32-bit value
1092 ///
1093 UINT32 Uint32;
1094 } CPUID_MONITOR_MWAIT_EDX;
1095
1096
1097 /**
1098 CPUID Thermal and Power Management
1099
1100 @param EAX CPUID_THERMAL_POWER_MANAGEMENT (0x06)
1101
1102 @retval EAX Thermal and power management features described by the type
1103 CPUID_THERMAL_POWER_MANAGEMENT_EAX.
1104 @retval EBX Number of Interrupt Thresholds in Digital Thermal Sensor
1105 described by the type CPUID_THERMAL_POWER_MANAGEMENT_EBX.
1106 @retval ECX Performance features described by the type
1107 CPUID_THERMAL_POWER_MANAGEMENT_ECX.
1108 @retval EDX Reserved.
1109
1110 <b>Example usage</b>
1111 @code
1112 CPUID_THERMAL_POWER_MANAGEMENT_EAX Eax;
1113 CPUID_THERMAL_POWER_MANAGEMENT_EBX Ebx;
1114 CPUID_THERMAL_POWER_MANAGEMENT_ECX Ecx;
1115
1116 AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
1117 @endcode
1118 **/
1119 #define CPUID_THERMAL_POWER_MANAGEMENT 0x06
1120
1121 /**
1122 CPUID Thermal and Power Management Information returned in EAX for CPUID leaf
1123 #CPUID_THERMAL_POWER_MANAGEMENT.
1124 **/
1125 typedef union {
1126 ///
1127 /// Individual bit fields
1128 ///
1129 struct {
1130 ///
1131 /// [Bit 0] Digital temperature sensor is supported if set.
1132 ///
1133 UINT32 DigitalTemperatureSensor:1;
1134 ///
1135 /// [Bit 1] Intel Turbo Boost Technology Available (see IA32_MISC_ENABLE[38]).
1136 ///
1137 UINT32 TurboBoostTechnology:1;
1138 ///
1139 /// [Bit 2] APIC-Timer-always-running feature is supported if set.
1140 ///
1141 UINT32 ARAT:1;
1142 UINT32 Reserved1:1;
1143 ///
1144 /// [Bit 4] Power limit notification controls are supported if set.
1145 ///
1146 UINT32 PLN:1;
1147 ///
1148 /// [Bit 5] Clock modulation duty cycle extension is supported if set.
1149 ///
1150 UINT32 ECMD:1;
1151 ///
1152 /// [Bit 6] Package thermal management is supported if set.
1153 ///
1154 UINT32 PTM:1;
1155 ///
1156 /// [Bit 7] HWP base registers (IA32_PM_ENABLE[Bit 0], IA32_HWP_CAPABILITIES,
1157 /// IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.
1158 ///
1159 UINT32 HWP:1;
1160 ///
1161 /// [Bit 8] IA32_HWP_INTERRUPT MSR is supported if set.
1162 ///
1163 UINT32 HWP_Notification:1;
1164 ///
1165 /// [Bit 9] IA32_HWP_REQUEST[Bits 41:32] is supported if set.
1166 ///
1167 UINT32 HWP_Activity_Window:1;
1168 ///
1169 /// [Bit 10] IA32_HWP_REQUEST[Bits 31:24] is supported if set.
1170 ///
1171 UINT32 HWP_Energy_Performance_Preference:1;
1172 ///
1173 /// [Bit 11] IA32_HWP_REQUEST_PKG MSR is supported if set.
1174 ///
1175 UINT32 HWP_Package_Level_Request:1;
1176 UINT32 Reserved2:1;
1177 ///
1178 /// [Bit 13] HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1,
1179 /// IA32_THREAD_STALL MSRs are supported if set.
1180 ///
1181 UINT32 HDC:1;
1182 UINT32 Reserved3:18;
1183 } Bits;
1184 ///
1185 /// All bit fields as a 32-bit value
1186 ///
1187 UINT32 Uint32;
1188 } CPUID_THERMAL_POWER_MANAGEMENT_EAX;
1189
1190 /**
1191 CPUID Thermal and Power Management Information returned in EBX for CPUID leaf
1192 #CPUID_THERMAL_POWER_MANAGEMENT.
1193 **/
1194 typedef union {
1195 ///
1196 /// Individual bit fields
1197 ///
1198 struct {
1199 ///
1200 /// {Bits 3:0] Number of Interrupt Thresholds in Digital Thermal Sensor.
1201 ///
1202 UINT32 InterruptThresholds:4;
1203 UINT32 Reserved:28;
1204 } Bits;
1205 ///
1206 /// All bit fields as a 32-bit value
1207 ///
1208 UINT32 Uint32;
1209 } CPUID_THERMAL_POWER_MANAGEMENT_EBX;
1210
1211 /**
1212 CPUID Thermal and Power Management Information returned in ECX for CPUID leaf
1213 #CPUID_THERMAL_POWER_MANAGEMENT.
1214 **/
1215 typedef union {
1216 ///
1217 /// Individual bit fields
1218 ///
1219 struct {
1220 ///
1221 /// [Bit 0] Hardware Coordination Feedback Capability (Presence of IA32_MPERF
1222 /// and IA32_APERF). The capability to provide a measure of delivered
1223 /// processor performance (since last reset of the counters), as a percentage
1224 /// of the expected processor performance when running at the TSC frequency.
1225 ///
1226 UINT32 HardwareCoordinationFeedback:1;
1227 UINT32 Reserved1:2;
1228 ///
1229 /// [Bit 3] If this bit is set, then the processor supports performance-energy
1230 /// bias preference and the architectural MSR called IA32_ENERGY_PERF_BIAS
1231 /// (1B0H).
1232 ///
1233 UINT32 PerformanceEnergyBias:1;
1234 UINT32 Reserved2:28;
1235 } Bits;
1236 ///
1237 /// All bit fields as a 32-bit value
1238 ///
1239 UINT32 Uint32;
1240 } CPUID_THERMAL_POWER_MANAGEMENT_ECX;
1241
1242
1243 /**
1244 CPUID Structured Extended Feature Flags Enumeration
1245
1246 @param EAX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07)
1247 @param ECX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO (0x00).
1248
1249 @note
1250 If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf
1251 index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX.
1252
1253 @retval EAX The maximum input value for ECX to retrieve sub-leaf information.
1254 @retval EBX Structured Extended Feature Flags described by the type
1255 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX.
1256 @retval EBX Structured Extended Feature Flags described by the type
1257 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX.
1258 @retval EDX Reserved.
1259
1260 <b>Example usage</b>
1261 @code
1262 UINT32 Eax;
1263 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;
1264 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx;
1265 UINT32 SubLeaf;
1266
1267 AsmCpuidEx (
1268 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
1269 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
1270 &Eax, NULL, NULL, NULL
1271 );
1272 for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) {
1273 AsmCpuidEx (
1274 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
1275 SubLeaf,
1276 NULL, &Ebx.Uint32, &Ecx.Uint32, NULL
1277 );
1278 }
1279 @endcode
1280 **/
1281 #define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07
1282
1283 ///
1284 /// CPUID Structured Extended Feature Flags Enumeration sub-leaf
1285 ///
1286 #define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO 0x00
1287
1288 /**
1289 CPUID Structured Extended Feature Flags Enumeration in EBX for CPUID leaf
1290 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf
1291 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.
1292 **/
1293 typedef union {
1294 ///
1295 /// Individual bit fields
1296 ///
1297 struct {
1298 ///
1299 /// [Bit 0] Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.
1300 ///
1301 UINT32 FSGSBASE:1;
1302 ///
1303 /// [Bit 1] IA32_TSC_ADJUST MSR is supported if 1.
1304 ///
1305 UINT32 IA32_TSC_ADJUST:1;
1306 ///
1307 /// [Bit 2] Intel SGX is supported if 1. See section 37.7 "DISCOVERING SUPPORT
1308 /// FOR INTEL(R) SGX AND ENABLING ENCLAVE INSTRUCTIONS".
1309 ///
1310 UINT32 SGX:1;
1311 ///
1312 /// [Bit 3] If 1 indicates the processor supports the first group of advanced
1313 /// bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT)
1314 ///
1315 UINT32 BMI1:1;
1316 ///
1317 /// [Bit 4] Hardware Lock Elision
1318 ///
1319 UINT32 HLE:1;
1320 ///
1321 /// [Bit 5] If 1 indicates the processor supports AVX2 instruction extensions.
1322 ///
1323 UINT32 AVX2:1;
1324 ///
1325 /// [Bit 6] x87 FPU Data Pointer updated only on x87 exceptions if 1.
1326 ///
1327 UINT32 FDP_EXCPTN_ONLY:1;
1328 ///
1329 /// [Bit 7] Supports Supervisor-Mode Execution Prevention if 1.
1330 ///
1331 UINT32 SMEP:1;
1332 ///
1333 /// [Bit 8] If 1 indicates the processor supports the second group of
1334 /// advanced bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX,
1335 /// SARX, SHLX, SHRX)
1336 ///
1337 UINT32 BMI2:1;
1338 ///
1339 /// [Bit 9] Supports Enhanced REP MOVSB/STOSB if 1.
1340 ///
1341 UINT32 EnhancedRepMovsbStosb:1;
1342 ///
1343 /// [Bit 10] If 1, supports INVPCID instruction for system software that
1344 /// manages process-context identifiers.
1345 ///
1346 UINT32 INVPCID:1;
1347 ///
1348 /// [Bit 11] Restricted Transactional Memory
1349 ///
1350 UINT32 RTM:1;
1351 ///
1352 /// [Bit 12] Supports Platform Quality of Service Monitoring (PQM)
1353 /// capability if 1.
1354 ///
1355 UINT32 PQM:1;
1356 ///
1357 /// [Bit 13] Deprecates FPU CS and FPU DS values if 1.
1358 ///
1359 UINT32 DeprecateFpuCsDs:1;
1360 ///
1361 /// [Bit 14] Supports Intel(R) Memory Protection Extensions if 1.
1362 ///
1363 UINT32 MPX:1;
1364 ///
1365 /// [Bit 15] Supports Platform Quality of Service Enforcement (PQE)
1366 /// capability if 1.
1367 ///
1368 UINT32 PQE:1;
1369 UINT32 Reserved2:2;
1370 ///
1371 /// [Bit 18] If 1 indicates the processor supports the RDSEED instruction.
1372 ///
1373 UINT32 RDSEED:1;
1374 ///
1375 /// [Bit 19] If 1 indicates the processor supports the ADCX and ADOX
1376 /// instructions.
1377 ///
1378 UINT32 ADX:1;
1379 ///
1380 /// [Bit 20] Supports Supervisor-Mode Access Prevention (and the CLAC/STAC
1381 /// instructions) if 1.
1382 ///
1383 UINT32 SMAP:1;
1384 UINT32 Reserved3:2;
1385 ///
1386 /// [Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction.
1387 ///
1388 UINT32 CLFLUSHOPT:1;
1389 UINT32 Reserved4:1;
1390 ///
1391 /// [Bit 25] If 1 indicates the processor supports the Intel Processor Trace
1392 /// extensions.
1393 ///
1394 UINT32 IntelProcessorTrace:1;
1395 UINT32 Reserved5:6;
1396 } Bits;
1397 ///
1398 /// All bit fields as a 32-bit value
1399 ///
1400 UINT32 Uint32;
1401 } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX;
1402
1403 /**
1404 CPUID Structured Extended Feature Flags Enumeration in ECX for CPUID leaf
1405 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf
1406 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.
1407 **/
1408 typedef union {
1409 ///
1410 /// Individual bit fields
1411 ///
1412 struct {
1413 ///
1414 /// [Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction.
1415 ///
1416 UINT32 PREFETCHWT1:1;
1417 UINT32 Reserved1:2;
1418 ///
1419 /// [Bit 3] Supports protection keys for user-mode pages if 1.
1420 ///
1421 UINT32 PKU:1;
1422 ///
1423 /// [Bit 4] If 1, OS has set CR4.PKE to enable protection keys (and the
1424 /// RDPKRU/WRPKRU instructions).
1425 ///
1426 UINT32 OSPKE:1;
1427 UINT32 Reserved2:27;
1428 } Bits;
1429 ///
1430 /// All bit fields as a 32-bit value
1431 ///
1432 UINT32 Uint32;
1433 } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX;
1434
1435
1436 /**
1437 CPUID Direct Cache Access Information
1438
1439 @param EAX CPUID_DIRECT_CACHE_ACCESS_INFO (0x09)
1440
1441 @retval EAX Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1F8H).
1442 @retval EBX Reserved.
1443 @retval ECX Reserved.
1444 @retval EDX Reserved.
1445
1446 <b>Example usage</b>
1447 @code
1448 UINT32 Eax;
1449
1450 AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL);
1451 @endcode
1452 **/
1453 #define CPUID_DIRECT_CACHE_ACCESS_INFO 0x09
1454
1455
1456 /**
1457 CPUID Architectural Performance Monitoring
1458
1459 @param EAX CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING (0x0A)
1460
1461 @retval EAX Architectural Performance Monitoring information described by
1462 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX.
1463 @retval EBX Architectural Performance Monitoring information described by
1464 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX.
1465 @retval ECX Reserved.
1466 @retval EDX Architectural Performance Monitoring information described by
1467 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX.
1468
1469 <b>Example usage</b>
1470 @code
1471 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX Eax;
1472 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX Ebx;
1473 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX Edx;
1474
1475 AsmCpuid (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING, &Eax.Uint32, &Ebx.Uint32, NULL, &Edx.Uint32);
1476 @endcode
1477 **/
1478 #define CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING 0x0A
1479
1480 /**
1481 CPUID Architectural Performance Monitoring EAX for CPUID leaf
1482 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
1483 **/
1484 typedef union {
1485 ///
1486 /// Individual bit fields
1487 ///
1488 struct {
1489 ///
1490 /// [Bit 7:0] Version ID of architectural performance monitoring.
1491 ///
1492 UINT32 ArchPerfMonVerID:8;
1493 ///
1494 /// [Bits 15:8] Number of general-purpose performance monitoring counter
1495 /// per logical processor.
1496 ///
1497 /// IA32_PERFEVTSELx MSRs start at address 186H and occupy a contiguous
1498 /// block of MSR address space. Each performance event select register is
1499 /// paired with a corresponding performance counter in the 0C1H address
1500 /// block.
1501 ///
1502 UINT32 PerformanceMonitorCounters:8;
1503 ///
1504 /// [Bits 23:16] Bit width of general-purpose, performance monitoring counter.
1505 ///
1506 /// The bit width of an IA32_PMCx MSR. This the number of valid bits for
1507 /// read operation. On write operations, the lower-order 32 bits of the MSR
1508 /// may be written with any value, and the high-order bits are sign-extended
1509 /// from the value of bit 31.
1510 ///
1511 UINT32 PerformanceMonitorCounterWidth:8;
1512 ///
1513 /// [Bits 31:24] Length of EBX bit vector to enumerate architectural
1514 /// performance monitoring events.
1515 ///
1516 UINT32 EbxBitVectorLength:8;
1517 } Bits;
1518 ///
1519 /// All bit fields as a 32-bit value
1520 ///
1521 UINT32 Uint32;
1522 } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX;
1523
1524 /**
1525 CPUID Architectural Performance Monitoring EBX for CPUID leaf
1526 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
1527 **/
1528 typedef union {
1529 ///
1530 /// Individual bit fields
1531 ///
1532 struct {
1533 ///
1534 /// [Bit 0] Core cycle event not available if 1.
1535 ///
1536 UINT32 UnhaltedCoreCycles:1;
1537 ///
1538 /// [Bit 1] Instruction retired event not available if 1.
1539 ///
1540 UINT32 InstructionsRetired:1;
1541 ///
1542 /// [Bit 2] Reference cycles event not available if 1.
1543 ///
1544 UINT32 UnhaltedReferenceCycles:1;
1545 ///
1546 /// [Bit 3] Last-level cache reference event not available if 1.
1547 ///
1548 UINT32 LastLevelCacheReferences:1;
1549 ///
1550 /// [Bit 4] Last-level cache misses event not available if 1.
1551 ///
1552 UINT32 LastLevelCacheMisses:1;
1553 ///
1554 /// [Bit 5] Branch instruction retired event not available if 1.
1555 ///
1556 UINT32 BranchInstructionsRetired:1;
1557 ///
1558 /// [Bit 6] Branch mispredict retired event not available if 1.
1559 ///
1560 UINT32 AllBranchMispredictRetired:1;
1561 UINT32 Reserved:25;
1562 } Bits;
1563 ///
1564 /// All bit fields as a 32-bit value
1565 ///
1566 UINT32 Uint32;
1567 } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX;
1568
1569 /**
1570 CPUID Architectural Performance Monitoring EDX for CPUID leaf
1571 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
1572 **/
1573 typedef union {
1574 ///
1575 /// Individual bit fields
1576 ///
1577 struct {
1578 ///
1579 /// [Bits 4:0] Number of fixed-function performance counters
1580 /// (if Version ID > 1).
1581 ///
1582 UINT32 FixedFunctionPerformanceCounters:5;
1583 ///
1584 /// [Bits 12:5] Bit width of fixed-function performance counters
1585 /// (if Version ID > 1).
1586 ///
1587 UINT32 FixedFunctionPerformanceCounterWidth:8;
1588 UINT32 Reserved:19;
1589 } Bits;
1590 ///
1591 /// All bit fields as a 32-bit value
1592 ///
1593 UINT32 Uint32;
1594 } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX;
1595
1596
1597 /**
1598 CPUID Extended Topology Information
1599
1600 @note
1601 Most of Leaf 0BH output depends on the initial value in ECX. The EDX output
1602 of leaf 0BH is always valid and does not vary with input value in ECX. Output
1603 value in ECX[7:0] always equals input value in ECX[7:0]. For sub-leaves that
1604 return an invalid level-type of 0 in ECX[15:8]; EAX and EBX will return 0. If
1605 an input value n in ECX returns the invalid level-type of 0 in ECX[15:8],
1606 other input values with ECX > n also return 0 in ECX[15:8].
1607
1608 @param EAX CPUID_EXTENDED_TOPOLOGY (0x0B)
1609 @param ECX Level number
1610
1611 @retval EAX Extended topology information described by the type
1612 CPUID_EXTENDED_TOPOLOGY_EAX.
1613 @retval EBX Extended topology information described by the type
1614 CPUID_EXTENDED_TOPOLOGY_EBX.
1615 @retval ECX Extended topology information described by the type
1616 CPUID_EXTENDED_TOPOLOGY_ECX.
1617 @retval EDX x2APIC ID the current logical processor.
1618
1619 <b>Example usage</b>
1620 @code
1621 CPUID_EXTENDED_TOPOLOGY_EAX Eax;
1622 CPUID_EXTENDED_TOPOLOGY_EBX Ebx;
1623 CPUID_EXTENDED_TOPOLOGY_ECX Ecx;
1624 UINT32 Edx;
1625 UINT32 LevelNumber;
1626
1627 LevelNumber = 0;
1628 do {
1629 AsmCpuidEx (
1630 CPUID_EXTENDED_TOPOLOGY, LevelNumber,
1631 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx
1632 );
1633 LevelNumber++;
1634 } while (Eax.Bits.ApicIdShift != 0);
1635 @endcode
1636 **/
1637 #define CPUID_EXTENDED_TOPOLOGY 0x0B
1638
1639 /**
1640 CPUID Extended Topology Information EAX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
1641 **/
1642 typedef union {
1643 ///
1644 /// Individual bit fields
1645 ///
1646 struct {
1647 ///
1648 /// [Bits 4:0] Number of bits to shift right on x2APIC ID to get a unique
1649 /// topology ID of the next level type. All logical processors with the
1650 /// same next level ID share current level.
1651 ///
1652 /// @note
1653 /// Software should use this field (EAX[4:0]) to enumerate processor
1654 /// topology of the system.
1655 ///
1656 UINT32 ApicIdShift:5;
1657 UINT32 Reserved:27;
1658 } Bits;
1659 ///
1660 /// All bit fields as a 32-bit value
1661 ///
1662 UINT32 Uint32;
1663 } CPUID_EXTENDED_TOPOLOGY_EAX;
1664
1665 /**
1666 CPUID Extended Topology Information EBX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
1667 **/
1668 typedef union {
1669 ///
1670 /// Individual bit fields
1671 ///
1672 struct {
1673 ///
1674 /// [Bits 15:0] Number of logical processors at this level type. The number
1675 /// reflects configuration as shipped by Intel.
1676 ///
1677 /// @note
1678 /// Software must not use EBX[15:0] to enumerate processor topology of the
1679 /// system. This value in this field (EBX[15:0]) is only intended for
1680 /// display/diagnostic purposes. The actual number of logical processors
1681 /// available to BIOS/OS/Applications may be different from the value of
1682 /// EBX[15:0], depending on software and platform hardware configurations.
1683 ///
1684 UINT32 LogicalProcessors:16;
1685 UINT32 Reserved:16;
1686 } Bits;
1687 ///
1688 /// All bit fields as a 32-bit value
1689 ///
1690 UINT32 Uint32;
1691 } CPUID_EXTENDED_TOPOLOGY_EBX;
1692
1693 /**
1694 CPUID Extended Topology Information ECX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
1695 **/
1696 typedef union {
1697 ///
1698 /// Individual bit fields
1699 ///
1700 struct {
1701 ///
1702 /// [Bits 7:0] Level number. Same value in ECX input.
1703 ///
1704 UINT32 LevelNumber:8;
1705 ///
1706 /// [Bits 15:8] Level type.
1707 ///
1708 /// @note
1709 /// The value of the "level type" field is not related to level numbers in
1710 /// any way, higher "level type" values do not mean higher levels.
1711 ///
1712 UINT32 LevelType:8;
1713 UINT32 Reserved:16;
1714 } Bits;
1715 ///
1716 /// All bit fields as a 32-bit value
1717 ///
1718 UINT32 Uint32;
1719 } CPUID_EXTENDED_TOPOLOGY_ECX;
1720
1721 ///
1722 /// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType
1723 ///
1724 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x00
1725 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x01
1726 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x02
1727 ///
1728 /// @}
1729 ///
1730
1731
1732 /**
1733 CPUID Extended State Information
1734
1735 @param EAX CPUID_EXTENDED_STATE (0x0D)
1736 @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00).
1737 CPUID_EXTENDED_STATE_SUB_LEAF (0x01).
1738 CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02).
1739 Sub leafs 2..n based on supported bits in XCR0 or IA32_XSS_MSR.
1740 **/
1741 #define CPUID_EXTENDED_STATE 0x0D
1742
1743 /**
1744 CPUID Extended State Information Main Leaf
1745
1746 @param EAX CPUID_EXTENDED_STATE (0x0D)
1747 @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00)
1748
1749 @retval EAX Reports the supported bits of the lower 32 bits of XCR0. XCR0[n]
1750 can be set to 1 only if EAX[n] is 1. The format of the extended
1751 state main leaf is described by the type
1752 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX.
1753 @retval EBX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save
1754 area) required by enabled features in XCR0. May be different than
1755 ECX if some features at the end of the XSAVE save area are not
1756 enabled.
1757 @retval ECX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save
1758 area) of the XSAVE/XRSTOR save area required by all supported
1759 features in the processor, i.e all the valid bit fields in XCR0.
1760 @retval EDX Reports the supported bits of the upper 32 bits of XCR0.
1761 XCR0[n+32] can be set to 1 only if EDX[n] is 1.
1762
1763 <b>Example usage</b>
1764 @code
1765 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax;
1766 UINT32 Ebx;
1767 UINT32 Ecx;
1768 UINT32 Edx;
1769
1770 AsmCpuidEx (
1771 CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF,
1772 &Eax.Uint32, &Ebx, &Ecx, &Edx
1773 );
1774 @endcode
1775 **/
1776 #define CPUID_EXTENDED_STATE_MAIN_LEAF 0x00
1777
1778 /**
1779 CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,
1780 sub-leaf #CPUID_EXTENDED_STATE_MAIN_LEAF.
1781 **/
1782 typedef union {
1783 ///
1784 /// Individual bit fields
1785 ///
1786 struct {
1787 ///
1788 /// [Bit 0] x87 state.
1789 ///
1790 UINT32 x87:1;
1791 ///
1792 /// [Bit 1] SSE state.
1793 ///
1794 UINT32 SSE:1;
1795 ///
1796 /// [Bit 2] AVX state.
1797 ///
1798 UINT32 AVX:1;
1799 ///
1800 /// [Bits 4:3] MPX state.
1801 ///
1802 UINT32 MPX:2;
1803 ///
1804 /// [Bits 7:5] AVX-512 state.
1805 ///
1806 UINT32 AVX_512:3;
1807 ///
1808 /// [Bit 8] Used for IA32_XSS.
1809 ///
1810 UINT32 IA32_XSS:1;
1811 ///
1812 /// [Bit 9] PKRU state.
1813 ///
1814 UINT32 PKRU:1;
1815 UINT32 Reserved:22;
1816 } Bits;
1817 ///
1818 /// All bit fields as a 32-bit value
1819 ///
1820 UINT32 Uint32;
1821 } CPUID_EXTENDED_STATE_MAIN_LEAF_EAX;
1822
1823 /**
1824 CPUID Extended State Information Sub Leaf
1825
1826 @param EAX CPUID_EXTENDED_STATE (0x0D)
1827 @param ECX CPUID_EXTENDED_STATE_SUB_LEAF (0x01)
1828
1829 @retval EAX The format of the extended state sub-leaf is described by the
1830 type CPUID_EXTENDED_STATE_SUB_LEAF_EAX.
1831 @retval EBX The size in bytes of the XSAVE area containing all states
1832 enabled by XCRO | IA32_XSS.
1833 @retval ECX The format of the extended state sub-leaf is described by the
1834 type CPUID_EXTENDED_STATE_SUB_LEAF_ECX.
1835 @retval EDX Reports the supported bits of the upper 32 bits of the
1836 IA32_XSS MSR. IA32_XSS[n+32] can be set to 1 only if EDX[n] is 1.
1837
1838 <b>Example usage</b>
1839 @code
1840 CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax;
1841 UINT32 Ebx;
1842 CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx;
1843 UINT32 Edx;
1844
1845 AsmCpuidEx (
1846 CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF,
1847 &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx
1848 );
1849 @endcode
1850 **/
1851 #define CPUID_EXTENDED_STATE_SUB_LEAF 0x01
1852
1853 /**
1854 CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,
1855 sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.
1856 **/
1857 typedef union {
1858 ///
1859 /// Individual bit fields
1860 ///
1861 struct {
1862 ///
1863 /// [Bit 0] XSAVEOPT is available.
1864 ///
1865 UINT32 XSAVEOPT:1;
1866 ///
1867 /// [Bit 1] Supports XSAVEC and the compacted form of XRSTOR if set.
1868 ///
1869 UINT32 XSAVEC:1;
1870 ///
1871 /// [Bit 2] Supports XGETBV with ECX = 1 if set.
1872 ///
1873 UINT32 XGETBV:1;
1874 ///
1875 /// [Bit 3] Supports XSAVES/XRSTORS and IA32_XSS if set.
1876 ///
1877 UINT32 XSAVES:1;
1878 UINT32 Reserved:28;
1879 } Bits;
1880 ///
1881 /// All bit fields as a 32-bit value
1882 ///
1883 UINT32 Uint32;
1884 } CPUID_EXTENDED_STATE_SUB_LEAF_EAX;
1885
1886 /**
1887 CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,
1888 sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.
1889 **/
1890 typedef union {
1891 ///
1892 /// Individual bit fields
1893 ///
1894 struct {
1895 ///
1896 /// [Bits 7:0] Used for XCR0.
1897 ///
1898 UINT32 XCR0:1;
1899 ///
1900 /// [Bit 8] PT STate.
1901 ///
1902 UINT32 PT:1;
1903 ///
1904 /// [Bit 9] Used for XCR0.
1905 ///
1906 UINT32 XCR0_1:1;
1907 UINT32 Reserved:22;
1908 } Bits;
1909 ///
1910 /// All bit fields as a 32-bit value
1911 ///
1912 UINT32 Uint32;
1913 } CPUID_EXTENDED_STATE_SUB_LEAF_ECX;
1914
1915 /**
1916 CPUID Extended State Information Size and Offset Sub Leaf
1917
1918 @note
1919 Leaf 0DH output depends on the initial value in ECX.
1920 Each sub-leaf index (starting at position 2) is supported if it corresponds to
1921 a supported bit in either the XCR0 register or the IA32_XSS MSR.
1922 If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf
1923 n (0 <= n <= 31) is invalid if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1
1924 returns 0 in ECX[n]. Sub-leaf n (32 <= n <= 63) is invalid if sub-leaf 0
1925 returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32].
1926
1927 @param EAX CPUID_EXTENDED_STATE (0x0D)
1928 @param ECX CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02). Sub leafs 2..n based
1929 on supported bits in XCR0 or IA32_XSS_MSR.
1930
1931 @retval EAX The size in bytes (from the offset specified in EBX) of the save
1932 area for an extended state feature associated with a valid
1933 sub-leaf index, n.
1934 @retval EBX The offset in bytes of this extended state component's save area
1935 from the beginning of the XSAVE/XRSTOR area. This field reports
1936 0 if the sub-leaf index, n, does not map to a valid bit in the
1937 XCR0 register.
1938 @retval ECX The format of the extended state components's save area as
1939 described by the type CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX.
1940 This field reports 0 if the sub-leaf index, n, is invalid.
1941 @retval EDX This field reports 0 if the sub-leaf index, n, is invalid;
1942 otherwise it is reserved.
1943
1944 <b>Example usage</b>
1945 @code
1946 UINT32 Eax;
1947 UINT32 Ebx;
1948 CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX Ecx;
1949 UINT32 Edx;
1950 UINTN SubLeaf;
1951
1952 for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) {
1953 AsmCpuidEx (
1954 CPUID_EXTENDED_STATE, SubLeaf,
1955 &Eax, &Ebx, &Ecx.Uint32, &Edx
1956 );
1957 }
1958 @endcode
1959 **/
1960 #define CPUID_EXTENDED_STATE_SIZE_OFFSET 0x02
1961
1962 /**
1963 CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,
1964 sub-leaf #CPUID_EXTENDED_STATE_SIZE_OFFSET.
1965 **/
1966 typedef union {
1967 ///
1968 /// Individual bit fields
1969 ///
1970 struct {
1971 ///
1972 /// [Bit 0] Is set if the bit n (corresponding to the sub-leaf index) is
1973 /// supported in the IA32_XSS MSR; it is clear if bit n is instead supported
1974 /// in XCR0.
1975 ///
1976 UINT32 XSS:1;
1977 ///
1978 /// [Bit 1] is set if, when the compacted format of an XSAVE area is used,
1979 /// this extended state component located on the next 64-byte boundary
1980 /// following the preceding state component (otherwise, it is located
1981 /// immediately following the preceding state component).
1982 ///
1983 UINT32 Compacted:1;
1984 UINT32 Reserved:30;
1985 } Bits;
1986 ///
1987 /// All bit fields as a 32-bit value
1988 ///
1989 UINT32 Uint32;
1990 } CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX;
1991
1992
1993 /**
1994 CPUID Platform QoS Monitoring Information
1995
1996 @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F)
1997 @param ECX CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF (0x00).
1998 CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF (0x01).
1999
2000 **/
2001 #define CPUID_PLATFORM_QOS_MONITORING 0x0F
2002
2003 /**
2004 CPUID Platform QoS Monitoring Information Enumeration Sub-leaf
2005
2006 @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F)
2007 @param ECX CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF (0x00)
2008
2009 @retval EAX Reserved.
2010 @retval EBX Maximum range (zero-based) of RMID within this physical
2011 processor of all types.
2012 @retval ECX Reserved.
2013 @retval EDX L3 Cache QoS Monitoring Information Enumeration described by the
2014 type CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX.
2015
2016 <b>Example usage</b>
2017 @code
2018 UINT32 Ebx;
2019 CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;
2020
2021 AsmCpuidEx (
2022 CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF,
2023 NULL, &Ebx, NULL, &Edx.Uint32
2024 );
2025 @endcode
2026 **/
2027 #define CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF 0x00
2028
2029 /**
2030 CPUID Platform QoS Monitoring Information EDX for CPUID leaf
2031 #CPUID_PLATFORM_QOS_MONITORING, sub-leaf
2032 #CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF.
2033 **/
2034 typedef union {
2035 ///
2036 /// Individual bit fields
2037 ///
2038 struct {
2039 UINT32 Reserved1:1;
2040 ///
2041 /// [Bit 1] Supports L3 Cache QoS Monitoring if 1.
2042 ///
2043 UINT32 L3CacheQosEnforcement:1;
2044 UINT32 Reserved2:30;
2045 } Bits;
2046 ///
2047 /// All bit fields as a 32-bit value
2048 ///
2049 UINT32 Uint32;
2050 } CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX;
2051
2052 /**
2053 CPUID Platform QoS Monitoring Information Capability Sub-leaf
2054
2055 @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F)
2056 @param ECX CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF (0x01)
2057
2058 @retval EAX Reserved.
2059 @retval EBX Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes).
2060 @retval ECX Maximum range (zero-based) of RMID of this resource type.
2061 @retval EDX L3 Cache QoS Monitoring Capability information described by the
2062 type CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX.
2063
2064 <b>Example usage</b>
2065 @code
2066 UINT32 Ebx;
2067 UINT32 Ecx;
2068 CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX Edx;
2069
2070 AsmCpuidEx (
2071 CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF,
2072 NULL, &Ebx, &Ecx, &Edx.Uint32
2073 );
2074 @endcode
2075 **/
2076 #define CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF 0x01
2077
2078 /**
2079 CPUID Platform QoS Monitoring Information Capability EDX for CPUID leaf
2080 #CPUID_PLATFORM_QOS_MONITORING, sub-leaf
2081 #CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF.
2082 **/
2083 typedef union {
2084 ///
2085 /// Individual bit fields
2086 ///
2087 struct {
2088 ///
2089 /// [Bit 0] Supports L3 occupancy monitoring if 1.
2090 ///
2091 UINT32 L3CacheOccupancyMonitoring:1;
2092 UINT32 Reserved:31;
2093 } Bits;
2094 ///
2095 /// All bit fields as a 32-bit value
2096 ///
2097 UINT32 Uint32;
2098 } CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX;
2099
2100
2101 /**
2102 CPUID Platform QoS Enforcement Information
2103
2104 @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10).
2105 @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF (0x00).
2106 CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF (0x01).
2107 Additional sub leafs 1..n based in RESID from sub leaf 0x00.
2108 **/
2109 #define CPUID_PLATFORM_QOS_ENFORCEMENT 0x10
2110
2111 /**
2112 CPUID Platform QoS Enforcement Information
2113
2114 @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10)
2115 @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF (0x00).
2116
2117 @retval EAX Reserved.
2118 @retval EBX L3 Cache QoS Enforcement information described by the
2119 type CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX.
2120 @retval ECX Reserved.
2121 @retval EDX Reserved.
2122
2123 <b>Example usage</b>
2124 @code
2125 CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX Ebx;
2126
2127 AsmCpuidEx (
2128 CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF,
2129 NULL, &Ebx.Uint32, NULL, NULL
2130 );
2131 @endcode
2132 **/
2133 #define CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF 0x00
2134
2135 /**
2136 CPUID Platform QoS Enforcement Information EBX for CPUID leaf
2137 #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf
2138 #CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF.
2139 **/
2140 typedef union {
2141 ///
2142 /// Individual bit fields
2143 ///
2144 struct {
2145 UINT32 Reserved1:1;
2146 ///
2147 /// [Bit 1] Supports L3 Cache QoS Enforcement if 1.
2148 ///
2149 UINT32 L3CacheQosEnforcement:1;
2150 UINT32 Reserved2:30;
2151 } Bits;
2152 ///
2153 /// All bit fields as a 32-bit value
2154 ///
2155 UINT32 Uint32;
2156 } CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX;
2157
2158
2159 /**
2160 CPUID Platform QoS Enforcement Information
2161
2162 @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10)
2163 @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF (0x00)
2164 Additional sub leafs 1..n based in RESID from sub leaf 0x00.
2165
2166 @retval EAX RESID L3 Cache3 QoS Enforcement information described by the
2167 type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX.
2168 @retval EBX Bit-granular map of isolation/contention of allocation units.
2169 @retval ECX RESID L3 Cache3 QoS Enforcement information described by the
2170 type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX.
2171 @retval EDX RESID L3 Cache3 QoS Enforcement information described by the
2172 type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX.
2173
2174 <b>Example usage</b>
2175 @code
2176 CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX Eax;
2177 UINT32 Ebx;
2178 CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX Ecx;
2179 CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX Edx;
2180
2181 AsmCpuidEx (
2182 CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF,
2183 &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32
2184 );
2185 @endcode
2186 **/
2187 #define CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF 0x01
2188
2189 /**
2190 CPUID Platform QoS Enforcement Information EAX for CPUID leaf
2191 #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf
2192 #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.
2193 **/
2194 typedef union {
2195 ///
2196 /// Individual bit fields
2197 ///
2198 struct {
2199 ///
2200 /// [Bits 3:0] Length of the capacity bit mask for the corresponding ResID.
2201 ///
2202 UINT32 CapacityLength:4;
2203 UINT32 Reserved:28;
2204 } Bits;
2205 ///
2206 /// All bit fields as a 32-bit value
2207 ///
2208 UINT32 Uint32;
2209 } CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX;
2210
2211 /**
2212 CPUID Platform QoS Enforcement Information ECX for CPUID leaf
2213 #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf
2214 #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.
2215 **/
2216 typedef union {
2217 ///
2218 /// Individual bit fields
2219 ///
2220 struct {
2221 UINT32 Reserved1:1;
2222 ///
2223 /// [Bit 1] Updates of COS should be infrequent if 1.
2224 ///
2225 UINT32 CosUpdatesInfrequent:1;
2226 ///
2227 /// [Bit 2] Code and Data Prioritization Technology supported if 1.
2228 ///
2229 UINT32 CodeDataPrioritization:1;
2230 UINT32 Reserved2:29;
2231 } Bits;
2232 ///
2233 /// All bit fields as a 32-bit value
2234 ///
2235 UINT32 Uint32;
2236 } CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX;
2237
2238 /**
2239 CPUID Platform QoS Enforcement Information EDX for CPUID leaf
2240 #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf
2241 #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.
2242 **/
2243 typedef union {
2244 ///
2245 /// Individual bit fields
2246 ///
2247 struct {
2248 ///
2249 /// [Bits 15:0] Highest COS number supported for this ResID.
2250 ///
2251 UINT32 HighestCosNumber:16;
2252 UINT32 Reserved:16;
2253 } Bits;
2254 ///
2255 /// All bit fields as a 32-bit value
2256 ///
2257 UINT32 Uint32;
2258 } CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX;
2259
2260
2261 /**
2262 Intel SGX resource capability and configuration.
2263 See Section 37.7.2 "Intel(R) SGX Resource Enumeration Leaves".
2264
2265 If CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor also supports querying
2266 CPUID with EAX=12H on Intel SGX resource capability and configuration.
2267
2268 @param EAX CPUID_INTEL_SGX (0x12)
2269 @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00).
2270 CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01).
2271 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02).
2272 Sub leafs 2..n based on the sub-leaf-type encoding (returned in EAX[3:0])
2273 until the sub-leaf type is invalid.
2274
2275 **/
2276 #define CPUID_INTEL_SGX 0x12
2277
2278 /**
2279 Sub-Leaf 0 Enumeration of Intel SGX Capabilities.
2280 Enumerates Intel SGX capability, including enclave instruction opcode support.
2281
2282 @param EAX CPUID_INTEL_SGX (0x12)
2283 @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00)
2284
2285 @retval EAX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is
2286 described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX.
2287 @retval EBX MISCSELECT: Reports the bit vector of supported extended features
2288 that can be written to the MISC region of the SSA.
2289 @retval ECX Reserved.
2290 @retval EDX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is
2291 described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX.
2292
2293 <b>Example usage</b>
2294 @code
2295 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX Eax;
2296 UINT32 Ebx;
2297 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx;
2298
2299 AsmCpuidEx (
2300 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,
2301 &Eax.Uint32, &Ebx, NULL, &Edx.Uint32
2302 );
2303 @endcode
2304 **/
2305 #define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF 0x00
2306
2307 /**
2308 Sub-Leaf 0 Enumeration of Intel SGX Capabilities EAX for CPUID leaf #CPUID_INTEL_SGX,
2309 sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.
2310 **/
2311 typedef union {
2312 ///
2313 /// Individual bit fields
2314 ///
2315 struct {
2316 ///
2317 /// [Bit 0] If 1, indicates leaf functions of SGX1 instruction are supported.
2318 ///
2319 UINT32 SGX1:1;
2320 ///
2321 /// [Bit 1] If 1, indicates leaf functions of SGX2 instruction are supported.
2322 ///
2323 UINT32 SGX2:1;
2324 UINT32 Reserved:30;
2325 } Bits;
2326 ///
2327 /// All bit fields as a 32-bit value
2328 ///
2329 UINT32 Uint32;
2330 } CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX;
2331
2332 /**
2333 Sub-Leaf 0 Enumeration of Intel SGX Capabilities EDX for CPUID leaf #CPUID_INTEL_SGX,
2334 sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.
2335 **/
2336 typedef union {
2337 ///
2338 /// Individual bit fields
2339 ///
2340 struct {
2341 ///
2342 /// [Bit 7:0] The maximum supported enclave size is 2^(EDX[7:0]) bytes
2343 /// when not in 64-bit mode.
2344 ///
2345 UINT32 MaxEnclaveSize_Not64:8;
2346 ///
2347 /// [Bit 15:8] The maximum supported enclave size is 2^(EDX[15:8]) bytes
2348 /// when operating in 64-bit mode.
2349 ///
2350 UINT32 MaxEnclaveSize_64:8;
2351 UINT32 Reserved:16;
2352 } Bits;
2353 ///
2354 /// All bit fields as a 32-bit value
2355 ///
2356 UINT32 Uint32;
2357 } CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX;
2358
2359
2360 /**
2361 Sub-Leaf 1 Enumeration of Intel SGX Capabilities.
2362 Enumerates Intel SGX capability of processor state configuration and enclave
2363 configuration in the SECS structure.
2364
2365 @param EAX CPUID_INTEL_SGX (0x12)
2366 @param ECX CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01)
2367
2368 @retval EAX Report the valid bits of SECS.ATTRIBUTES[31:0] that software can
2369 set with ECREATE. SECS.ATTRIBUTES[n] can be set to 1 using ECREATE
2370 only if EAX[n] is 1, where n < 32.
2371 @retval EBX Report the valid bits of SECS.ATTRIBUTES[63:32] that software can
2372 set with ECREATE. SECS.ATTRIBUTES[n+32] can be set to 1 using ECREATE
2373 only if EBX[n] is 1, where n < 32.
2374 @retval ECX Report the valid bits of SECS.ATTRIBUTES[95:64] that software can
2375 set with ECREATE. SECS.ATTRIBUTES[n+64] can be set to 1 using ECREATE
2376 only if ECX[n] is 1, where n < 32.
2377 @retval EDX Report the valid bits of SECS.ATTRIBUTES[127:96] that software can
2378 set with ECREATE. SECS.ATTRIBUTES[n+96] can be set to 1 using ECREATE
2379 only if EDX[n] is 1, where n < 32.
2380
2381 <b>Example usage</b>
2382 @code
2383 UINT32 Eax;
2384 UINT32 Ebx;
2385 UINT32 Ecx;
2386 UINT32 Edx;
2387
2388 AsmCpuidEx (
2389 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,
2390 &Eax, &Ebx, &Ecx, &Edx
2391 );
2392 @endcode
2393 **/
2394 #define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF 0x01
2395
2396
2397 /**
2398 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources.
2399 Enumerates available EPC resources.
2400
2401 @param EAX CPUID_INTEL_SGX (0x12)
2402 @param ECX CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02)
2403
2404 @retval EAX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
2405 Resources is described by the type
2406 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX.
2407 @retval EBX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
2408 Resources is described by the type
2409 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX.
2410 @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
2411 Resources is described by the type
2412 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX.
2413 @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
2414 Resources is described by the type
2415 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX.
2416
2417 <b>Example usage</b>
2418 @code
2419 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX Eax;
2420 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX Ebx;
2421 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX Ecx;
2422 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX Edx;
2423
2424 AsmCpuidEx (
2425 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF,
2426 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
2427 );
2428 @endcode
2429 **/
2430 #define CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF 0x02
2431
2432 /**
2433 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EAX for CPUID
2434 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
2435 **/
2436 typedef union {
2437 ///
2438 /// Individual bit fields
2439 ///
2440 struct {
2441 ///
2442 /// [Bit 3:0] Sub-leaf-type encoding.
2443 /// 0000b: This sub-leaf is invalid, EBX:EAX and EDX:ECX report 0.
2444 /// 0001b: This sub-leaf provides information on the Enclave Page Cache (EPC)
2445 /// in EBX:EAX and EDX:ECX.
2446 /// All other encoding are reserved.
2447 ///
2448 UINT32 SubLeafType:4;
2449 UINT32 Reserved:8;
2450 ///
2451 /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the physical address of
2452 /// the base of the EPC section.
2453 ///
2454 UINT32 LowAddressOfEpcSection:20;
2455 } Bits;
2456 ///
2457 /// All bit fields as a 32-bit value
2458 ///
2459 UINT32 Uint32;
2460 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX;
2461
2462 /**
2463 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EBX for CPUID
2464 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
2465 **/
2466 typedef union {
2467 ///
2468 /// Individual bit fields
2469 ///
2470 struct {
2471 ///
2472 /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the physical address of
2473 /// the base of the EPC section.
2474 ///
2475 UINT32 HighAddressOfEpcSection:20;
2476 UINT32 Reserved:12;
2477 } Bits;
2478 ///
2479 /// All bit fields as a 32-bit value
2480 ///
2481 UINT32 Uint32;
2482 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX;
2483
2484 /**
2485 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources ECX for CPUID
2486 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
2487 **/
2488 typedef union {
2489 ///
2490 /// Individual bit fields
2491 ///
2492 struct {
2493 ///
2494 /// [Bit 3:0] The EPC section encoding.
2495 /// 0000b: Not valid.
2496 /// 0001b: The EPC section is confidentiality, integrity and replay protected.
2497 /// All other encoding are reserved.
2498 ///
2499 UINT32 EpcSection:4;
2500 UINT32 Reserved:8;
2501 ///
2502 /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the size of the
2503 /// corresponding EPC section within the Processor Reserved Memory.
2504 ///
2505 UINT32 LowSizeOfEpcSection:20;
2506 } Bits;
2507 ///
2508 /// All bit fields as a 32-bit value
2509 ///
2510 UINT32 Uint32;
2511 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX;
2512
2513 /**
2514 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EDX for CPUID
2515 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
2516 **/
2517 typedef union {
2518 ///
2519 /// Individual bit fields
2520 ///
2521 struct {
2522 ///
2523 /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the size of the
2524 /// corresponding EPC section within the Processor Reserved Memory.
2525 ///
2526 UINT32 HighSizeOfEpcSection:20;
2527 UINT32 Reserved:12;
2528 } Bits;
2529 ///
2530 /// All bit fields as a 32-bit value
2531 ///
2532 UINT32 Uint32;
2533 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX;
2534
2535
2536 /**
2537 CPUID Intel Processor Trace Information
2538
2539 @param EAX CPUID_INTEL_PROCESSOR_TRACE (0x14)
2540 @param ECX CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF (0x00).
2541 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01).
2542
2543 **/
2544 #define CPUID_INTEL_PROCESSOR_TRACE 0x14
2545
2546 /**
2547 CPUID Intel Processor Trace Information Main Leaf
2548
2549 @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)
2550 @param ECX CPUID_INTEL_PROCEDSSOR_TRACE_MAIN_LEAF (0x00)
2551
2552 @retval EAX Reports the maximum sub-leaf supported in leaf 14H.
2553 @retval EBX Returns Intel processor trace information described by the
2554 type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX.
2555 @retval ECX Returns Intel processor trace information described by the
2556 type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX.
2557 @retval EDX Reserved.
2558
2559 <b>Example usage</b>
2560 @code
2561 UINT32 Eax;
2562 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Ebx;
2563 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx;
2564
2565 AsmCpuidEx (
2566 CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,
2567 &Eax, &Ebx.Uint32, &Ecx.Uint32, NULL
2568 );
2569 @endcode
2570 **/
2571 #define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF 0x00
2572
2573 /**
2574 CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
2575 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.
2576 **/
2577 typedef union {
2578 ///
2579 /// Individual bit fields
2580 ///
2581 struct {
2582 ///
2583 /// [Bit 0] If 1, Indicates that IA32_RTIT_CTL.CR3Filter can be set to 1,
2584 /// and that IA32_RTIT_CR3_MATCH MSR can be accessed.
2585 ///
2586 UINT32 Cr3Filter:1;
2587 ///
2588 /// [Bit 1] If 1, Indicates support of Configurable PSB and Cycle-Accurate
2589 /// Mode.
2590 ///
2591 UINT32 ConfigurablePsb:1;
2592 ///
2593 /// [Bit 2] If 1, Indicates support of IP Filtering, TraceStop filtering,
2594 /// and preservation of Intel PT MSRs across warm reset.
2595 ///
2596 UINT32 IpTraceStopFiltering:1;
2597 ///
2598 /// [Bit 3] If 1, Indicates support of MTC timing packet and suppression of
2599 /// COFI-based packets.
2600 ///
2601 UINT32 Mtc:1;
2602 UINT32 Reserved:28;
2603 } Bits;
2604 ///
2605 /// All bit fields as a 32-bit value
2606 ///
2607 UINT32 Uint32;
2608 } CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX;
2609
2610 /**
2611 CPUID Intel Processor Trace ECX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
2612 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.
2613 **/
2614 typedef union {
2615 ///
2616 /// Individual bit fields
2617 ///
2618 struct {
2619 ///
2620 /// [Bit 0] If 1, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence
2621 /// utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and
2622 /// IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.
2623 ///
2624 UINT32 RTIT:1;
2625 ///
2626 /// [Bit 1] If 1, ToPA tables can hold any number of output entries, up to
2627 /// the maximum allowed by the MaskOrTableOffset field of
2628 /// IA32_RTIT_OUTPUT_MASK_PTRS.
2629 ///
2630 UINT32 ToPA:1;
2631 ///
2632 /// [Bit 2] If 1, Indicates support of Single-Range Output scheme.
2633 ///
2634 UINT32 SingleRangeOutput:1;
2635 ///
2636 /// [Bit 3] If 1, Indicates support of output to Trace Transport subsystem.
2637 ///
2638 UINT32 TraceTransportSubsystem:1;
2639 UINT32 Reserved:27;
2640 ///
2641 /// [Bit 31] If 1, Generated packets which contain IP payloads have LIP
2642 /// values, which include the CS base component.
2643 ///
2644 UINT32 LIP:1;
2645 } Bits;
2646 ///
2647 /// All bit fields as a 32-bit value
2648 ///
2649 UINT32 Uint32;
2650 } CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX;
2651
2652
2653 /**
2654 CPUID Intel Processor Trace Information Sub-leaf
2655
2656 @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)
2657 @param ECX CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01)
2658
2659 @retval EAX Returns Intel processor trace information described by the
2660 type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX.
2661 @retval EBX Returns Intel processor trace information described by the
2662 type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX.
2663 @retval ECX Reserved.
2664 @retval EDX Reserved.
2665
2666 <b>Example usage</b>
2667 @code
2668 UINT32 MaximumSubLeaf;
2669 UINT32 SubLeaf;
2670 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX Eax;
2671 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX Ebx;
2672
2673 AsmCpuidEx (
2674 CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,
2675 &MaximumSubLeaf, NULL, NULL, NULL
2676 );
2677
2678 for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) {
2679 AsmCpuidEx (
2680 CPUID_INTEL_PROCESSOR_TRACE, SubLeaf,
2681 &Eax.Uint32, &Ebx.Uint32, NULL, NULL
2682 );
2683 }
2684 @endcode
2685 **/
2686 #define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF 0x01
2687
2688 /**
2689 CPUID Intel Processor Trace EAX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
2690 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.
2691 **/
2692 typedef union {
2693 ///
2694 /// Individual bit fields
2695 ///
2696 struct {
2697 ///
2698 /// [Bits 2:0] Number of configurable Address Ranges for filtering.
2699 ///
2700 UINT32 ConfigurableAddressRanges:3;
2701 UINT32 Reserved:13;
2702 ///
2703 /// [Bits 31:16] Bitmap of supported MTC period encodings
2704 ///
2705 UINT32 MtcPeriodEncodings:16;
2706
2707 } Bits;
2708 ///
2709 /// All bit fields as a 32-bit value
2710 ///
2711 UINT32 Uint32;
2712 } CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX;
2713
2714 /**
2715 CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
2716 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.
2717 **/
2718 typedef union {
2719 ///
2720 /// Individual bit fields
2721 ///
2722 struct {
2723 ///
2724 /// [Bits 15:0] Bitmap of supported Cycle Threshold value encodings.
2725 ///
2726 UINT32 CycleThresholdEncodings:16;
2727 ///
2728 /// [Bits 31:16] Bitmap of supported Configurable PSB frequency encodings.
2729 ///
2730 UINT32 PsbFrequencyEncodings:16;
2731
2732 } Bits;
2733 ///
2734 /// All bit fields as a 32-bit value
2735 ///
2736 UINT32 Uint32;
2737 } CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX;
2738
2739
2740 /**
2741 CPUID Time Stamp Counter Information
2742
2743 @note
2744 If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated.
2745 EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core
2746 crystal clock frequency.
2747 "TSC frequency" = "core crystal clock frequency" * EBX/EAX.
2748 The core crystal clock may differ from the reference clock, bus clock, or core
2749 clock frequencies.
2750
2751 @param EAX CPUID_TIME_STAMP_COUNTER (0x15)
2752
2753 @retval EAX An unsigned integer which is the denominator of the
2754 TSC/"core crystal clock" ratio
2755 @retval EBX An unsigned integer which is the numerator of the
2756 TSC/"core crystal clock" ratio.
2757 @retval ECX Reserved.
2758 @retval EDX Reserved.
2759
2760 <b>Example usage</b>
2761 @code
2762 UINT32 Eax;
2763 UINT32 Ebx;
2764
2765 AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, NULL, NULL);
2766 @endcode
2767 **/
2768 #define CPUID_TIME_STAMP_COUNTER 0x15
2769
2770
2771 /**
2772 CPUID Processor Frequency Information
2773
2774 @note
2775 Data is returned from this interface in accordance with the processor's
2776 specification and does not reflect actual values. Suitable use of this data
2777 includes the display of processor information in like manner to the processor
2778 brand string and for determining the appropriate range to use when displaying
2779 processor information e.g. frequency history graphs. The returned information
2780 should not be used for any other purpose as the returned information does not
2781 accurately correlate to information / counters returned by other processor
2782 interfaces. While a processor may support the Processor Frequency Information
2783 leaf, fields that return a value of zero are not supported.
2784
2785 @param EAX CPUID_TIME_STAMP_COUNTER (0x16)
2786
2787 @retval EAX Returns processor base frequency information described by the
2788 type CPUID_PROCESSOR_FREQUENCY_EAX.
2789 @retval EBX Returns maximum frequency information described by the type
2790 CPUID_PROCESSOR_FREQUENCY_EBX.
2791 @retval ECX Returns bus frequency information described by the type
2792 CPUID_PROCESSOR_FREQUENCY_ECX.
2793 @retval EDX Reserved.
2794
2795 <b>Example usage</b>
2796 @code
2797 CPUID_PROCESSOR_FREQUENCY_EAX Eax;
2798 CPUID_PROCESSOR_FREQUENCY_EBX Ebx;
2799 CPUID_PROCESSOR_FREQUENCY_ECX Ecx;
2800
2801 AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
2802 @endcode
2803 **/
2804 #define CPUID_PROCESSOR_FREQUENCY 0x16
2805
2806 /**
2807 CPUID Processor Frequency Information EAX for CPUID leaf
2808 #CPUID_PROCESSOR_FREQUENCY.
2809 **/
2810 typedef union {
2811 ///
2812 /// Individual bit fields
2813 ///
2814 struct {
2815 ///
2816 /// [Bits 15:0] Processor Base Frequency (in MHz).
2817 ///
2818 UINT32 ProcessorBaseFrequency:16;
2819 UINT32 Reserved:16;
2820 } Bits;
2821 ///
2822 /// All bit fields as a 32-bit value
2823 ///
2824 UINT32 Uint32;
2825 } CPUID_PROCESSOR_FREQUENCY_EAX;
2826
2827 /**
2828 CPUID Processor Frequency Information EBX for CPUID leaf
2829 #CPUID_PROCESSOR_FREQUENCY.
2830 **/
2831 typedef union {
2832 ///
2833 /// Individual bit fields
2834 ///
2835 struct {
2836 ///
2837 /// [Bits 15:0] Maximum Frequency (in MHz).
2838 ///
2839 UINT32 MaximumFrequency:16;
2840 UINT32 Reserved:16;
2841 } Bits;
2842 ///
2843 /// All bit fields as a 32-bit value
2844 ///
2845 UINT32 Uint32;
2846 } CPUID_PROCESSOR_FREQUENCY_EBX;
2847
2848 /**
2849 CPUID Processor Frequency Information ECX for CPUID leaf
2850 #CPUID_PROCESSOR_FREQUENCY.
2851 **/
2852 typedef union {
2853 ///
2854 /// Individual bit fields
2855 ///
2856 struct {
2857 ///
2858 /// [Bits 15:0] Bus (Reference) Frequency (in MHz).
2859 ///
2860 UINT32 BusFrequency:16;
2861 UINT32 Reserved:16;
2862 } Bits;
2863 ///
2864 /// All bit fields as a 32-bit value
2865 ///
2866 UINT32 Uint32;
2867 } CPUID_PROCESSOR_FREQUENCY_ECX;
2868
2869
2870 /**
2871 CPUID SoC Vendor Information
2872
2873 @param EAX CPUID_SOC_VENDOR (0x17)
2874 @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00)
2875 CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)
2876 CPUID_SOC_VENDOR_BRAND_STRING1 (0x02)
2877 CPUID_SOC_VENDOR_BRAND_STRING1 (0x03)
2878
2879 @note
2880 Leaf 17H output depends on the initial value in ECX. SOC Vendor Brand String
2881 is a UTF-8 encoded string padded with trailing bytes of 00H. The complete SOC
2882 Vendor Brand String is constructed by concatenating in ascending order of
2883 EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3.
2884
2885 **/
2886 #define CPUID_SOC_VENDOR 0x17
2887
2888 /**
2889 CPUID SoC Vendor Information
2890
2891 @param EAX CPUID_SOC_VENDOR (0x17)
2892 @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00)
2893
2894 @retval EAX MaxSOCID_Index. Reports the maximum input value of supported
2895 sub-leaf in leaf 17H.
2896 @retval EBX Returns SoC Vendor information described by the type
2897 CPUID_SOC_VENDOR_MAIN_LEAF_EBX.
2898 @retval ECX Project ID. A unique number an SOC vendor assigns to its SOC
2899 projects.
2900 @retval EDX Stepping ID. A unique number within an SOC project that an SOC
2901 vendor assigns.
2902
2903 <b>Example usage</b>
2904 @code
2905 UINT32 Eax;
2906 CPUID_SOC_VENDOR_MAIN_LEAF_EBX Ebx;
2907 UINT32 Ecx;
2908 UINT32 Edx;
2909
2910 AsmCpuidEx (
2911 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF,
2912 &Eax, &Ebx.Uint32, &Ecx, &Edx
2913 );
2914 @endcode
2915 **/
2916 #define CPUID_SOC_VENDOR_MAIN_LEAF 0x00
2917
2918 /**
2919 CPUID SoC Vendor Information EBX for CPUID leaf #CPUID_SOC_VENDOR sub-leaf
2920 #CPUID_SOC_VENDOR_MAIN_LEAF.
2921 **/
2922 typedef union {
2923 ///
2924 /// Individual bit fields
2925 ///
2926 struct {
2927 ///
2928 /// [Bits 15:0] SOC Vendor ID.
2929 ///
2930 UINT32 SocVendorId:16;
2931 ///
2932 /// [Bit 16] If 1, the SOC Vendor ID field is assigned via an industry
2933 /// standard enumeration scheme. Otherwise, the SOC Vendor ID field is
2934 /// assigned by Intel.
2935 ///
2936 UINT32 IsVendorScheme:1;
2937 UINT32 Reserved:15;
2938 } Bits;
2939 ///
2940 /// All bit fields as a 32-bit value
2941 ///
2942 UINT32 Uint32;
2943 } CPUID_SOC_VENDOR_MAIN_LEAF_EBX;
2944
2945 /**
2946 CPUID SoC Vendor Information
2947
2948 @param EAX CPUID_SOC_VENDOR (0x17)
2949 @param ECX CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)
2950
2951 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type
2952 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
2953 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type
2954 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
2955 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type
2956 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
2957 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type
2958 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
2959
2960 <b>Example usage</b>
2961 @code
2962 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;
2963 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;
2964 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;
2965 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;
2966
2967 AsmCpuidEx (
2968 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1,
2969 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
2970 );
2971 @endcode
2972 **/
2973 #define CPUID_SOC_VENDOR_BRAND_STRING1 0x01
2974
2975 /**
2976 CPUID SoC Vendor Brand String for CPUID leafs #CPUID_SOC_VENDOR_BRAND_STRING1,
2977 #CPUID_SOC_VENDOR_BRAND_STRING2, and #CPUID_SOC_VENDOR_BRAND_STRING3.
2978 **/
2979 typedef union {
2980 ///
2981 /// 4 UTF-8 characters of Soc Vendor Brand String
2982 ///
2983 CHAR8 BrandString[4];
2984 ///
2985 /// All fields as a 32-bit value
2986 ///
2987 UINT32 Uint32;
2988 } CPUID_SOC_VENDOR_BRAND_STRING_DATA;
2989
2990 /**
2991 CPUID SoC Vendor Information
2992
2993 @param EAX CPUID_SOC_VENDOR (0x17)
2994 @param ECX CPUID_SOC_VENDOR_BRAND_STRING2 (0x02)
2995
2996 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type
2997 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
2998 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type
2999 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3000 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type
3001 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3002 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type
3003 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3004
3005 <b>Example usage</b>
3006 @code
3007 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;
3008 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;
3009 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;
3010 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;
3011
3012 AsmCpuidEx (
3013 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2,
3014 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
3015 );
3016 @endcode
3017 **/
3018 #define CPUID_SOC_VENDOR_BRAND_STRING2 0x02
3019
3020 /**
3021 CPUID SoC Vendor Information
3022
3023 @param EAX CPUID_SOC_VENDOR (0x17)
3024 @param ECX CPUID_SOC_VENDOR_BRAND_STRING3 (0x03)
3025
3026 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type
3027 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3028 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type
3029 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3030 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type
3031 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3032 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type
3033 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3034
3035 <b>Example usage</b>
3036 @code
3037 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;
3038 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;
3039 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;
3040 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;
3041
3042 AsmCpuidEx (
3043 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3,
3044 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
3045 );
3046 @endcode
3047 **/
3048 #define CPUID_SOC_VENDOR_BRAND_STRING3 0x03
3049
3050
3051 /**
3052 CPUID Extended Function
3053
3054 @param EAX CPUID_EXTENDED_FUNCTION (0x80000000)
3055
3056 @retval EAX Maximum Input Value for Extended Function CPUID Information.
3057 @retval EBX Reserved.
3058 @retval ECX Reserved.
3059 @retval EDX Reserved.
3060
3061 <b>Example usage</b>
3062 @code
3063 UINT32 Eax;
3064
3065 AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);
3066 @endcode
3067 **/
3068 #define CPUID_EXTENDED_FUNCTION 0x80000000
3069
3070
3071 /**
3072 CPUID Extended Processor Signature and Feature Bits
3073
3074 @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001)
3075
3076 @retval EAX CPUID_EXTENDED_CPU_SIG.
3077 @retval EBX Reserved.
3078 @retval ECX Extended Processor Signature and Feature Bits information
3079 described by the type CPUID_EXTENDED_CPU_SIG_ECX.
3080 @retval EDX Extended Processor Signature and Feature Bits information
3081 described by the type CPUID_EXTENDED_CPU_SIG_EDX.
3082
3083 <b>Example usage</b>
3084 @code
3085 UINT32 Eax;
3086 CPUID_EXTENDED_CPU_SIG_ECX Ecx;
3087 CPUID_EXTENDED_CPU_SIG_EDX Edx;
3088
3089 AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32);
3090 @endcode
3091 **/
3092 #define CPUID_EXTENDED_CPU_SIG 0x80000001
3093
3094 /**
3095 CPUID Extended Processor Signature and Feature Bits ECX for CPUID leaf
3096 #CPUID_EXTENDED_CPU_SIG.
3097 **/
3098 typedef union {
3099 ///
3100 /// Individual bit fields
3101 ///
3102 struct {
3103 ///
3104 /// [Bit 0] LAHF/SAHF available in 64-bit mode.
3105 ///
3106 UINT32 LAHF_SAHF:1;
3107 UINT32 Reserved1:4;
3108 ///
3109 /// [Bit 5] LZCNT.
3110 ///
3111 UINT32 LZCNT:1;
3112 UINT32 Reserved2:2;
3113 ///
3114 /// [Bit 8] PREFETCHW.
3115 ///
3116 UINT32 PREFETCHW:1;
3117 UINT32 Reserved3:23;
3118 } Bits;
3119 ///
3120 /// All bit fields as a 32-bit value
3121 ///
3122 UINT32 Uint32;
3123 } CPUID_EXTENDED_CPU_SIG_ECX;
3124
3125 /**
3126 CPUID Extended Processor Signature and Feature Bits EDX for CPUID leaf
3127 #CPUID_EXTENDED_CPU_SIG.
3128 **/
3129 typedef union {
3130 ///
3131 /// Individual bit fields
3132 ///
3133 struct {
3134 UINT32 Reserved1:11;
3135 ///
3136 /// [Bit 11] SYSCALL/SYSRET available in 64-bit mode.
3137 ///
3138 UINT32 SYSCALL_SYSRET:1;
3139 UINT32 Reserved2:8;
3140 ///
3141 /// [Bit 20] Execute Disable Bit available.
3142 ///
3143 UINT32 NX:1;
3144 UINT32 Reserved3:5;
3145 ///
3146 /// [Bit 26] 1-GByte pages are available if 1.
3147 ///
3148 UINT32 Page1GB:1;
3149 ///
3150 /// [Bit 27] RDTSCP and IA32_TSC_AUX are available if 1.
3151 ///
3152 UINT32 RDTSCP:1;
3153 UINT32 Reserved4:1;
3154 ///
3155 /// [Bit 29] Intel(R) 64 Architecture available if 1.
3156 ///
3157 UINT32 LM:1;
3158 UINT32 Reserved5:2;
3159 } Bits;
3160 ///
3161 /// All bit fields as a 32-bit value
3162 ///
3163 UINT32 Uint32;
3164 } CPUID_EXTENDED_CPU_SIG_EDX;
3165
3166
3167 /**
3168 CPUID Processor Brand String
3169
3170 @param EAX CPUID_BRAND_STRING1 (0x80000002)
3171
3172 @retval EAX Processor Brand String in type CPUID_BRAND_STRING_DATA.
3173 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3174 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3175 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3176
3177 <b>Example usage</b>
3178 @code
3179 CPUID_BRAND_STRING_DATA Eax;
3180 CPUID_BRAND_STRING_DATA Ebx;
3181 CPUID_BRAND_STRING_DATA Ecx;
3182 CPUID_BRAND_STRING_DATA Edx;
3183
3184 AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
3185 @endcode
3186 **/
3187 #define CPUID_BRAND_STRING1 0x80000002
3188
3189 /**
3190 CPUID Processor Brand String for CPUID leafs #CPUID_BRAND_STRING1,
3191 #CPUID_BRAND_STRING2, and #CPUID_BRAND_STRING3.
3192 **/
3193 typedef union {
3194 ///
3195 /// 4 ASCII characters of Processor Brand String
3196 ///
3197 CHAR8 BrandString[4];
3198 ///
3199 /// All fields as a 32-bit value
3200 ///
3201 UINT32 Uint32;
3202 } CPUID_BRAND_STRING_DATA;
3203
3204 /**
3205 CPUID Processor Brand String
3206
3207 @param EAX CPUID_BRAND_STRING2 (0x80000003)
3208
3209 @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3210 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3211 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3212 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3213
3214 <b>Example usage</b>
3215 @code
3216 CPUID_BRAND_STRING_DATA Eax;
3217 CPUID_BRAND_STRING_DATA Ebx;
3218 CPUID_BRAND_STRING_DATA Ecx;
3219 CPUID_BRAND_STRING_DATA Edx;
3220
3221 AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
3222 @endcode
3223 **/
3224 #define CPUID_BRAND_STRING2 0x80000003
3225
3226 /**
3227 CPUID Processor Brand String
3228
3229 @param EAX CPUID_BRAND_STRING3 (0x80000004)
3230
3231 @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3232 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3233 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3234 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3235
3236 <b>Example usage</b>
3237 @code
3238 CPUID_BRAND_STRING_DATA Eax;
3239 CPUID_BRAND_STRING_DATA Ebx;
3240 CPUID_BRAND_STRING_DATA Ecx;
3241 CPUID_BRAND_STRING_DATA Edx;
3242
3243 AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
3244 @endcode
3245 **/
3246 #define CPUID_BRAND_STRING3 0x80000004
3247
3248
3249 /**
3250 CPUID Extended Cache information
3251
3252 @param EAX CPUID_EXTENDED_CACHE_INFO (0x80000006)
3253
3254 @retval EAX Reserved.
3255 @retval EBX Reserved.
3256 @retval ECX Extended cache information described by the type
3257 CPUID_EXTENDED_CACHE_INFO_ECX.
3258 @retval EDX Reserved.
3259
3260 <b>Example usage</b>
3261 @code
3262 CPUID_EXTENDED_CACHE_INFO_ECX Ecx;
3263
3264 AsmCpuid (CPUID_EXTENDED_CACHE_INFO, NULL, NULL, &Ecx.Uint32, NULL);
3265 @endcode
3266 **/
3267 #define CPUID_EXTENDED_CACHE_INFO 0x80000006
3268
3269 /**
3270 CPUID Extended Cache information ECX for CPUID leaf #CPUID_EXTENDED_CACHE_INFO.
3271 **/
3272 typedef union {
3273 ///
3274 /// Individual bit fields
3275 ///
3276 struct {
3277 ///
3278 /// [Bits 7:0] Cache line size in bytes.
3279 ///
3280 UINT32 CacheLineSize:8;
3281 UINT32 Reserved:4;
3282 ///
3283 /// [Bits 15:12] L2 Associativity field. Supported values are in the range
3284 /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED to
3285 /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL
3286 ///
3287 UINT32 L2Associativity:4;
3288 ///
3289 /// [Bits 31:16] Cache size in 1K units.
3290 ///
3291 UINT32 CacheSize:16;
3292 } Bits;
3293 ///
3294 /// All bit fields as a 32-bit value
3295 ///
3296 UINT32 Uint32;
3297 } CPUID_EXTENDED_CACHE_INFO_ECX;
3298
3299 ///
3300 /// @{ Define value for bit field CPUID_EXTENDED_CACHE_INFO_ECX.L2Associativity
3301 ///
3302 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED 0x00
3303 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DIRECT_MAPPED 0x01
3304 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_2_WAY 0x02
3305 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_4_WAY 0x04
3306 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_8_WAY 0x06
3307 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_16_WAY 0x08
3308 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL 0x0F
3309 ///
3310 /// @}
3311 ///
3312
3313 /**
3314 CPUID Extended Time Stamp Counter information
3315
3316 @param EAX CPUID_EXTENDED_TIME_STAMP_COUNTER (0x80000007)
3317
3318 @retval EAX Reserved.
3319 @retval EBX Reserved.
3320 @retval ECX Reserved.
3321 @retval EDX Extended time stamp counter (TSC) information described by the
3322 type CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX.
3323
3324 <b>Example usage</b>
3325 @code
3326 CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX Edx;
3327
3328 AsmCpuid (CPUID_EXTENDED_TIME_STAMP_COUNTER, NULL, NULL, NULL, &Edx.Uint32);
3329 @endcode
3330 **/
3331 #define CPUID_EXTENDED_TIME_STAMP_COUNTER 0x80000007
3332
3333 /**
3334 CPUID Extended Time Stamp Counter information EDX for CPUID leaf
3335 #CPUID_EXTENDED_TIME_STAMP_COUNTER.
3336 **/
3337 typedef union {
3338 ///
3339 /// Individual bit fields
3340 ///
3341 struct {
3342 UINT32 Reserved1:8;
3343 ///
3344 /// [Bit 8] Invariant TSC available if 1.
3345 ///
3346 UINT32 InvariantTsc:1;
3347 UINT32 Reserved2:23;
3348 } Bits;
3349 ///
3350 /// All bit fields as a 32-bit value
3351 ///
3352 UINT32 Uint32;
3353 } CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX;
3354
3355
3356 /**
3357 CPUID Linear Physical Address Size
3358
3359 @param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)
3360
3361 @retval EAX Linear/Physical Address Size described by the type
3362 CPUID_VIR_PHY_ADDRESS_SIZE_EAX.
3363 @retval EBX Reserved.
3364 @retval ECX Reserved.
3365 @retval EDX Reserved.
3366
3367 <b>Example usage</b>
3368 @code
3369 CPUID_VIR_PHY_ADDRESS_SIZE_EAX Eax;
3370
3371 AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Eax.Uint32, NULL, NULL, NULL);
3372 @endcode
3373 **/
3374 #define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008
3375
3376 /**
3377 CPUID Linear Physical Address Size EAX for CPUID leaf
3378 #CPUID_VIR_PHY_ADDRESS_SIZE.
3379 **/
3380 typedef union {
3381 ///
3382 /// Individual bit fields
3383 ///
3384 struct {
3385 ///
3386 /// [Bits 7:0] Number of physical address bits.
3387 ///
3388 /// @note
3389 /// If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address
3390 /// number supported should come from this field.
3391 ///
3392 UINT32 PhysicalAddressBits:8;
3393 ///
3394 /// [Bits 15:8] Number of linear address bits.
3395 ///
3396 UINT32 LinearAddressBits:8;
3397 UINT32 Reserved:16;
3398 } Bits;
3399 ///
3400 /// All bit fields as a 32-bit value
3401 ///
3402 UINT32 Uint32;
3403 } CPUID_VIR_PHY_ADDRESS_SIZE_EAX;
3404
3405 #endif